WO1991017613A1

WO1991017613A1 - Correlation process for obtaining an electrical signal

Info

Publication number: WO1991017613A1
Application number: PCT/DE1991/000365
Authority: WO
Inventors: Andreas Wolf
Original assignee: Siemens Aktiengesellschaft
Priority date: 1990-05-03
Filing date: 1991-04-26
Publication date: 1991-11-14
Also published as: DE4014767A1

Abstract

In order to produce error-free signals by correlation of two unipolar binary data streams, each of the data streams [f(n), h(n)] is read into one of two registers (11, 12), and the data in each pair of associated memories (e.g. 3, 13; 4, 14) are exclusively ORed. The intermediate data obtained simultaneously from each exclusive OR operation are summed to form an electrical signal [g(n)]. The process proposed is suitable for use in communications testing, in particular in B-ISDM.

Description

Method for obtaining an electrical signal by correlation

The invention relates to a method for obtaining an electrical signal by correlation between two incoming binary, unipolar data streams.

Such a method can be found in the book "ISDN - The Future Telecommunications Network of the German Bundespost", 1985, edited by P. Kahl, pages 83 and 84; because there it is stated that, in the context of a so-called synchronization of an incoming data stream, an eleven-level Barker code can be used as the synchronization word, the autocorrelation function of which is particularly well suited for the synchronization. Because of its characteristic course, the autocorrelation function makes it easier to find the synchronous word in the incoming data stream during a connection setup. To form an electrical signal corresponding to the autocorrelation function while fulfilling the definition equation for the autocorrelation function, a multiplication of two measured values and then a suation or integration of the individual values obtained by multiplication must be carried out. If one describes two binary, unipolar functions with f (n) and h (n), then the electrical signal £ _ff (n) or £ _hh (n) obtained by autocorrelation can be

described by the following equations.

* _f ? * _f - (vn ..) y = - c- ₁ . .— ^** ^ - f (m + n) f (n) and

*

φ hh ⁽ⁿ ) = c2.

h (m + n) h (n)

with m as the time interval. The cross correlation functions are through the relationships + Op

$ fh ⁽ⁿ ) = c,. _> _ ^ f (m + n) h (n) and

defined in which each time interval describes and c-, ... c. Denote proportionality factors.

To obtain an electrical signal by correlation between two incoming binary, unipolar data streams, a multiplicity of multiplications with subsequent summation must therefore be carried out, which also requires a relatively large amount of time, even when using very fast computers. Incidentally, when multiplying or adding certain sections from the incoming binary data streams, multiplication does not always give unambiguous statements, as can be illustrated, for example, by multiplying the data sequence 1010 by 1010 and the data sequence 1010 by 1111 in both cases the product is size 1010, the sum of which is always two; in spite of binary sizes multiplied with one another, the same correlation value results.

The invention is therefore based on the object of specifying a method for obtaining an electrical signal by correlation between two incoming binary, unipolar data streams, with which a clear electrical signal can be obtained quickly and in terms of its size.

To achieve this object, according to the invention, in such a method, the data streams are read into a register and the data are linked to one another in the memory locations of the two registers which are assigned to one another according to an exclusive OR function; the intermediate data resulting from the linking at the same time are formed to form the electrical signal summed.

An essential advantage of the method according to the invention is that the multiplicity of multiplications which have to be carried out according to the definition equation of the correlation functions can be dispensed with in order to obtain an electrical signal corresponding to the correlation function. Due to the merely necessary linking in the manner of an exclusive OR function, the method according to the invention can be carried out in a comparatively very short time and, moreover, as will be demonstrated below, offers the advantage of an electrical signal that is largely error-free because of its clear statements.

If the method according to the invention is carried out in the manner specified above, the electrical signal obtained does not exactly represent the signal expected by correlation between the two incoming data streams as defined, but rather forms a negated correlation result. Since such a correlation result can be regarded as a usable electrical signal to be further processed in some applications, for example in communications measurement technology, the method according to the invention fulfills all the requirements placed in this regard.

An electrical signal which corresponds exactly to the definition equations for the correlation functions results in a further embodiment of the method according to the invention, in which the intermediate data resulting from the links are negated before summation. The electrical signal obtained in this way then represents a correlation result in accordance with the equations given above and is merely provided with a constant offset which is not disruptive for further processing.

Often one of the two bipolar, binary data currents, between which a correlation is to be carried out, as a constant reference sequence. In this case, when carrying out the method according to the invention, it is advantageous if the constant reference sequence is firmly written into one of the two registers. Then only the other binary data stream has to be read into the other register.

The method according to the invention can be carried out with circuit arrangements of different types. However, it is considered to be particularly advantageous if a circuit arrangement is used in which the memory locations of the registers which are assigned to one another in each case are connected on the output side to the inputs of an exclusive-OR element and in which the output of each exclusive-OR is used Member is connected to an input of a summer. This circuit arrangement then supplies a correlation result which, with regard to a result calculated in accordance with the definition equations, represents a negated result; it is also provided with a constant offset.

If, according to an advantageous embodiment of the circuit arrangement according to the invention, a negator is arranged upstream of each input of the summer, an electrical signal results which, apart from a constant offset, corresponds exactly to the definition equations.

In the circuit arrangement according to the invention, the summer can be constructed in different ways; In an advantageous embodiment, the adder consists of a cascade-like structure of several adders, each with eight inputs, of which the adders arranged on the input side are each acted upon at their two LSB inputs, while further adders each have two input-side or upstream adders are each connected via a bus line and each with a downstream additional adder via a further bus line. In another advantageous embodiment of the summer, the summer is an operational amplifier connected as a reversing adder, which is provided with input resistances of the same size. The particular advantage of a summator constructed in this way is that summation can be carried out with it in a relatively short time.

Another digital version of a summer has a shift register on the input side, the inputs of which are connected to the outputs of the exclusive-OR elements and which is connected to a clock generator; a counter is arranged on the output side of the shift register.

To explain the invention, FIG. 1 shows an embodiment of a circuit arrangement for carrying out the method according to the invention, FIG. 2 shows an embodiment of a summer in the circuit arrangement according to FIG. 1, and FIG. 3 shows another embodiment for a summer.

As can be seen in FIG. 1, a binary, unipolar data stream f (n) is fed to an input 1 of a circuit arrangement 2 for carrying out the method according to the invention. The individual data of this data stream are successively shifted through the individual memory locations 3 to 10 of a register 11. Another register 12 has a corresponding number of memory locations 13 to 20, into which the data of a further binary, unipolar data stream h (n) can be read via a further input 21. In the exemplary embodiment shown, a fixed reference sequence h (n) is permanently written into the further register 11.

Memory locations 3 and 13, 4 and 14, etc. of registers 11 and 12, each associated with one another, are connected to the inputs of an exclusive-OR gate 22, 23 and 24 to 29, respectively. The outputs of the exclusive-OR elements 22 to 29 are each connected via a negator 30 to 37 to inputs 38 to 45 of a summer 46. An output 47 of summer 46 results in an electrical signal g (n) which represents the correlation result between the data streams f (n) and h (n).

As can be seen in FIG. 2, the summer 46 shown in FIG. 1 can consist of adders arranged in cascade form, each with two times eight inputs. Input-side adders 50, 51 and 52 and 53 are each connected with their LSB inputs to outputs 38 to 45 of the negators 30 to 37. At the outputs of the input-side adders 50 and 51 of the further input-side adders 52 and 52 there are adders 58 and 59 arranged downstream via bus lines 54 and 55 or 56 and 57, which in turn are followed by an additional adder 62 via bus lines 60 and 61 . The correlation result g (n) then results in digital form at the output 63 of the summer.

In the exemplary embodiment according to FIG. 3, the summer 46 according to FIG. 1 is provided on the input side with a shift register 70 which is connected to the outputs 38 to 45 of the negators 30 to 37. The shift register 70 is connected to a clock generator (not shown) via a clock input 71. On the output side, the shift register 70 is connected to a counter 72, at whose output 73, which is formed by a bus line, the electrical signal g (n) is present in digital form.

Claims

1. A method for obtaining an electrical signal by correlation between two incoming binary, unipolar data streams (f (n), h (n)), characterized in that the data streams (f (n), h (n)) each in a register ( 11, 12) are read in, that the data are linked to each other in memory locations (for example 3, 13; 4, 14) of the two registers (11, 12) which are assigned to one another after an exclusive OR function and that the result is the interrelationships resulting at the same time from the links are summed to form the electrical signal (g (n)).

2. The method of claim 1, d a d u r c h g e k e n n z e i c h n e t that the intermediate data resulting from the links are negated before summing.

3. The method according to claim 1 or 2, characterized in that one (h (n)) of the two bipolar, binary data streams (f (n), h (n)) as a constant reference sequence in one (12) of the two registers (11 , 12) is registered.

4. Circuit arrangement for carrying out the method according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that each associated memory locations (z. B. 3, 13;

4, 14) of the registers (11, 12) on the output side are connected to the inputs of an exclusive OR gate (22 ... 29) and that the output of each exclusive OR gate (22 ... 29) is connected to a Input (38 ... 45) of a totalizer (46) is connected.

5. Circuit arrangement according to claim 4, d a d u r c h g e k e n n z e i c h n e t that each input (38 ... 45) of the summer (46) has a negator

(30 ... 37) is upstream.

6. Circuit arrangement according to claim 4 or 5, characterized in that the summer consists of a cascade-like structure of a plurality of adders (50, 51, 52, 53, 58, 59, 62) each having eight inputs, of which the adder arranged on the input side (50 , 51; 52, 53) are each applied to their two LSB inputs, while further adders (58, 59) each with two input-side or upstream adders (50, 51; 52, 53) via a bus line (54 , 55; 56, 51) and are each connected to a downstream additional adder (62) via a further bus line (60, 61).

7. Circuit arrangement according to claim 4 or 5, so that the summator is an operational amplifier connected as a reversing adder, which is provided with input resistors of the same size.

8. Circuit arrangement according to claim 4 or 5, characterized in that the adder on the input side has a shift register (70), the inputs (38 ... 5) of which are connected to the outputs of the exclusive OR gates (22 ... 29) and that is connected to a clock generator, and that a counter (72) is arranged downstream of the shift register (70).