[go: up one dir, main page]

WO1991013392A3 - Easily configurable fully differential fast logic circuit - Google Patents

Easily configurable fully differential fast logic circuit Download PDF

Info

Publication number
WO1991013392A3
WO1991013392A3 PCT/US1991/000987 US9100987W WO9113392A3 WO 1991013392 A3 WO1991013392 A3 WO 1991013392A3 US 9100987 W US9100987 W US 9100987W WO 9113392 A3 WO9113392 A3 WO 9113392A3
Authority
WO
WIPO (PCT)
Prior art keywords
fully differential
sum
logic circuit
differential
cout
Prior art date
Application number
PCT/US1991/000987
Other languages
French (fr)
Other versions
WO1991013392A2 (en
Inventor
James Hesson
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of WO1991013392A2 publication Critical patent/WO1991013392A2/en
Publication of WO1991013392A3 publication Critical patent/WO1991013392A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H03K19/09429—Multistate logic one of the states being the high impedance or floating state
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3876—Alternation of true and inverted stages

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Mathematical Optimization (AREA)
  • Logic Circuits (AREA)

Abstract

Fast CMOS fully differential logic circuitry, using only tristatable buffers, and capable of as low as a single transistor propagation delay. The preferred embodiment of the invention includes four tristatable buffers (A1, A2, A3, and A4) connected together in such a way as to have multiple differential inputs and one differential output. Different configurations of the output and inputs make different logic functions available. An alternate embodiment combines three of these logic circuits to make a fully differential 3-input full adder, generating sum (SUM/SUM*) and carry outputs (COUT/COUT*) within two transistor delays.
PCT/US1991/000987 1990-02-12 1991-02-12 Easily configurable fully differential fast logic circuit WO1991013392A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US47890690A 1990-02-12 1990-02-12
US478,906 1990-02-12

Publications (2)

Publication Number Publication Date
WO1991013392A2 WO1991013392A2 (en) 1991-09-05
WO1991013392A3 true WO1991013392A3 (en) 1991-10-31

Family

ID=23901864

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1991/000987 WO1991013392A2 (en) 1990-02-12 1991-02-12 Easily configurable fully differential fast logic circuit

Country Status (1)

Country Link
WO (1) WO1991013392A2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4718035A (en) * 1984-05-24 1988-01-05 Kabushiki Kaisha Toshiba Logic operation circuit having an exclusive-OR circuit
US4718579A (en) * 1986-05-27 1988-01-12 General Foods Corporation Beverage dispensing machine
US4740907A (en) * 1984-03-29 1988-04-26 Kabushiki Kaisha Toshiba Full adder circuit using differential transistor pairs
US4749886A (en) * 1986-10-09 1988-06-07 Intersil, Inc. Reduced parallel EXCLUSIVE or and EXCLUSIVE NOR gate
US4870609A (en) * 1986-11-13 1989-09-26 Mitsubishi Denki Kabushiki Kaisha High speed full adder using complementary input-output signals

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4740907A (en) * 1984-03-29 1988-04-26 Kabushiki Kaisha Toshiba Full adder circuit using differential transistor pairs
US4718035A (en) * 1984-05-24 1988-01-05 Kabushiki Kaisha Toshiba Logic operation circuit having an exclusive-OR circuit
US4718579A (en) * 1986-05-27 1988-01-12 General Foods Corporation Beverage dispensing machine
US4749886A (en) * 1986-10-09 1988-06-07 Intersil, Inc. Reduced parallel EXCLUSIVE or and EXCLUSIVE NOR gate
US4870609A (en) * 1986-11-13 1989-09-26 Mitsubishi Denki Kabushiki Kaisha High speed full adder using complementary input-output signals

Also Published As

Publication number Publication date
WO1991013392A2 (en) 1991-09-05

Similar Documents

Publication Publication Date Title
US5023484A (en) Architecture of high speed synchronous state machine
US6469541B2 (en) Exclusive Or/Nor circuit
CA1257344A (en) Dual domino cmos logic circuit, including complementary vectorization and integration
US7372299B2 (en) Differential clock tree in an integrated circuit
US5920202A (en) Configurable logic element with ability to evaluate five and six input functions
CA2235047A1 (en) A dynamic current mode logic family
JP3185727B2 (en) Programmable function block
KR960009247B1 (en) Data output buffer of semiconductor integrated circuit
TW359027B (en) CMOS digital level shift circuit
JP2685203B2 (en) Delay circuit
US6362648B1 (en) Multiplexer for implementing logic functions in a programmable logic device
US5773995A (en) Digital multiplexer circuit
KR940000253Y1 (en) Nmos exclusive or gate circuit
JPH0993116A (en) Semiconductor integrated circuit
Kandpal et al. Design of low power and high speed XOR/XNOR circuit using 90 nm CMOS technology
TW344030B (en) Integrated circuit having Schmitt input circuits
US6965251B1 (en) Input buffer with hysteresis option
WO1991013392A3 (en) Easily configurable fully differential fast logic circuit
US6724225B2 (en) Logic circuit for true and complement signal generator
US6957245B2 (en) Ultra-fast adder
EP0647030A2 (en) Integrated circuit devices
WO1994021046A1 (en) Complementary macrocell feedback circuit
JP2004153690A (en) Tri-state buffer circuit
KR0146237B1 (en) Full adder
KR100278992B1 (en) Full adder

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): DE GB JP

AK Designated states

Kind code of ref document: A3

Designated state(s): DE GB JP

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642