WO1988009554A1

WO1988009554A1 - Process and arrangement for self-checking of a word-oriented ram

Info

Publication number: WO1988009554A1
Application number: PCT/DE1988/000256
Authority: WO
Inventors: Johann Maierhofer
Original assignee: Siemens Aktiengesellschaft
Priority date: 1987-05-29
Filing date: 1988-04-29
Publication date: 1988-12-01
Also published as: DE3718182A1

Abstract

The RAM self-check is performed using a test algorithm in the following steps: in the word-oriented storage cells, the corresponding addresses are stored consecutively in a given sequence, the stored addresses are then read and compared with the absolute addresses and the inverted addresses are coded simultaneously. The stored inverted addresses are then read in the given sequence and compared with the relevant addresses, and the addresses are again coded simultaneously. This process is then carried out in reverse. Defective functioning of the store can be detected by comparison of the addresses read from the word-oriented storage cells with the relevant addresses.

Description

Method and arrangement for executing a self-test of a word-wise organized RAM

The invention relates to a method and an arrangement for executing a self-test of a word-by-word organized RAM, the memory cells of which are addressable by word.

Through the use of modern development tools for VLSI modules (CAD processes) and advances in technology, complex, hierarchical structures can be integrated on a chip today. Semicustom design systems now also offer the option of accommodating complex circuits such as PLAs, ROMs or RAMs on one chip. Since a large number of VLSI chips contain programmable processors, RAMs are indispensable there. Such RAMs, in which the address data and control signals are not directly accessible through the pins of the chip, are difficult to test if the test patterns have to be set and observed via input / output pins and logic circuits in between. For this reason, very early attempts were made to increase testability by means of special test circuits and thus to reduce test costs.

The test path method, which is increasingly used in logic-oriented VLSI chips, can also be used to test such RAMs. With this technique, addresses, data and control samples are inserted via the test path. The read data can be pushed out again in the same way. The additional hardware effort required for this is small, but the test time increases very much. It is also not possible to test with the operating frequency. The object on which the invention is based is to specify a method and an arrangement with the aid of which a self-test of a RAM can be carried out.

This object is achieved in a method of the type specified at the outset by the steps specified in the characterizing part of patent claim 1.

An arrangement for performing this method results from the characterizing part of patent claim 3.

Further developments of the invention result from the subclaims.

The proposed method and the proposed arrangement for implementation thus completely dispense with a test path. It is sufficient to apply a test signal from the outside and to evaluate the test result signal. The test logic on the chip required for the self-test is ensured by a self-test method during test operation. The additional hardware effort compared to the test path method is compensated for by not using the test path.

The invention is further explained on the basis of an exemplary embodiment which is shown in the figures. 1 shows a block diagram of the arrangement required for testing a RAM, FIG. 2 shows an exemplary embodiment of a RAM, FIG. 3 shows a flowchart of the test method, FIG. 4 shows an embodiment of an address counter, FIG. 5 shows an execution of a data inverter, 6 shows a block diagram of a test control, FIG. 7 shows the sequence control of the test control in the circuit diagram, 8 a clock generator of the test control in the circuit diagram,

9 is a timing chart showing the sequence of a read and write step.

10 and 11 an embodiment of a test circuit,

12 shows the interconnection of several test circuits according to FIGS. 10 and 11.

Before going into the exemplary embodiments, the basics of the memory test are explained. In known memory test methods, test time and degree of error detection play an important role. When selecting a test method and executing it using a self-test, other factors are important:

-The additional test logic for the self-test of a RAM leads to an increase in the chips- it should therefore be as small as possible;

-durc-h the self-test logic, there may be an increase in access times in normal operation. This delay should be kept as low as possible; since the test costs depend on the test time, this must be as short as possible;

-to ensure that the self-test runs correctly, the self-test logic must also be checked.

Despite the special requirements for the self-test, the majority of the errors occurring with static RAMs must be recognized. A RAM memory corresponding to FIG. 2 is assumed to illustrate these errors. 2 has a memory field SP with n (n = 1, 2 ...) segments SGI, SG2 ... SGπ. The memory cells that are used to hold a bit can be addressed word by word and are used to store date words or parts thereof. A data word in the memory SP is controlled via a word decoder WD, are selected via the word lines WL and via a column decoder SPD, via which the memory cells assigned to a data word are selected. Access to a data word in the memory SP takes place via an address A, which consists, for example, of bits, so that 2 ^m data words can be addressed in the memory SP. The word width can be, for example, n bits, so that a memory cell assigned to a data word is provided for each memory segment SG. The addressing of the memory cells in the segment SG can be done with the help of b bits of the address A, so that 2 memory cells per word line can be addressed. The data words to be written into the memory SP are fed to the memory SP according to FIG. 2 via a data bus DI and via a write logic SL via the column decoder SPD; the data words read out are fed to a data bus DA via the column decoder SPD and a reading logic LL. The data bus DI and DA can be combined in a bidirectional data bus.

The RAM memory of Fig. 2 is known, so that its function need not be discussed in detail.

For such a memory model, short circuits, interrupted lines, coupling errors and holding errors should be detected during the test, to the errors, which are based on the fact that a line is, for example, always at logical 1 or at logical 0 (stuck-at O / l -Error). The errors can have different effects in the individual blocks of RAM. Since errors occur most frequently in the memory field, they are discussed in more detail. Many errors in the remaining self-test logic can also be mapped to such errors: one or more memory cells are always 0 or 1. One or more pairs of adjacent memory cells are coupled to one another. This means that when a memory cell is accessed, one of the neighboring memory cells also being affected. This does not require the corresponding coupling in the opposite direction. With this type of coupling, two cases can be distinguished. A coupling on the word lines influences two memory cells on the same bit line. The same value is written in both memory cells. When reading, depending on the technology, this leads to an AND or OR link at the output. In the case of a coupling between the bit line and the inverted bit line of the neighboring cell, these are described with mutually identified data. No linkage takes place during reading, since the column decoder SPD only switches through one bit line.

-One or more memory cells are short-circuited. The content of the memory cells is the one that was last written in one of the memory cells.

One or more memory cells lose their content if other memory cells are accessed after writing to a memory cell.

Neighborhood errors in which more than two memory cells are involved are not considered here. In contrast to dynamic memories, these play a subordinate role in the static memories considered here.

Errors can also occur in the decoder logic, consisting of the word decoder WD and the column decoder SPD. The decoders select the addressed memory cell. A faulty behavior can lead to no, one wrong or several memory cells being selected at the same time: in the word decoder WD either a word line WL is selected continuously or never if there is a stuck-at-0/1 error. This causes the line to either stay on 0 or always 1. Such errors in the column decoder SPD falsify the read and write data.

Short-circuit and coupling errors in the word decoder WD address several memory cells simultaneously. In the ^" column decoder of the SPD, the data bits are linked.

In the write and read logic SL, stuck-at-0/1 errors have the same effect as those in the memory field and are easily recognizable.

Short circuits and coupling errors require different logic levels on physically adjacent data lines in order to recognize them.

In order to recognize the explained errors in the RAM, the following procedure is shown in FIG. 3: In a first step INIT, the respective address WA or a part thereof are successively in a fixed order as data words in the memory assigned to the addresses Cher cells enrolled. For example, the address A = 1 is written into the memory cells which are assigned to this address, then the address two or a part thereof is written into the memory cells which are addressed by this address A = 2 and so on until finally the address An is written into the memory cells which are assigned to this address.

In a second step PH1, the addresses RA stored in the word-wise organized memory cells are successively read out, compared with the assigned address A and at the same time the inverted address A 'is written into the addressed memory cell as data word WA ¹ . Thus, the first memory cell with address A = 1, read out the previously written address RA and then write this address inverted as data word WA '. This takes place again in succession in the specified order until the memory cells assigned to the address AN have been operated in this way.

In the third step PH2, the previously written inverted addresses RA 'are again read out in succession in the specified order, compared with the assigned address and then the correct address is rewritten as data word WA. This takes place again in succession up to the last address AN.

In the fourth step PH3, the process described is repeated in the reverse order. Now on, with the last address started, read out the addressed by this address data RA word in the store SP and with the zugeord¬ Neten address cf. ^e cozy and then data word WA ¹ registered as the inverted address. This continues until at the end the data word addressed by the address AI has been read out in the memory field SP and the inverted address AI has been written in as the data word WA '.

In the last step PHA, the data words RA 'written in step PH3 are again read out in reverse order and compared with the assigned address, and the assigned addresses are then written in again as data word WA.

It is essential that the steps PH in the memory field SP only proceed to the memory cells of the next address when the data word RA or RA ^{1 has been} read out from the memory cells of the previous address and the address WA or WA ^{1 has been written in} as the data word. In this way it is achieved that the influence of other memory cells caused by the writing of the data word WA or WA ¹ due to errors is recognized in the subsequent read operations.

The sequence of addressing the individual memory words in the memory field SP is arbitrary, but a sequence once selected must then be followed.

The addresses of the memory cells assigned to a data word are thus used as the ^" test pattern for checking the RAM. If the data width is smaller than the address width, only part of the address is used as the test pattern. With a wider data word, the address bits are used several times.

The method detects coupling errors and short circuits in the column decoder as well as in the read and write logic. All four bit combinations occur here between any two data bits. Since each memory cell contains the 0 and the 1 at least once during the test, stuck-at-0 / l errors in the memory field SP and on the data lines can be easily recognized. Such errors on the address and word lines are recognized by the control process before each writing of the data word WA. The one-sided couplings can be found by writing both data values 0 and 1 in ascending and descending address direction. These are recognized on the bit and data lines, since all four combinations of data types are created between the data lines. Short circuits are identified even more easily as coupling errors, since they do not have a one-sided effect ¬ write a memory cell and the control reading each other words are addressed. An arrangement for carrying out the self-test in accordance with the described method can be found in FIG. 1. The memory RAM, which can be constructed in accordance with FIG. 2, for example, is already present on the chip. In addition, the self-test logic requires an address counter AZ, a data inverter INV, a test circuit CH, a test controller ST. In addition, a driver stage TR is advantageous and an EXCLUSIVE OR gate AQ1, an OR gate OG and an error flip-flop EFF can be connected to the test circuit CH. The circuits AQ1, OG and E-FF can of course also be contained in the test circuit CH or be implemented in some other way.

With the help of the address counter AZ, addresses A, e.g. generated by 8 bits and fed to the memory RAM via the address bus. Part of this address, e.g. 4 bits are transferred to the memory RAM via a data bus DB. This part AI of the address is then written under the address A in the memory RAM. With the aid of the data inverter INV, this address part AI can be written into the memory RAM under the address A inverted or non-inverted. This address part is simultaneously fed to the test circuit CH via the bus DI. The address part stored in the RAM memory can be read out when addressing with the aid of the address A, can be fed to the test circuit CH via the data bus DA and can be compared there with the address part supplied via the data bus DI. If there are differences in this comparison, then there is an error.

The sequence in the self-test is carried out with the aid of the test control ST, which for this purpose receives control commands STS from the outside.

In the exemplary embodiment, bidirectional data buses DA are used, via which an address part AI is inserted into the memory RAM can be written or this address can be read out of the memory RAM again.

From Fig. 4 it follows, e.g. the address counter AZ can be constructed. The address counter AZ can be a binary counter. 4 shows an implementation with the aid of a feedback shift register. All that is necessary for the method is that a fixed sequence of addresses is run through. However, this must also be able to be traversed in the opposite direction. Such a counter can be easily constructed with a shift register SR, which can be shifted in both directions and loaded in parallel.

The NOR gate NR1, NR2 used in the feedback RL ensures that the O state is inserted in the shift register SR. The output of the shift register SR outputs the addresses A, which are fed to the memory RAM via the address bus ABI. Some of the address lines in the address bus ABI are used for the shift register SR for feedback and lead to an EXOR circuit AQ2, AQ3. A line RL leads from the EXOR circuit AQ2 to the input C-UP of the shift register SR, from the EXOR circuit AQ3 a line RL leads to the input C-DO of the shift register SR. The circuits NR1, AQ2 are in operation when the shift register SR counts up, the circuits NR2, AQ2 are in operation when the shift register SR counts down. Accordingly, lines AK to the EXOR circuit AQ2, lines AK + 1 to the EXOR circuit AQ3 are led from the address lines in the address bus ABI. The order of the addresses A generated by the shift register SR can be determined with the aid of the address lines used from the address A.

The shift register SR can be loaded with an external address AX via the address bus AB, in order then as Address register to be used in normal operation. At the output of the shift register SR, the addresses AO to Am-1 appear, which are fed to the memory RAM via the address bus ABI.

Finally, a circuit SC is also provided, which uses the output signal from the NOR gate NR1, a signal UP to determine the up-counting and the address signal Am-1 to determine whether a run has ended. Control signals are fed to the shift register SR in order to stop its operation. The control signal UP specifies that the shift register counts up, the signal DO specifies that the shift register counts down, the signal RCH specifies that the shift register is reset, the LOAD signal that the shift register with the external address AX is loaded. The shift clock of the shift register SR is determined with the aid of a clock signal CLKA.

An error in the address counter AZ is not recognized itself. However, this has no disadvantageous consequences, since such an error leads to an incorrect data comparison and is therefore recognized in any case. An error either means that only one counting direction is affected or the final state no longer occurs. The first case is recognized when passing through the second direction. The missing end signal is recognized from the outside.

An embodiment of the data inverter INV is shown in FIG. 5. The data inverter INV is connected to address lines of the bus DB, for example for the address AO to An-1, and either outputs the assigned address bit not inverted or inverted as signals DO to Dπ-1 from. There is one for each line EXCLUSIVE OR link AQ5 and a driver link TR provided. With the help of a signal IN it can be determined whether the address bit is inverted or not, with the aid of a signal ENA it can be determined whether an address bit is applied to the memory RAM or not.

This circuit is also not self-checking. Stuck-at errors on the control lines for IN and ENA or on the EXOR outputs, as well as the driver elements, however, mean that data bits are never or permanently inverted. This is recognized in the test circuit. A stuck-at error at the address input of the EXOR gate AQ5 is not recognized because the input is inverted correctly. A single error does not disturb the method, however, since a complementary data combination still occurs between this data line and the other data lines. The inverter INV can be used in the form shown.

The sequence of the self-test is controlled by the test control ST. This is according to the block diagram of FIG. ^'6 from a sequence control KA and a timing generator TG. Control signals STS are supplied to the test control from the outside, such as a clock signal CLK, a signal TM for setting the test mode, a signal R / W to determine whether writing or reading is carried out and a signal RN for resetting the circuits of the Test logic. Furthermore, the end signal E is supplied by the binary counter. The test controller generates clock signals CLKA, CLKB, internal write and read signals R / WI, a trigger signal ENA and a reset signal RCH from these control signals. The test controller also generates control signals such as the control signal UP for the upward counting of the address counter, the control signal DO for the downward counting, the control signal IN for the inversion of the data inverter and the signal TE for the end of the test. Finally there the sequence control KA signals YO through Y3, which are fed to the test circuit CH and which enables the test circuit to determine whether the test control part ST is working correctly.

A circuit diagram of the clock generator TG is shown in FIG. 8, and a circuit diagram of the sequence control KA is shown in FIG. 7. The circuit diagrams are constructed using conventional components. Furthermore, the signals are drawn in, so that the circuit diagrams of FIGS. 7 and 8 can be used to easily determine how the signals STS and the end signal E are generated from the control signals STS and the end signal E which are output at the output of the test controller.

The time diagram of FIG. 9 shows once again how a reading step and a writing step follow one another. The reading step is denoted by R, the writing step by W. The write step W is followed by a recovery phase RG for the memory. The data comparison between the read address and the assigned address is carried out at point DV. It can be seen from the time diagram how address A is created as a function of the clock signal CLKA and how data DI is written and data DA read out. The data comparison D takes place as a function of the clock signal CLKB. The R / WI signal determines whether reading or writing is carried out.

The test circuit CH can be seen in FIGS. 10 and 11, the interconnection of which is shown in FIG. 12. Since the inverted read data are written back into the RAM, the test circuit must check this inversion. The test signal arrangement RT of FIG. 10 is provided for this. This has two groups of inputs A and B. The inputs A are the address signals which are supplied via the line DI Signals B, the signals which are supplied by the memory RAM via the line DA. The data comparison is carried out in the circuit arrangement of FIG. 10 and it is determined whether there is an error. 10, the two outputs F and G are complementary to one another, as long as all input pairs A, B are complementary and the test circuit does not contain any errors. If there are more inputs than four according to FIG. 10, the circuit arrangement according to FIG. 10 must be interconnected to form a tree according to FIG. 12. A circuit arrangement with 12 inputs is shown there.

The test circuit CH also includes a circuit arrangement CH1 for checking that the test control ST is free of errors. This is carried out according to FIG. 11. The test controller controls the individual steps of the test method with the aid of a two out of four codes. It requires six code words, which can be constructed in such a way that an error in one code word always means that this code word does not lead to another permitted code word. 11, the four bits Y0 to Y3 of the code words are checked to determine whether they belong to an allowed code word or to an illegal code word. The output signals ZI and Z2 of this circuit arrangement are also fed to a test signal circuit RT in accordance with FIG. 10. The signals F, G are evaluated by the EXCLUSIVE OR circuit AQ1 and lead to the setting of the error flip-flop E-FF if an error signal is present. This then outputs the error signal G0.

The self-test procedure described offers significant advantages for RAM memories that are not directly accessible from the outside via connection pins: No access to the RAM via external connections is necessary,

-the test is carried out at the operating frequency, -it can be integrated into a system test.

The self-test hardware should as far as possible not influence the normal operation of the RAM. However, all test path technologies start from input and output registers in the data path, which can worsen the access times. The procedure described here does not require a test bus or data register. Therefore normal operation is not affected.

Due to the implicit checking of the test logic during the test run, in contrast to other techniques, no special checking of the test hardware is necessary. The method is therefore a very simple and effective method for checking RAMs.

Claims

1. Method for executing a self-test of a word-wise organized RAM, the memory cells of which can be addressed word-by-word, by the following steps:

for all addresses, the respective address or a part thereof is written into the memory cells addressed by a respective address as a data word and this in succession for all addresses in a fixed order, the address stored under the respective address as a data word is read out and with the compare the respective address and then write the respective address in inverted form into the memory cells addressed by the respective address and this is carried out for all addresses in succession in a fixed order, the inverted address stored under the respective address being selected as a data word read out the memory cells addressed by the respective address and compare them with the respective address and then write the respective address back into these memory cells and this is carried out successively for all addresses in the specified order,

the data words stored under the respective addresses are read out successively, but in reverse order, from the individual memory cells addressed by the respective addresses and compared with the respective addresses, and the inverted respective addresses are written in at the same time,

the data words are read out word by word in succession in reverse order from the memory cells addressed by the respective addresses and compared with the respective address and at the same time the respective address is written again.

2. The method according to claim 1, characterized in that the data words respectively read out from the memory cells are each compared with the addresses to be written into the memory cells as the next address.

3. Arrangement for performing the method according to claim 1 or 2, based on the following features:

an address counter (BZ) is provided for the sequential generation of addresses for the RAM, which are used for word-by-word control of the memory cells in the RAM, a data inverter is provided for inverting the addresses or parts thereof,

a test circuit (CH) is provided which compares the respective address with the address read from the memory and emits a test signal as a function of the comparison result,

-A test control (ST) is provided which controls the course of the test.

4. Arrangement according to claim 3, characterized in that the test controller (ST) uses code words in a two out of four code, which are constructed in such a way that an error can be recognized.

5. Arrangement according to claim 3 or 4, g e k e n n z e i c h n e t by the following features:

the address counter (AZ) is connected to the address inputs of the RAM via an address bus (ABI),

a bus (DB) leads from the address bus (ABI) to the data inverter (INV), - the output of the data inverter (INV) is via a bus (DI) both with the test circuit (CH) and via a driver (TR) connected to the data input of the RAM, - the data output of the RAM is connected to the test circuit (CH) via a bus (DA).