WO1988009036A2

WO1988009036A2 - Vlsi chip

Info

Publication number: WO1988009036A2
Application number: PCT/GB1988/000348
Authority: WO
Inventors: Ali Gamal Eldin; Mohamed Ibrahim Elmasry
Original assignee: University of Waterloo
Current assignee: University of Waterloo
Priority date: 1987-05-04
Filing date: 1988-05-04
Publication date: 1988-11-17
Anticipated expiration: 1989-11-04
Also published as: JPH02504335A; WO1988009036A3; EP0358668A1

Abstract

The disclosure relates to the JCMOS memory cell, which includes a bipolar transistor for WRITing a charge into the cell's capacitor, and a JFET for (non-destructive) READing. The disclosure describes the need for special measures for isolating the JCMOS memory cells, to enable them to be used with CMOS technology on a common substrate. In the ''physical barrier'' isolation, as disclosed, trenches (19) are formed between the respective sources (34) of the JCMOS cells. Other trenches (100) are provided to separate the drains (36) of adjacent columns of cells. In the ''island diffusion'' isolation, as disclosed, each JCMOS cell is placed on a grounded island-substrate (97), and the IGFET (29) of the CMOS pair that has its channel of the opposite polarity material to that of the overall chip substrate (99) is formed in a well (26) which is separated from the overall substrate by a deep island-implant (25). The overall substrate (99) and the deep implant (25) are both electrically floating.

Description

VLSI Chip

The article "A Novel JCMOS Dynamic RAM Cell for VLSI Memories", by Ali G Eldin and Mohamed I Elmasry (published in the IEEE Journal of Solid-State Circuits, Vol SC-20, No 3, June 1985), describes the construction and operation of a memory cell which is used as a component in a VLSI dynamic RAM integrated chip. The cell as described therein has come to be known as the JCMOS memory cell.

Irrespective of what kind of memory cell is used, for low overall power consumption and high operational speeds, it is desirable to use Complementary IGFET (or CMOS) technology on the VLSI chip.

The JCMOS cell is compatible physically with conventional CMOS technology. The kinds and depths of diffusions needed to produce the complementary pairs of IGFETs on the chip are also suitable to produce the JCMOS memory cells. Therefore, the designer of a VLSI chip favours the use of the JCMOS memory cell because the JCMOS cell does not impose a need for more complexity in the production steps, as compared with the established CMOS technology.

Thus, the JCMOS cell is compatible with CMOS technology from the physical or manufacturing point of view. But there are other problems facing, the chip designer who wishes to provide JCMOS cells and complementary pairs of IGFETs on the same chip. The present invention is concerned with recognizing and alleviating these other problems.

The invention will now be introduced and explained with reference to the accompanying Figures, in which:

Fig 1 is a diagram of a JCMOS memory cell;

Fig 2 is an electrical circuit diagram of the JCMOS cell;

Figs 3A and 3B are the same diagram of an array of JCMOS memory cells on a chip, showing the connecting lines, and show the voltages on the lines during a WRITE and a READ operations, respectively;

Fig 4 shows a column of JCMOS cells connected to a sense-amplifier;

Fig 5 is a cross-section showing two JCMOS memory cells and a complementary pair of IGFETs formed on a common substrate;

Fig 6 is a plan of a practical layout, which embodies the invention, of an array of JCMOS cells, which are separated from each other by physical barriers;

Fig 7 is a section on line 7-7 of Fig 6; Fig 8 is a section on line 8-8 of Fig 6;

Fig 9 is a section of a JCMOS cell which is formed in an island diffusion - - an arrangement which embodies the invention;

Fig 10 shows pairs of JCMOS cells, each pair in a respective island diffusion;

Fig 11 shows a complementary pair of IGFETs and a JCMOS memory cell formed in a common substrate;

and Fig 12 shows a preferred way of forming the JCMOS cells and the complementary pair of IGFETs in an overall substrate.

Fig 1 is a diagram of the the physical layout of a single JCMOS cell. The cell includes a p-substrate 37 into which are diffused an n+ source 34 and an n+ drain 36. An n-diffused layer 35 constitutes a channel between the source and the drain, and is surmounted by a p-diffused layer 32. A layer of oxide 31 (or other insulating material) surmounts the layer 32, and a gate or plate 30 of metal (or other conducting material) resides on top of that.

The equivalent circuit diagram of the JCMOS cell is shown in Fig 2. The regions 30, 31, 32 make up a capacitor, which either does or does not hold a charge, depending on whether the cell is storing a "0" or a "1".

The regions 32, 35, 37 make up a bipolar transistor, which, when turned on, allows a charge to be placed on, or removed from, the capacitor. Turning on this bipolar transistor therefore allows a WRITE operation to be performed on the cell.

The regions 34, 35, 36 make up an n-channel junction-gate field-effect transistor. The gate of the JFET comprises the bottom plate 32 of the capacitor. This JFET is arranged to either conduct or not conduct depending on whether the capacitor is or is not charged. The READ operation is carried out by applying a potential difference between the source 34 and drain 36 of the JFET, and by then sensing whether a current flows through the channel 35 of the JFET.

(It may be noted that the READ operation on the JCMOS cell is non-destructive, in that the capacitor's condition remains unchanged during and after a READ operation.)

Each cell is connected, as shown in Fig 2, to three lines: the WRITE-BIT-LINE 58, the WORD-LINE 50, and the READ-BIT-LINE 53. Figs 3A and 3B show several of the cells arranged together on the chip. The BIT-LINEs connect the cells together in columns 75,76,78,79 and the WORD-LINEs connect the cells together in rows 71,72,73.

Fig 3A shows the voltages on the lines during a READ operation. Fig 3B shows the same thing during a WRITE operation. The cell 74 is the "selected" cell in both cases.

The READ-BIT-LINEs 53 are connected to sensors, ie to sense-amplifiers, during a READ operation. The JFET in the selected JCMOS cell either does or does not conduct a voltage to the respective sense-amplifier on the particular READ-BIT-LINE, depending upon the stored state of the cell. Fig 4 shows the arrangement of the sense-amplifier 90 of the column defined by the READ-BIT-LINE 53.

Each sense-amplifier 90 contains a complementary pair of insulated-gate field-effect transistors 92,93. The physical arrangement of these transistors, as diffused onto the chip, is shown in Fig 5. Transistor 92 is a p-channel IGFET, and transistor 93 is an n-channel IGFET. Also shown in Fig 5 are two of the JCMOS memory cells, one being the "selected" cell 74, and the other being the adjacent cell from the row 78.

Conventional CMOS operation requires that the substrate (in the case of a p-substrate 80) be the most-negative region of the chip, for the following reason. In the n-channel IGFET 93, the Source 89 and Drain 87 diffusions cannot be allowed to go negative with respect to the substrate 80, because if that happened the diffusion 87,89 would be forward-biassed with respect to the substrate 80: all the other diffusions in the vicinity are reverse-biassed with respect to the substrate, so that the presence of a forward-biassed diffusion would immediately give rise to a parasitic bipolar transistor action.

In the p-channel IGFET 92, the n-well 86 must never go negative with respect to the substrate 80, for the same reason. Similarly, the p-diffusions comprising the Source 84 and Drain 85 of the p-IGFET 92 should never go positive with respect to the n-well 86.

CMOS technology normally requires that none of the p-n junctions ever become forward-biassed. In CMOS technology, if a p-type substrate is to be at ground voltage, the designer must see to it that the diffusions can only be connected to voltages that are positive.

As far as the design of a VLSI memory chip is concerned, the use of CMOS technology is virtually mandatory, because the designer needs the very small energy dissipation feature of a complementary pair of IGFETs. The JCMOS memory cell however requires that during the WRITE operation a negative voltage (ie negative with respect to the p-substrate) be connected, via the WORD-LINE 50 to the Source 34 of the selected cell 74. It is this negative voltage which turns on the bipolar transistor of the cell, allowing the capacitor to be charged or discharged. The Source 34 of the selected cell (and of all the other cells on the same WORD-LINE) is therefore forward-biassed with respect to the (grounded) substrate 37 during a WRITE operation.

Thus, it may be considered that the JCMOS cell, though physically compatible with CMOS technology, is electrically incompatible. If, during a WRITE operation in the JCMOS cell, there were to exist in the vicinity any reverse-biassed n-diffusions, a parasitic bipolar transistor action would immediately ensue - - and in fact, there are of course many such reverse-biassed n-diffusions in the CMOS pairs of IGFETs, which will act as collectors for the electrons emitted from the forward-biassed regions.

It may be seen from Fig 5 that when the n-type Source 34 is forward-biassed, there also might occur a parasitic silicon-controlled-rectifier action. This would take place between the following four regions: the n-type Source 34, the p-substrate 37, and the n-well 86 and the p-type Source diffusion 96 of the p-channel IGFET 92. Such a parasitic SCR action, if it occurred, could be disastrous to the chip, in that SCR conduction, once established, can become latched into the chip. Again, this possibility of SCR latch-up would seem to indicate that the JCMOS cell is incompatible with CMOS technology.

It should also be noted that only one particular WORD-LINE 50 is set negative during a WRITE operation. The other WORD-LINEs 39,51 are all set positive during a WRITE. Therefore, although the Sources of the cells on the selected WORD-LINE 50 are forward-biassed, the Sources of all the other cells, including those on the WORD-LINEs 39,51 immediately adjacent to the selected WORD-LINE, are all reverse-biassed. Again, a parasitic transistor action would be expected.

The invention is concerned with the recognition that the JCMOS cell can, contrary to these indications, be incorporated into the same chip as IGFETs that are arranged in CMOS complementary pairs.

In the invention, the chip is provided with a means for electrically isolating the respective Source diffusion (ie the diffusion connected to the respective WORD-LINE) of each JCMOS cell, at a time when the said diffusion is forward biassed with respect to a second diffusion (being a diffusion of opposite polarity, and contiguous with the Source diffusion) of the chip, from all diffusions on the chip that are contiguous with, and reverse-biassed with respect to, the said second diffusion.

It is recognized, in the invention, that the JCMOS cell Sources can be electrically isolated from each other by imposing a physical barrier between the Sources, ie a barrier of insulating material. Alternatively, it is recognised also that the required Isolation can be achieved by forming the JCMOS cells and the CMOS IGFETs in respective island-diffusions, which are allowed to float electrically.

Both of these ways of isolating the forward-biassed Sources will now be described in more detail.

First described is the "physical barrier" means for isolating the Sources of the JCMOS cells. Fig 6 is a plan view of a section of a chip, showing part of an array of JCMOS memory cells. The Sources 5,6,7,8 on any one WORD-LINE 50 are all isolated from the Sources 45,46,47,48, 65,66,67,68 on the other WORD-LINEs 39,51 by the insulators 10.

Fig 7 is a sectional view along line 7-7 of Fig 6, and Fig 8 is a sectional view along the line 8-8 of Fig 6. The insulators 10 comprise Source-separating trenches 19, which are cut (ie etched) or otherwise formed into the depth of the silicon of the chip. The trenches are lined with a coating 18 of insulative oxide. The trench 19 is filled in with a filler 17 of, for example, polysilicon. The filler 17 is just for physical strength; whether the filler is electrically conductive or not is irrelevant.

The trench 19 should be formed deeply into the material of the chip. The trench should be at least as deep, and preferably should be deeper, than the Source diffusions. It may be regarded that the electrons or holes generated by the forward-biassed Sources 5,6,7,8 can reach a reverse-biassed region 45,46,47,48,65,66,67,68 only if the electrons or holes can travel directly in a straight line towards the reverse-biassed region. Thus the deeper the trench 19, the more tortuous the path the electrons or holes are forced to follow to reach a reverse-biassed region.

It may be noted that the layout of the cells as shown in Fig 6 is very efficient as regards the packing density of the cells on the chip. The Figure actually shows the components in substantially the correct scale relative to each other, from which it can be seen that it is meaningful to refer to the area of the cell as being made up of a number of square units of area. Fig 6 shows four cells A,B,C,D in fourteen squares in the direction parallel to the WORD-LINEs, and five cells J,K,L,M,N in ten squares in the direction of the READ- and WRITE-BIT-LINEs. Each cell therefore requires an area of only seven squares, which is a very efficient utilisation of the space.

The Drains 69 of the JCMOS cells are connected to each other in rows, as shown in Fig 6, by the respective READ-BIT-LINEs 52,53,54. The READ-BIT-LINE itself comprises the n+ diffusion. Adjacent READ-BIT-LINEs 52,53 must be electrically insulated, and again isolation trenches 100 are used for this purpose. The adjacent READ-LINEs 52,53 are actually diffused as one unitary region, which is then divided into the two READ-LINEs by the Drain-separating trench 100. The Sources 5,6 also may be formed as one unitary diffusion, which is then broken up into individual Sources by means of the Source-separating trenches 19.

The alternative means, ie the "island-diffusion" means, for isolating the forward-biassed Sources of the JCMOS cells will now be described.

Fig 9 shows a JCMOS memory cell formed on an island diffusion 97 of p-type material, the overall substrate 99 of the chip being of n-type material.

Fig 10 shows a section of the chip in which are located two adjacent pairs of JCMOS cells. Here, each pair of cells resides in an individual well 97,98 of p-type material, rather than the whole substrate being of p-type material. In this case, the cell-substrate 97 is not now unitary with the overall substrate 99 of the chip. The substrate 99 itself is of n-type material. Now, during a WRITE operation, there is no parasitic bipolar path between the forward-biassed Sources of the cells in the selected row 50, and the reverse-biassed Sources of the cells in the nearby unselected rows 39,51.

However, another problem arises in this case. Fig 11 shows a p-channel IGFET 29 formed in the same n-substrate 99 as is shown in Fig 10. The p-type Source 27 and Drain 28 diffusions of the IGFET 29 cannot be allowed to become forward-biassed with respect to the n-substrate 99, so that the n-substrate 99 must be connected to the most positive voltage on the chip. The fact that the n-substrate 99 is therefore more positive than the p-well 97 of the JCMOS cell means that the p-well 97 is reverse-biassed with respect to the substrate 99. Hence a parasitic bipolar action would occur between the n-substrate 99, the p-well 97 of the memory cell, and the n-Source 5,6 of the memory cell, during a WRITE operation.

It is recognised in the invention that the parasitic bipolar action just described can be prevented by allowing the n-substrate 99 to float electrically, ie by connecting the substrate 99 neither to ground, nor to any other voltage level.

However, if the JCMOS cells are formed in grounded p-wells 97, and if the n-substrate 99 is allowed to float electrically, a further problem arises, which may be seen from Fig 11. This problem is that the floating substrate 99 makes it possible for an SCR latch-up path to exist, between the following regions, ie: the p-type Source 27 of the IGFET 29, which is at positive voltage, the floating n-type substrate 99, the grounded p-well 97, and the n-type Source 5,6 of the JCMOS cell, which, during a WRITE operation, is at negative voltage.

It is recognised in the invention that this parasitic SCR action can be prevented by forming the p-channel IGFET 29 in a well 26 of n-type material, and by surrounding that n-well 26 by a deeper well 25 of p-type material. The n-well 26 can be set most-positive, which is compatible with the CMOS technology. The deep p-well 25 is allowed to float electrically, like the n-substrate 99.

Now, there is no SCR path on the chip - - neither during a WRITE operation, when the Source of the p-IGFET is positive and the Source of the JCMOS cell is negative, nor at any other time.

By the two means described, termed herein the "physical barrier" means and the "island diffusion" means, JCMOS memory cells may be provided on the same chip as IGFETs arranged in complementary pairs, without the dangers of parasitic bipolar action, nor of SCR latch-up. The "island diffusion" means is the more reliable, in that with the "physical barrier" means, there is a slight chance that the electrons/holes that are emitted could find their way around or past the trenches. The "island diffusion" means is, in practice, effective to eliminate all spurious bipolar emitters.

In constructing the chips of the invention, the n- and p-type polarities of the material may be reversed.

Claims

CLAIM 1. Integrated circuit chip, characterised:

in that the chip includes many one-bit memory cells;

in that each cell comprises a respective junction-gate field effect transistor (JFET), a respective bipolar transistor, and a respective capacitor;

in that, in plan view, the JFET comprises a respective gate, which is sandwiched between a respective source and a respective drain;

in that the chip also includes insulated-gate field-effect transistors (92,93) which are arranged in complementary pairs;

in that the chip includes a means for causing the source of the JFET of one such memory cell, during normal operation of the cell, to enter a forward-biassed condition, in which the source is forward-biassed relative to the cell-substrate (97,37) upon which that said one cell is directly formed;

in that the chip includes means for preventing, at the time when the source (5) of the said one cell is in the forward-biassed condition, the sources (65) of others of the cells on the chip from being forward-biassed relative to the cell-substrate of the said one cell;

in that each cell on the chip that can enter the forward-biassed condition relative to its respective cell-substrate, is equipped with a respective source isolation means (97,19);

and in that the source isolation means of the said one cell is effective to prevent substantially all the electrons or holes that are emitted from the said forward-biassed source of the said one cell from being collected by the sources of the said other cells.

CLAIM 2. Chip of claim 1, further characterised:

in that each source isolation means comprises a physical barrier around the respective source which directly prevents the transmission of electrons or holes from the said source.

CLAIM 3. Chip of claim 2, further characterised:

in that the said physical barrier comprises a trench (19) formed into the material of the chip;

and in that the trench extends more deeply into the material than does the said source.

CLAIM 4. Chip of claim 3, further characterised:

in that the cells are arranged on the chip in an array of rows (J-N) and columns (A-D);

in that the sources of the cells in one row (K) are connected all to one and the same WORD-LINE (50);

in that the sources of the cells in other rows (J,L) are connected to respective other WORD-LINEs (39,51);

in that adjacent cells in the same row are arranged in an alternating mariner, ie drain-gate-source, source-gate-drain, drain-gate-source ..;

and in that adjacent sources (5,6) in the same row are arranged in a common diffusion into the material of the chip.

CLAIM 5. Chip of claim 4, further characterised:

in that the said trenches comprise source-separating trenches (19); in that the diffusion that comprises a common pair (5,6) of sources in one (K) of the rows is separated from the diffusion that comprises a common pair (65,66) of sources in an adjacent one (L) of the rows by means of a respective one of the source-separating trenches;

and in that the arrangement of the cells is such that the source diffusions are intercalated along the columns with the said source-separating trenches.

CLAIM 6. Chip of claim 5, further characterised:

in that adjacent drains (52,53) in one of the rows (K) are separated by means of respective drain-separating trenches (100);

and in that the drain-separating trenches extend along the length of the respective columns (A-D) of cells.

CLAIM 7. Chip of claim 1, further characterised:

in that the memory cells are formed in island diffusions (97), which are of opposite polarity material from that of the overall substrate (99) of the chip;

and in that the arrangement is such that the sources of cells that are in different rows are on different, separated islands.

CLAIM 8. Chip of claim 7, further characterised:

in. that the overall substrate of the chip is electrically floating.

CLAIM 9. Chip of claim 8, further characterised:

in that the one IGFET (29), of the complementary pair of IGFETs on the chip, which has a channel of the opposite polarity to that of the floating overall substrate (99) of the chip, is formed by diffusing the source (27) and drain (28) of that IGFET (29) into an island (26) of material of the same polarity as the overall substrate (99);

and in that the island (26) is separated and isolated from the overall substrate (99) by means of an implanted diffusion (25) of material of opposite polarity to that of the overall substrate.

CLAIM 10. Chip of claim 9, further characterised:

in that the said implanted diffusion (25) is electrically floating.