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WO1987001006A1 - Agencement de circuit permettant l'alignement, les uns par rapport aux autres, de groupes mic entrant en un point de branchement de communication - Google Patents

Agencement de circuit permettant l'alignement, les uns par rapport aux autres, de groupes mic entrant en un point de branchement de communication Download PDF

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Publication number
WO1987001006A1
WO1987001006A1 PCT/EP1986/000330 EP8600330W WO8701006A1 WO 1987001006 A1 WO1987001006 A1 WO 1987001006A1 EP 8600330 W EP8600330 W EP 8600330W WO 8701006 A1 WO8701006 A1 WO 8701006A1
Authority
WO
WIPO (PCT)
Prior art keywords
output
input
circuit
designed
circuit arrangement
Prior art date
Application number
PCT/EP1986/000330
Other languages
English (en)
Inventor
Francesco Marchelli
Piercarlo Sarto
Original Assignee
Italtel Società Italiana Telecomunicazioni S.P.A.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Italtel Società Italiana Telecomunicazioni S.P.A. filed Critical Italtel Società Italiana Telecomunicazioni S.P.A.
Publication of WO1987001006A1 publication Critical patent/WO1987001006A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
    • H04J3/0629—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators in a network, e.g. in combination with switching or multiplexing, slip buffers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes

Definitions

  • Circuit arrangement to align the PCM groups entering a co ⁇ -munication branch point with another.
  • the present invention relates to a circuit arrangement to align the PCM groups entering a communications branch point (such as a switching matrix) and having a lag that varies from group to group, one another.
  • a communications branch point such as a switching matrix
  • the switching network mentioned above includes three switching stages henceforth respectively indicated with the terms input switching stages, intermediate switching stages and output switching stages.
  • the input switching stages - and/or the output switching stages - can be placed at a distance, from the intermediate switching stages, that for some stages will amount to only a few meters, whilst for others will amount to a hundred odd meters. Therefore the PCM groups entering the intermediate switching stages are affected by lags that differ from group 5 to group according to the distance at which the input switching stages are placed.
  • PCM groups is carried out, the said PCM groups must be aligned so that, at any one moment, the digital words allocated in the nth temporal channel of all the groups are present on the matrix's input.
  • Evaluation of the entity of the lag is usually carried out by using a synchronizing pulse output by a timing unit.
  • the aligning operations referred to above are carried out through means designed to be used in the presence of a lag condition of the PCM signals output from the input switching stages compared to the synchronizing pulse output by the said timing unit.
  • the said known solutions are not suitable for carrying out the said aligning operations in the presence of a lead condition of the PCM signals compared to the reference pulse (synchronizing signal). This latter condition can occur when the distance between the intermediate switching stages is minimum and consequently the signal transit times are determined by the lags introduced by their respective logical circuits.
  • the purpose of the present invention is to make a circuit arrangement to align the PCM groups entering a communications branch point both in the presence of the said lag condition as well as in the presence of the said lead condition.
  • the object of the present invention is a circuit arrangement comprising a transmitting section and a 3 -
  • a basic time generating unit which outputs a clock signal/ having a frequency equal to that of the PCM signals to be aligned on its first output, and a synchronizing pulse with a predetermined repetition rate on its second output.
  • the transmitting section includes the presence of means to encode the PCM signals according to a biphase type law and also to introduce violations of the said law each time they receive a synchronizing pulse from the said basic time generation unit.
  • the receiving section includes the presence in combination of the following characteristic elements:
  • - 4 a write counter designed to enable writing of the cells of the said elastic memory starting from a predetermined cell, having K + 2 counting steps and also having its counting and enabling inputs respectively connected to the second and third output of the decoding means; - 4 -
  • a read counter designed to enable reading of the cells of the said elastic memory starting from a predetermined cell, again having K + 2 counting .
  • s t epS an ⁇ also having its counting and enabling input -; ' respectively connected to the first and second output of the basic time generating unit.
  • the alignment of the PCM groups entering a communications branch point is carried out by determining the simultaneous reading of a specific bit of the frame Q f all the PCM groups in the instant defined by the synchronizing pulse output by the basic time generating unit.
  • the writing operation is carried out in an instant that differs from group to group and is defined by the synchronizing pulse extracted from the received data; ie: the writing operation can have a lead on the reading operation by a number of bits that varies from 1 to K + 1.
  • - fig. 1 shows some elements of a communications branch point to which the circuit arrangement according to the invention is associated;
  • - fig. 2 shows an embodiment according to the invention of the circuit arrangement RIL of fig. 1 in detail
  • - fig. 3 shows waveforms relating to fig. 2. - 5 -
  • SC-P1 • 11 SC-Pri indicates ri peripheral switching stages (input/output stages), whilst SC-I1, SC-In indicates the same number of intermediate switching stages to which the peripheral switching stages are connected by means of bidirectional lines L.
  • Each line L can carry out bidirectional transmission of a PCM group and has a length that can in actual fact vary from a few meters to about one hundred meters.
  • RIL indicates the circuit arrangement as claimed in the present invention which, in a preferred form of embodiment is configured in order to manage four bidirectional PCM groups, even if circuits suitable to manage only one PCM group are illustrated in fig. 2.
  • Each RIL unit therefore is able to align four bidirectional PCM groups with one another by introducing a lag, for each group, that is determined by using the synchronizing pulses S output by their respective stage timing unit UTS.
  • each UTS unit receives a clock signal CK with a frequency for example equal to 2 MHz from a network timing unit UTR.
  • This signal has discontinuities (for example the cancelling of a pulse) with a repetition rate equal to 4 KHz the picking up of which makes it possible to extract the synchronizing pulses S.
  • the CK signal is in fact input into each stage timing unit UTS which then extracts the said synchronizing signal S and also outputs a signal CK- with a frequency equal to 8 MHz. - 6 -
  • Each RIL circuit receives the S signal and the CK_ signal o from its respective UTS unit and includes - for each PCM group - a transmitting section and a receiving section. Presuming that the RIL circuit in question is associated to a peripheral switching stage, the transmitting section encodes the PCM signals according to a biphase type code (for example Manchester II) and introduces a violation of the encoding law each time it receives the synchronizing pulse S.
  • a biphase type code for example Manchester II
  • the PCM group thus encoded is input to the SC-I stage to which it is addressed, to the input of which a respective RIL unit is connected which carries out the said alignment operations by comparing the temporal position of the local synchronizing pulse S output by its respective timing unit with the temporal position of the synchronizing pulse S extracted from the received data stream.
  • 1 r signals are output with a lag of 8 bits (1 byte); in all other cases the lag can take on values which, according to a preferential embodiment may vary from 1 to 11 bits.
  • Fig. 2 illustrates the circuits of the RIL unit necessary to manage a PCM group; said circuits are constituted by a basic time generating unit TBG, a transmitting section ST and a receiving section SR.
  • the TBG unit receives the said sequence of timing pulses .CK 0 o from its relevant stage timing unit UT$ as well as the synchronizing signal S having a frequency of 4 KHz.
  • the transmitting section ST has an encoding unit for converting the PCM signals from their original code (N.R.Z.) into a biphase type code (eg: Manchester II henceforth also referred to as Mil).
  • the said encoding unit is implemented by means of a logical product circuit A which receives the said signal CK on its first input and the local
  • the output of the A unit corrisponds to the PCM signal converted into Mil code which, as can be seen from diagram C, includes the transmission - during the first half of the bit time - of the same logical value as the NRZ signal and during the second half of the bit time the transmission of said logical value inverted.
  • the output of the EX unit corrisponds to the MIl/S signal where a violation - operated by the signal S (see diagram D) - to the encoding regulations of the Mil code (see diagram E), is present. It must be kept in mind that transmission of the said violation must be carried out when a couple of bits with the same logical value are present in the NRZ signal and, according to a preferred form of embodiment, said transmission is carried out, in - 8 _
  • the PCM signal after being manipulated as described above, is sent to the line L, to the other end of which a receiving section SR of a relevant RIL unit is connected.
  • the SR unit includes a decoder DC comprising an exclusive OR circuit EX to the output of which a g ⁇ lf register comprising five memory cells C , ••., C made with B type bistable elements is connected.
  • the said bistable elements receive a clock signal CK 0 with a frequency of 8 o
  • the decoder DC also comprises a sampling unit C- , made by means of a further B
  • the C, unit o In order to correctly sample the MIl/S signal, the C, unit o must receive a pulse on its timing input in the instant in which the "true" logical value of the MIl/S signal (first half of the bit time) is present on its own data input.
  • the sampling instant is determined by the EX units, in as much as the EX unit outputs a pulse each time the "true” logical value - "inverted” logical value transition is present in the MIl/S signal.
  • 0 decoding unit can correctly reconstruct the NRZ signal.
  • the C_, C. and C_ units - together with the C. and C n units 3 4 5 1 2 and together with a logical sum unit 0 - have the function of extracting the said synchronizing pulse S from the MIl/S stream.
  • the extracting operation requires the use of at least four memory cells because during the time T mentioned above the CK 0 signal presents four pulses and consequently, o for all the time that the Mil signal encoding law is respected, in at least one of the cells C , ..., C the said pulse concerning the enabling of the output of the EX unit specified above is present. Consequently, for all the time that the condition described above occurs, logical value "one" corrisponds to the output of the 0 units.
  • the output of the C . unit is connected to the K + 2 cells of an elastic memory ME, where K represents the memory's degree of elasticity, said memory having a further two cells to ensure that a time interval of at least one bit passes between a write operation and a read operation.
  • Writing of the bits available on the output of the C, unit o is controlled by a write counter CS, with a counting capacity of K + 2, which receives the said pulses CK on
  • Reading of the memory cells of the ME unit is controlled instead by a read counter CL, also with a counting capacity of K + 2, which receives the signal CK and the synchronizing signal S output by the relevant basic time generating unit TBG respectively on its counting input and preset input.
  • the outputs of the CL unit monitor a multiplexer MX, with K + 2 inputs, to the output of which a PCM data stream corrisponds that is aligned with the remaining streams that enter the communications branch point.
  • the number K is assumed equal to 10 in order to allow the carrying out of alignment operations when the deviation between the S r pulses and the S pulses is not more than 7 bits of lag and . 3 bits of lead.
  • the write counter CS is preset to i s first counting step whilst 11 -
  • the read counter CL is preset to its fifth counting- step
  • Reading of the bit written in the M cell is therefore
  • the bit written in any one cell of the elastic memory is read with a ' .delay that varies in relationship to the position of the S pulse compared to that of the S pulse.
  • the said delay can assume a value that goes from one pulse to eleven pulses of the CK sequence.
  • the alignment operation of the PCM groups that enter a communications branch point is therefore carried out by determining the simultaneous reading of a predetermined bit of the frame . of all the groups; within the ambit of each group the write operation is instead carried out in an instant that differs from group to group in relation to the position of the S pulses compared with r that of the S pulses.
  • the circuit arrangement as claimed in the invention also includes the presence of an alarm unit AL to verify the state of the respective line L and of the memory ME by using said monitoring word transmitted in alternate patterns in the time slot TS .
  • the said alarm unit AL to verify the state of the respective line L and of the memory ME by using said monitoring word transmitted in alternate patterns in the time slot TS .
  • 0 includes the presence of a third exclusive OR circuit EX which receives the said monitoring word P from the TBG unit in predetermined instants that coincide with the instants in which said word corrisponds to the output of the MX unit.
  • __> unit is registered thus signalling the presence of an abnormal condition.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

L'agencement de circuit est conçu pour gérer la transmission bidirectionnelle de canaux MIC et inclut une section de transmissison (ST), une section de réception (SR) et une unité génératrice de temps de base (TBG). La section de transmission (ST) code les signaux MIC selon les règles prévues par le code Manchester II, entraîne une infraction auxdites réglementations chaque fois qu'elle reçoit une impulsion de synchronisation (S1) de ladite unité génératrice de temps de base (TBG). La section de réception (SR) décode les signaux reçus, extrait le signal de synchronisation (Sr) et sort les signaux MIC avec un retard qui est fonction de la relation temporelle entre le signal de synchronisation (Sr) extrait du flot de données et le signal de synchronisation (S1) sorti par l'unité génératrice de temps de base (TBG).
PCT/EP1986/000330 1985-07-31 1986-05-29 Agencement de circuit permettant l'alignement, les uns par rapport aux autres, de groupes mic entrant en un point de branchement de communication WO1987001006A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT21782/85A IT1200701B (it) 1985-07-31 1985-07-31 Disposizione circuitale atta ad allineare tra di loro i fasci pcm che pervengono ad un nodo di comunicazione
IT21782A/85 1985-07-31

Publications (1)

Publication Number Publication Date
WO1987001006A1 true WO1987001006A1 (fr) 1987-02-12

Family

ID=11186772

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP1986/000330 WO1987001006A1 (fr) 1985-07-31 1986-05-29 Agencement de circuit permettant l'alignement, les uns par rapport aux autres, de groupes mic entrant en un point de branchement de communication

Country Status (5)

Country Link
EP (1) EP0231202A1 (fr)
GR (1) GR861642B (fr)
IT (1) IT1200701B (fr)
WO (1) WO1987001006A1 (fr)
YU (1) YU105586A (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1122900A1 (fr) * 2000-01-31 2001-08-08 Harris Corporation Système d'émission pour la télévision numérique comportant un circuit pour récupérer des données et des signaux d'horloge
US6388717B1 (en) 1999-01-20 2002-05-14 Harris Corporation Digital television transmitting system having data and clock recovering circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2546793A1 (de) * 1975-10-18 1977-04-21 Hentschel Systemgesellschaft M Verfahren und einrichtung zur rahmensynchronisation bei der uebertragung von pcm-signalen
FR2490055A1 (fr) * 1980-09-09 1982-03-12 Italtel Spa Reseau de commutation pour canaux pcm pour systemes de telecommunications
EP0094178A2 (fr) * 1982-05-07 1983-11-16 Digital Equipment Corporation Interface pour ligne série de transmission de données

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2546793A1 (de) * 1975-10-18 1977-04-21 Hentschel Systemgesellschaft M Verfahren und einrichtung zur rahmensynchronisation bei der uebertragung von pcm-signalen
FR2490055A1 (fr) * 1980-09-09 1982-03-12 Italtel Spa Reseau de commutation pour canaux pcm pour systemes de telecommunications
EP0094178A2 (fr) * 1982-05-07 1983-11-16 Digital Equipment Corporation Interface pour ligne série de transmission de données

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Commutation et Electronique, Vol. 54, July 1976 (Issy-Les-Moulineaux, FR) M.A. HENRION et al.: "Utilisation de la Technologie C-MOS en Commutation Temporelle", pages 69-82, see page 70, right-hand column, paragraph 2.3 *
Electronic Design, Vol. 30, No. 16, August 1982 (Denville, US) L. SANDERS "For Data-Comm Links, Manchester Chip Could be Best", pages 201-212 see page 203, left-hand column, lines 9-16; page 206, left-hand column, line 27 - right-hand column, line 19 *
Proceedings International Zurich Seminar on Digital Communications, 9-11 March 1976, paper C.1, (Zurich, CH) P.R. GERKE: "Interaction Between Circuit Technology and System Concepts in the Field of Digital TDM Switching", see page C1.5, right-hand column, lines 31-45; page C1.4, paragraph 4.4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6388717B1 (en) 1999-01-20 2002-05-14 Harris Corporation Digital television transmitting system having data and clock recovering circuit
EP1122900A1 (fr) * 2000-01-31 2001-08-08 Harris Corporation Système d'émission pour la télévision numérique comportant un circuit pour récupérer des données et des signaux d'horloge

Also Published As

Publication number Publication date
EP0231202A1 (fr) 1987-08-12
YU105586A (en) 1988-12-31
IT1200701B (it) 1989-01-27
GR861642B (en) 1986-08-01
IT8521782A0 (it) 1985-07-31

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