[go: up one dir, main page]

USRE50181E1 - Isolation region fabrication for replacement gate processing - Google Patents

Isolation region fabrication for replacement gate processing Download PDF

Info

Publication number
USRE50181E1
USRE50181E1 US17/209,199 US202117209199A USRE50181E US RE50181 E1 USRE50181 E1 US RE50181E1 US 202117209199 A US202117209199 A US 202117209199A US RE50181 E USRE50181 E US RE50181E
Authority
US
United States
Prior art keywords
region
disposed
isolation region
gate structure
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US17/209,199
Inventor
Brent A. Anderson
Edward J. Nowak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Priority to US17/209,199 priority Critical patent/USRE50181E1/en
Application granted granted Critical
Publication of USRE50181E1 publication Critical patent/USRE50181E1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H01L29/66545—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H01L21/84—
    • H01L27/1203—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • This disclosure relates generally to the field of integrated circuit (IC) manufacturing, and more specifically to isolation region fabrication for electrical isolation between semiconductor devices on an IC.
  • IC integrated circuit
  • ICs are formed by connecting isolated active devices, which may include semiconductor devices such as field effect transistors (FETs), through specific electrical connection paths to form logic or memory circuits. Therefore, electrical isolation between active devices is important in IC fabrication. Isolation of FETs from one another is usually provided by shallow trench isolation (STI) regions located between active silicon islands.
  • STI shallow trench isolation
  • An STI region may be formed by forming a trench in the substrate between the active devices by etching, and then filling the trench with an insulating material, such as an oxide. After the STI trench is filled with the insulating material, the surface profile of the STI region may be planarized by, for example, chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • a semiconductor structure in one aspect, includes a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide (BOX) layer, and a top silicon layer; a plurality of active devices formed on the top silicon layer; and an isolation region located between two of the active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region, and wherein the isolation region extends through the top silicon layer to the BOX layer.
  • SOI silicon-on-insulator
  • BOX buried oxide
  • FIG. 1 illustrates a flowchart of an embodiment of a method of isolation region fabrication for replacement gate processing.
  • FIG. 2 A is a cross sectional view illustrating an embodiment of a semiconductor structure including dummy gates on a silicon-on-insulator (SOI) substrate.
  • SOI silicon-on-insulator
  • FIG. 2 B is a top view illustrating an embodiment of the semiconductor structure of FIG. 2 A that comprises fins for formation of fin field effect transistors (finFETs).
  • finFETs fin field effect transistors
  • FIG. 3 is a cross sectional view illustrating the semiconductor structure of FIG. 2 A after formation of an interlevel dielectric layer (ILD) over the dummy gates.
  • ILD interlevel dielectric layer
  • FIG. 4 is a cross sectional view illustrating the semiconductor structure of FIG. 3 after application and patterning of photoresist.
  • FIG. 5 is a cross sectional view illustrating the semiconductor structure of FIG. 3 after removal of an exposed dummy gate to form an isolation region trench.
  • FIG. 6 is a cross sectional view illustrating the semiconductor structure of FIG. 4 after removal filling the isolation region trench with an isolation dielectric.
  • FIG. 7 is a cross sectional view illustrating the semiconductor structure of FIG. 5 after formation of a hardmask layer over the isolation region trench.
  • FIG. 8 is a cross sectional view illustrating the semiconductor structure of FIG. 6 after replacement gate processing.
  • isolation regions may replace STI regions, as is described in U.S. patent application Ser. No. 12/951,575 (Anderson et al.), filed Nov. 22, 2010, which is herein incorporated by reference in its entirety.
  • a relatively dense, low-capacitance IC may be formed by replacement gate (i.e., gate-last) processing through use of a block mask that selectively allows removal of active silicon in a gate opening to form an isolation region. The active silicon is removed in a manner that is self-aligned to the dummy gate, such that there is no overlap of gate to active area and hence minimal capacitance penalty.
  • FIG. 1 shows a flowchart of an embodiment of a method 100 of isolation region fabrication for replacement gate processing.
  • FIG. 1 is discussed with reference to FIGS. 2 - 7 .
  • a semiconductor structure including dummy gates, source/drain regions, spacers is formed on a substrate using regular semiconductor processing techniques, and an interlevel dielectric layer (ILD) is formed over the dummy gates.
  • the semiconductor structure may also include raised source/drain regions located on either side of the dummy gates underneath the spacers is in some embodiments.
  • the semiconductor structure may include any appropriate semiconductor structure that includes dummy gates, including but not limited to a fin field effect transistor (finFET) structure. An embodiment of such a semiconductor structure 200 A is shown in FIG.
  • finFET fin field effect transistor
  • the substrate is a silicon-on-insulator substrate, including bottom silicon layer 201 , buried oxide (BOX) layer 202 , and top silicon layer 203 .
  • Dummy gates 204 are located on top silicon layer 203 .
  • a gate dielectric layer 207 is formed underneath each dummy gate 204 .
  • the dummy gate structure 204 may be polysilicon in some embodiments.
  • the gate dielectric layer 207 may be any appropriate dielectric material, and in some embodiments may include a bottom dielectric layer and a top metal layer. Spacers 205 are formed on either side of the dummy gates 204 .
  • FIG. 2 B shows a top view of an embodiment of the semiconductor structure 200 A of FIG.
  • the dummy gates 204 wrap around and cover the fins that comprise top silicon layer 203 .
  • ILD 301 is formed over the dummy gates 204 and spacers 205 , and ILD 301 is planarized such that the top surfaces of dummy gates 204 are exposed.
  • a block mask is applied to the top surface of the dummy gates and the ILD, and the block mask is patterned to selectively expose the dummy gates that are to become isolation regions.
  • the block mask may comprise, for example, photoresist.
  • FIG. 4 shows an embodiment of the semiconductor structure 200 A after application and patterning of photoresist 401 to form the block mask, which exposes a dummy gate 402 . Then, turning again to method 100 , in block 103 , the exposed dummy gate is removed, and the portion of the top silicon layer located underneath the removed dummy gate is etched down to the BOX layer to form an isolation region recess.
  • the etch used to remove exposed dummy gate 402 and its respective gate dielectric layer 207 , and to form the recess 501 in top silicon layer 203 may be a sequential multistage etch.
  • the sequential multistage etch may have 3 or 4 different stages depending on the materials that make up dummy gate 204 and gate dielectric layer 207 .
  • dummy gate 402 may be removed using a dry etch such as a bromine-based etch.
  • the respective gate dielectric layer 207 may next be removed using a wet etch, such as a hydrofluoric etch for example.
  • the etch to remove the gate dielectric layer 207 may be a 2-stage etch. Then, the recess 501 may be formed in the top silicon layer 203 using a dry etch such as a bromine-based etch to etch down to BOX layer 202 .
  • the recess that was formed during the etch performed in block 103 is filled with an insulating material to form the isolation region, and the top surface of the insulating material is planarized such as is shown in FIG. 6 .
  • the recess 501 is filled with an insulator, and the top surface of the insulator is planarized, to form isolation region 601 .
  • the insulator that comprises isolation region 601 may include silicon dioxide or silicon nitride in various embodiments.
  • flow of method 100 proceeds to block 105 , in which a hardmask layer is formed over the isolation region and the photoresist is removed.
  • the hardmask layer 701 may be silicon nitride.
  • the photoresist 401 is also removed to expose the top surfaces of the remaining dummy gates 204 .
  • FIG. 7 An example of an IC device 800 including an isolation region 601 between two active devices is shown in FIG. 7 8.
  • Dummy gates 204 have been replaced with gate stacks 801 to form active FETs 802 , including gate stacks 801 , gate dielectric layer 207 , spacers 205 , and source/drain and channel regions located underneath the devices in the top silicon layer 203 .
  • the active FETs 802 may include raised source/drain regions (not shown) located under the spacers 205 in some embodiments.
  • the active FETs 802 are separated by the isolation region 601 , which extends down to BOX layer 202 , preventing electrical leakage between active FETs 802 .
  • the hardmask layer 701 acts to protect the isolation region 601 during the replacement gate processing.
  • the hardmask layer 701 may be left on the device 800 in some embodiments, or in other embodiments the hardmask layer 701 may be removed after replacement gate processing is completed.
  • FIGS. 2 A- 8 are shown for illustrative purposes only; a device formed using method 100 may include any appropriate number, type, and layout of FETs separated by any appropriate number and layout of isolation regions.
  • two active devices in a semiconductor structure may have two isolation regions located between the two active devices.
  • the gate dielectric layer that is initially formed underneath the dummy gate may be replaced during the replacement gate processing.
  • the finished active devices may comprise finFETs in some embodiments, or any other appropriate type of active device that may be formed by replacement gate processing in other embodiments.
  • the technical effects and benefits of exemplary embodiments include formation of an IC having relatively high device density and low capacitance through replacement gate processing.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A semiconductor structure includes a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide (BOX) layer, and a top silicon layer; a plurality of active devices formed on the top silicon layer; and an isolation region located between two of the active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region, and wherein the isolation region extends through the top silicon layer to the BOX layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation reissue application of U.S. patent application Ser. No. 15/626,876, filed Jun. 19, 2017, which is an application for reissue of U.S. Pat. No. 8,643,109, filed Feb. 20, 2013, and which is continuation reissue application of U.S. patent application Ser. No. 15/015,546, filed Feb. 4, 2016 and now U.S. Pat. No. RE46,448, which is an application for reissue of U.S. Pat. No. 8,643,109, filed Feb. 20, 2013, which patent was filed as a divisional application of U.S. patent application Ser. No. 13/213,713, filed on Aug. 19, 2011, now U.S. Pat. No. 8,546,208, the disclosure of each of which is herein incorporated by reference in its entirety.
BACKGROUND
This disclosure relates generally to the field of integrated circuit (IC) manufacturing, and more specifically to isolation region fabrication for electrical isolation between semiconductor devices on an IC.
ICs are formed by connecting isolated active devices, which may include semiconductor devices such as field effect transistors (FETs), through specific electrical connection paths to form logic or memory circuits. Therefore, electrical isolation between active devices is important in IC fabrication. Isolation of FETs from one another is usually provided by shallow trench isolation (STI) regions located between active silicon islands. An STI region may be formed by forming a trench in the substrate between the active devices by etching, and then filling the trench with an insulating material, such as an oxide. After the STI trench is filled with the insulating material, the surface profile of the STI region may be planarized by, for example, chemical mechanical polishing (CMP).
However, use of raised (or regrown) source/drain structures, which may be employed to achieve lower series resistances of the IC or to strain FET channels, may exhibit significant growth non-uniformities at the boundary between a gate and an STI region, or when the opening in which the source/drain structure is formed is of variable dimensions. This results in increased variability in FET threshold voltage (Vt), delay, and leakage, which in turn degrades over-all product performance and power. One solution to such boundary non-uniformity is to require all STI regions to be bounded by isolation regions. However, inclusion of such isolation region structures may limit space available for wiring, device density, and increase the load capacitance, thereby increasing switching power of the IC.
BRIEF SUMMARY
In one aspect, a semiconductor structure includes a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide (BOX) layer, and a top silicon layer; a plurality of active devices formed on the top silicon layer; and an isolation region located between two of the active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region, and wherein the isolation region extends through the top silicon layer to the BOX layer.
Additional features are realized through the techniques of the present exemplary embodiment. Other embodiments are described in detail herein and are considered a part of what is claimed. For a better understanding of the features of the exemplary embodiment, refer to the description and to the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Referring now to the drawings wherein like elements are numbered alike in the several FIGURES:
FIG. 1 illustrates a flowchart of an embodiment of a method of isolation region fabrication for replacement gate processing.
FIG. 2A is a cross sectional view illustrating an embodiment of a semiconductor structure including dummy gates on a silicon-on-insulator (SOI) substrate.
FIG. 2B is a top view illustrating an embodiment of the semiconductor structure of FIG. 2A that comprises fins for formation of fin field effect transistors (finFETs).
FIG. 3 is a cross sectional view illustrating the semiconductor structure of FIG. 2A after formation of an interlevel dielectric layer (ILD) over the dummy gates.
FIG. 4 is a cross sectional view illustrating the semiconductor structure of FIG. 3 after application and patterning of photoresist.
FIG. 5 is a cross sectional view illustrating the semiconductor structure of FIG. 3 after removal of an exposed dummy gate to form an isolation region trench.
FIG. 6 is a cross sectional view illustrating the semiconductor structure of FIG. 4 after removal filling the isolation region trench with an isolation dielectric.
FIG. 7 is a cross sectional view illustrating the semiconductor structure of FIG. 5 after formation of a hardmask layer over the isolation region trench.
FIG. 8 is a cross sectional view illustrating the semiconductor structure of FIG. 6 after replacement gate processing.
 DETAILED DESCRIPTION
Embodiments of a method for isolation region fabrication for replacement gate processing, and an IC including isolation regions, are provided, with exemplary embodiments being discussed below in detail. Instead of placing isolation regions at STI region boundaries, isolation regions may replace STI regions, as is described in U.S. patent application Ser. No. 12/951,575 (Anderson et al.), filed Nov. 22, 2010, which is herein incorporated by reference in its entirety. A relatively dense, low-capacitance IC may be formed by replacement gate (i.e., gate-last) processing through use of a block mask that selectively allows removal of active silicon in a gate opening to form an isolation region. The active silicon is removed in a manner that is self-aligned to the dummy gate, such that there is no overlap of gate to active area and hence minimal capacitance penalty.
FIG. 1 shows a flowchart of an embodiment of a method 100 of isolation region fabrication for replacement gate processing. FIG. 1 is discussed with reference to FIGS. 2-7 . First, in block 101 of FIG. 1 , a semiconductor structure including dummy gates, source/drain regions, spacers, is formed on a substrate using regular semiconductor processing techniques, and an interlevel dielectric layer (ILD) is formed over the dummy gates. The semiconductor structure may also include raised source/drain regions located on either side of the dummy gates underneath the spacers is in some embodiments. The semiconductor structure may include any appropriate semiconductor structure that includes dummy gates, including but not limited to a fin field effect transistor (finFET) structure. An embodiment of such a semiconductor structure 200A is shown in FIG. 2A. The substrate is a silicon-on-insulator substrate, including bottom silicon layer 201, buried oxide (BOX) layer 202, and top silicon layer 203. Dummy gates 204 are located on top silicon layer 203. In some embodiments, a gate dielectric layer 207 is formed underneath each dummy gate 204. The dummy gate structure 204 may be polysilicon in some embodiments. The gate dielectric layer 207 may be any appropriate dielectric material, and in some embodiments may include a bottom dielectric layer and a top metal layer. Spacers 205 are formed on either side of the dummy gates 204. FIG. 2B shows a top view of an embodiment of the semiconductor structure 200A of FIG. 2A in which the top silicon layer 203 has been patterned to form fins for finFETs. In the semiconductor structure 200B of FIG. 2B, the dummy gates 204 wrap around and cover the fins that comprise top silicon layer 203. After formation of the dummy gates 204, as shown in FIG. 3 , ILD 301 is formed over the dummy gates 204 and spacers 205, and ILD 301 is planarized such that the top surfaces of dummy gates 204 are exposed.
Returning to method 100, in block 102, a block mask is applied to the top surface of the dummy gates and the ILD, and the block mask is patterned to selectively expose the dummy gates that are to become isolation regions. The block mask may comprise, for example, photoresist. FIG. 4 shows an embodiment of the semiconductor structure 200A after application and patterning of photoresist 401 to form the block mask, which exposes a dummy gate 402. Then, turning again to method 100, in block 103, the exposed dummy gate is removed, and the portion of the top silicon layer located underneath the removed dummy gate is etched down to the BOX layer to form an isolation region recess. FIG. 5 shows an embodiment of a device including an isolation region recess 501. The etch used to remove exposed dummy gate 402 and its respective gate dielectric layer 207, and to form the recess 501 in top silicon layer 203, may be a sequential multistage etch. The sequential multistage etch may have 3 or 4 different stages depending on the materials that make up dummy gate 204 and gate dielectric layer 207. In embodiments in which the dummy gate 402 is polysilicon, dummy gate 402 may be removed using a dry etch such as a bromine-based etch. The respective gate dielectric layer 207 may next be removed using a wet etch, such as a hydrofluoric etch for example. In embodiments in which respective gate dielectric layer 207 includes a bottom dielectric layer and a top metal layer, the etch to remove the gate dielectric layer 207 may be a 2-stage etch. Then, the recess 501 may be formed in the top silicon layer 203 using a dry etch such as a bromine-based etch to etch down to BOX layer 202.
Next, in method 100 of FIG. 1 , in block 104, the recess that was formed during the etch performed in block 103 is filled with an insulating material to form the isolation region, and the top surface of the insulating material is planarized such as is shown in FIG. 6 . In FIG. 6 , the recess 501 is filled with an insulator, and the top surface of the insulator is planarized, to form isolation region 601. The insulator that comprises isolation region 601 may include silicon dioxide or silicon nitride in various embodiments. Then, flow of method 100 proceeds to block 105, in which a hardmask layer is formed over the isolation region and the photoresist is removed. FIG. 7 shows an embodiment of a hardmask layer 701 formed over the isolation region 601. The hardmask layer 701 may be silicon nitride. The photoresist 401 is also removed to expose the top surfaces of the remaining dummy gates 204.
Lastly, in block 106 of method 100 of FIG. 1 , replacement gate processing is performed on the remaining dummy gates, resulting in an IC device including electrical devices separated by isolation regions. An example of an IC device 800 including an isolation region 601 between two active devices is shown in FIG. 7 8. Dummy gates 204 have been replaced with gate stacks 801 to form active FETs 802, including gate stacks 801, gate dielectric layer 207, spacers 205, and source/drain and channel regions located underneath the devices in the top silicon layer 203. The active FETs 802 may include raised source/drain regions (not shown) located under the spacers 205 in some embodiments. The active FETs 802 are separated by the isolation region 601, which extends down to BOX layer 202, preventing electrical leakage between active FETs 802. The hardmask layer 701 acts to protect the isolation region 601 during the replacement gate processing. The hardmask layer 701 may be left on the device 800 in some embodiments, or in other embodiments the hardmask layer 701 may be removed after replacement gate processing is completed. FIGS. 2A-8 are shown for illustrative purposes only; a device formed using method 100 may include any appropriate number, type, and layout of FETs separated by any appropriate number and layout of isolation regions. For example, in some embodiments, two active devices in a semiconductor structure may have two isolation regions located between the two active devices. Also, in some embodiments, the gate dielectric layer that is initially formed underneath the dummy gate may be replaced during the replacement gate processing. The finished active devices may comprise finFETs in some embodiments, or any other appropriate type of active device that may be formed by replacement gate processing in other embodiments.
The technical effects and benefits of exemplary embodiments include formation of an IC having relatively high device density and low capacitance through replacement gate processing.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Claims (14)

The invention claimed is:
1. A semiconductor structure, comprising:
a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide (BOX) layer, and a top silicon layer;
a plurality of active devices formed on the top silicon layer; and
an isolation region located between two of the plurality of active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region, wherein the isolation region extends through the top silicon layer to the BOX layer, wherein the isolation region further extends between a pair of spacers that are located on the top silicon layer on either side of the isolation region, and wherein the isolation region further extends through an interlevel dielectric (ILD) layer that is located over the pair of spacers.
2. The semiconductor structure of claim 1, further comprising a hardmask layer located over the isolation region.
3. The semiconductor structure of claim 2, wherein the hardmask layer comprises silicon nitride.
4. A semiconductor device comprising:
a substrate including a top silicon layer that includes a fin;
a first gate structure disposed on the fin;
a second gate structure disposed on the fin;
an isolation region disposed between the first gate structure and the second gate structure, and electrically isolating the first gate structure from the second gate structure;
a first region disposed on a first side of the isolation region and disposed on the substrate;
a second region disposed on a second side of the isolation region and disposed on the substrate;
a third region including an interlevel dielectric (ILD) layer and including a first portion disposed on the first region and a second portion disposed on the second region; and
a silicon nitride layer disposed on the first region and the second region,
wherein the isolation region extends between the first region and the second region, and extends through the third region,
the isolation region extends from above a top of the fin to a bottom of the fin,
the fin extends in a first horizontal direction and at least the first gate structure extends in a second horizontal direction perpendicular to the first horizontal direction, and
wherein a top surface of the first gate structure is at substantially the same level as a top surface of the isolation region.
5. The semiconductor device of claim 4, wherein the third region includes a third portion disposed on the first gate structure and a fourth portion disposed on the second gate structure.
6. The semiconductor device of claim 4, wherein the silicon nitride layer is disposed on the isolation region.
7. The semiconductor device of claim 4, wherein the silicon nitride layer is disposed on the third region.
8. The semiconductor device of claim 4, wherein the isolation region extends through the third region in a direction that is substantially parallel with respect to a top surface of the substrate.
9. The semiconductor device of claim 4, wherein the isolation region extends through the third region in a direction that is substantially perpendicular with respect to a top surface of the substrate.
10. The semiconductor device of claim 4, wherein the third region is disposed on a sidewall of the first region and on a sidewall of the second region.
11. The semiconductor device of claim 4, wherein the third region is disposed on a top surface of the first region and on a top surface of the second region.
12. The semiconductor device of claim 4, wherein the isolation region contacts the third region.
13. The semiconductor device of claim 4, wherein the isolation region contacts the silicon nitride layer.
14. A semiconductor device comprising:
a substrate including a top silicon layer that includes a fin;
a first gate structure disposed on the fin;
a second gate structure disposed on the fin;
an isolation region disposed between the first gate structure and the second gate structure, and electrically isolating the first gate structure from the second gate structure;
a first region disposed on a first side of the isolation region and disposed on the substrate;
a second region disposed on a second side of the isolation region and disposed on the substrate;
a third region including a first portion disposed on the first region and a second portion disposed on the second region;
a silicon nitride layer disposed on the first region and the second region, disposed on the isolation region above the isolation region to vertically overlap the isolation region, and disposed adjacent to the third region;
a first channel disposed below the first gate structure; and
a second channel disposed below the second gate structure,
wherein the isolation region extends between the first region and the second region, and extends through the third region that is disposed on the first region and the second region.
US17/209,199 2011-08-19 2021-03-22 Isolation region fabrication for replacement gate processing Active USRE50181E1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/209,199 USRE50181E1 (en) 2011-08-19 2021-03-22 Isolation region fabrication for replacement gate processing

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US13/213,713 US8546208B2 (en) 2011-08-19 2011-08-19 Isolation region fabrication for replacement gate processing
US13/771,275 US8643109B2 (en) 2011-08-19 2013-02-20 Isolation region fabrication for replacement gate processing
US15/015,546 USRE46448E1 (en) 2011-08-19 2016-02-04 Isolation region fabrication for replacement gate processing
US15/626,876 USRE48616E1 (en) 2011-08-19 2017-06-19 Isolation region fabrication for replacement gate processing
US17/209,199 USRE50181E1 (en) 2011-08-19 2021-03-22 Isolation region fabrication for replacement gate processing

Related Parent Applications (2)

Application Number Title Priority Date Filing Date
US13/771,275 Reissue US8643109B2 (en) 2011-08-19 2013-02-20 Isolation region fabrication for replacement gate processing
US15/626,876 Continuation USRE48616E1 (en) 2011-08-19 2017-06-19 Isolation region fabrication for replacement gate processing

Publications (1)

Publication Number Publication Date
USRE50181E1 true USRE50181E1 (en) 2024-10-22

Family

ID=47712038

Family Applications (6)

Application Number Title Priority Date Filing Date
US13/213,713 Ceased US8546208B2 (en) 2011-08-19 2011-08-19 Isolation region fabrication for replacement gate processing
US13/771,275 Ceased US8643109B2 (en) 2011-08-19 2013-02-20 Isolation region fabrication for replacement gate processing
US14/872,790 Active USRE46303E1 (en) 2011-08-19 2015-10-01 Isolation region fabrication for replacement gate processing
US15/015,546 Active USRE46448E1 (en) 2011-08-19 2016-02-04 Isolation region fabrication for replacement gate processing
US15/626,876 Active USRE48616E1 (en) 2011-08-19 2017-06-19 Isolation region fabrication for replacement gate processing
US17/209,199 Active USRE50181E1 (en) 2011-08-19 2021-03-22 Isolation region fabrication for replacement gate processing

Family Applications Before (5)

Application Number Title Priority Date Filing Date
US13/213,713 Ceased US8546208B2 (en) 2011-08-19 2011-08-19 Isolation region fabrication for replacement gate processing
US13/771,275 Ceased US8643109B2 (en) 2011-08-19 2013-02-20 Isolation region fabrication for replacement gate processing
US14/872,790 Active USRE46303E1 (en) 2011-08-19 2015-10-01 Isolation region fabrication for replacement gate processing
US15/015,546 Active USRE46448E1 (en) 2011-08-19 2016-02-04 Isolation region fabrication for replacement gate processing
US15/626,876 Active USRE48616E1 (en) 2011-08-19 2017-06-19 Isolation region fabrication for replacement gate processing

Country Status (1)

Country Link
US (6) US8546208B2 (en)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8546208B2 (en) * 2011-08-19 2013-10-01 International Business Machines Corporation Isolation region fabrication for replacement gate processing
US9136131B2 (en) * 2013-11-04 2015-09-15 Globalfoundries Inc. Common fill of gate and source and drain contacts
US20150214331A1 (en) 2014-01-30 2015-07-30 Globalfoundries Inc. Replacement metal gate including dielectric gate material
US9318574B2 (en) * 2014-06-18 2016-04-19 International Business Machines Corporation Method and structure for enabling high aspect ratio sacrificial gates
US9373641B2 (en) 2014-08-19 2016-06-21 International Business Machines Corporation Methods of forming field effect transistors using a gate cut process following final gate formation
CN105448917B (en) 2014-09-01 2019-03-29 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
US9490176B2 (en) 2014-10-17 2016-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for FinFET isolation
KR102214023B1 (en) 2014-12-03 2021-02-09 삼성전자주식회사 Semiconductor device
US9431396B2 (en) * 2015-01-30 2016-08-30 Globalfoundries Inc. Single diffusion break with improved isolation and process window and reduced cost
FR3036846B1 (en) * 2015-05-29 2018-06-15 Stmicroelectronics (Crolles 2) Sas METHOD FOR LOCAL ISOLATION BETWEEN TRANSISTORS MADE ON A SOI SUBSTRATE, ESPECIALLY FDSOI, AND CORRESPONDING INTEGRATED CIRCUIT
US10008493B2 (en) * 2015-06-08 2018-06-26 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
KR102399027B1 (en) 2015-06-24 2022-05-16 삼성전자주식회사 Semiconductor device
US9659786B2 (en) 2015-07-14 2017-05-23 International Business Machines Corporation Gate cut with high selectivity to preserve interlevel dielectric layer
KR20170065271A (en) * 2015-12-03 2017-06-13 삼성전자주식회사 A semiconductor device and methods of manufacturing the same
KR102564786B1 (en) 2016-01-13 2023-08-09 삼성전자주식회사 Semiconductor devices and method of fabricating the same
US10734522B2 (en) * 2016-06-15 2020-08-04 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device structure with gate stacks
US9917103B1 (en) 2017-01-04 2018-03-13 Globalfoundries Inc. Diffusion break forming after source/drain forming and related IC structure
TWI657533B (en) * 2017-06-16 2019-04-21 台灣積體電路製造股份有限公司 Semiconductor device and method for fabricating the same
US10727108B2 (en) 2018-10-23 2020-07-28 Globalfoundries Inc. Dummy gate isolation and method of production thereof
US11581430B2 (en) * 2019-08-22 2023-02-14 Globalfoundries U.S. Inc. Planar transistor device comprising at least one layer of a two-dimensional (2D) material and methods for making such transistor devices

Citations (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6803278B2 (en) 2001-03-16 2004-10-12 Micron Technology, Inc. Method of forming memory cells in an array
JP2004288685A (en) 2003-03-19 2004-10-14 Nec Micro Systems Ltd Method and program for designing layout of semiconductor integrated circuit
US6812149B1 (en) 2003-09-16 2004-11-02 Macronix International Co., Ltd. Method of forming junction isolation to isolate active elements
US20050019993A1 (en) 2003-07-24 2005-01-27 Deok-Hyung Lee Methods for fabricating fin field effect transistors using a protective layer to reduce etching damage
US20050035415A1 (en) * 2003-08-13 2005-02-17 Yee-Chia Yeo Multiple-gate transistors formed on bulk substrates
US20050153490A1 (en) * 2003-12-16 2005-07-14 Jae-Man Yoon Method of forming fin field effect transistor
US20050169052A1 (en) 2002-06-13 2005-08-04 Aplus Flash Technology, Inc. Novel EEPROM cell structure and array architecture
US20050239242A1 (en) 2004-04-23 2005-10-27 International Business Machines Corporation structure and method of manufacturing a finFet device having stacked fins
JP2005340461A (en) 2004-05-26 2005-12-08 Sharp Corp Semiconductor integrated circuit device
US7049185B2 (en) 1999-12-13 2006-05-23 Nec Electronics Corporation Semiconductor device having dummy gates and its manufacturing method
US7052937B2 (en) 1999-07-28 2006-05-30 International Business Machines Corporation Method and structure for providing improved thermal conduction for silicon semiconductor devices
US20060125024A1 (en) 2004-12-09 2006-06-15 Yoshiyuki Ishigaki Semiconductor device and a method of manufacturing the same
US20060228872A1 (en) * 2005-03-30 2006-10-12 Bich-Yen Nguyen Method of making a semiconductor device having an arched structure strained semiconductor layer
US20070178660A1 (en) * 2006-01-27 2007-08-02 Gayle Miller Polish stop and sealing layer for manufacture of semiconductor devices with deep trench isolation
US20070176235A1 (en) * 2006-01-27 2007-08-02 Renesas Technology Corp. Semiconductor device and manufacturing method for the same
US20080020515A1 (en) * 2006-07-20 2008-01-24 White Ted R Twisted Dual-Substrate Orientation (DSO) Substrates
US20080079074A1 (en) * 2006-10-02 2008-04-03 Ali Icel Soi semiconductor components and methods for their fabrication
US20080079088A1 (en) 2006-09-28 2008-04-03 Chiaki Kudo Semiconductor device and method for manufacturing the same
US20080197424A1 (en) 2007-02-21 2008-08-21 International Business Machines Corporation Semiconductor structure including gate electrode having laterally variable work function
US7525173B2 (en) 2005-07-22 2009-04-28 Samsung Electronics, Ltd Layout structure of MOS transistors on an active region
US20090114995A1 (en) 2007-11-05 2009-05-07 Masamichi Suzuki Complementary semiconductor device and method of manufacturing the same
US7569887B2 (en) 2004-08-17 2009-08-04 Nec Electronics Corporation C-shaped dummy gate electrode semiconductor device and method of manufacturing the same
US20090200604A1 (en) 2004-01-22 2009-08-13 International Business Machines Corporation Vertical fin-fet mos devices
US7671469B2 (en) 2007-12-31 2010-03-02 Mediatek Inc. SiGe device with SiGe-embedded dummy pattern for alleviating micro-loading effect
US20100148248A1 (en) 2008-12-11 2010-06-17 Elpida Memory, Inc. Semiconductor device having gate trenches and manufacturing method thereof
US20100193877A1 (en) 2006-02-24 2010-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Memory Array Structure With Strapping Cells
US7785946B2 (en) 2007-09-25 2010-08-31 Infineon Technologies Ag Integrated circuits and methods of design and manufacture thereof
US7915112B2 (en) 2008-09-23 2011-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate stress film for mobility enhancement in FinFET device
US20110147765A1 (en) 2009-12-17 2011-06-23 Taiwan Semiconductor Manufatcuring Company, Ltd. Dummy structure for isolating devices in integrated circuits
US20110287600A1 (en) * 2010-05-20 2011-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Selective Etching in the Formation of Epitaxy Regions in MOS Devices
US8502316B2 (en) 2010-02-11 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned two-step STI formation through dummy poly removal
US9184100B2 (en) 2011-08-10 2015-11-10 United Microelectronics Corp. Semiconductor device having strained fin structure and method of making the same
USRE46448E1 (en) * 2011-08-19 2017-06-20 Samsung Electronics Co., Ltd. Isolation region fabrication for replacement gate processing

Patent Citations (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7052937B2 (en) 1999-07-28 2006-05-30 International Business Machines Corporation Method and structure for providing improved thermal conduction for silicon semiconductor devices
US7049185B2 (en) 1999-12-13 2006-05-23 Nec Electronics Corporation Semiconductor device having dummy gates and its manufacturing method
US6803278B2 (en) 2001-03-16 2004-10-12 Micron Technology, Inc. Method of forming memory cells in an array
US20050169052A1 (en) 2002-06-13 2005-08-04 Aplus Flash Technology, Inc. Novel EEPROM cell structure and array architecture
JP2004288685A (en) 2003-03-19 2004-10-14 Nec Micro Systems Ltd Method and program for designing layout of semiconductor integrated circuit
US20050019993A1 (en) 2003-07-24 2005-01-27 Deok-Hyung Lee Methods for fabricating fin field effect transistors using a protective layer to reduce etching damage
US20050035415A1 (en) * 2003-08-13 2005-02-17 Yee-Chia Yeo Multiple-gate transistors formed on bulk substrates
US6812149B1 (en) 2003-09-16 2004-11-02 Macronix International Co., Ltd. Method of forming junction isolation to isolate active elements
US20050153490A1 (en) * 2003-12-16 2005-07-14 Jae-Man Yoon Method of forming fin field effect transistor
US20090200604A1 (en) 2004-01-22 2009-08-13 International Business Machines Corporation Vertical fin-fet mos devices
US20050239242A1 (en) 2004-04-23 2005-10-27 International Business Machines Corporation structure and method of manufacturing a finFet device having stacked fins
JP2005340461A (en) 2004-05-26 2005-12-08 Sharp Corp Semiconductor integrated circuit device
US7569887B2 (en) 2004-08-17 2009-08-04 Nec Electronics Corporation C-shaped dummy gate electrode semiconductor device and method of manufacturing the same
US20060125024A1 (en) 2004-12-09 2006-06-15 Yoshiyuki Ishigaki Semiconductor device and a method of manufacturing the same
US20060228872A1 (en) * 2005-03-30 2006-10-12 Bich-Yen Nguyen Method of making a semiconductor device having an arched structure strained semiconductor layer
US7525173B2 (en) 2005-07-22 2009-04-28 Samsung Electronics, Ltd Layout structure of MOS transistors on an active region
US20070178660A1 (en) * 2006-01-27 2007-08-02 Gayle Miller Polish stop and sealing layer for manufacture of semiconductor devices with deep trench isolation
US20070176235A1 (en) * 2006-01-27 2007-08-02 Renesas Technology Corp. Semiconductor device and manufacturing method for the same
US20100193877A1 (en) 2006-02-24 2010-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Memory Array Structure With Strapping Cells
US20080020515A1 (en) * 2006-07-20 2008-01-24 White Ted R Twisted Dual-Substrate Orientation (DSO) Substrates
US20080079088A1 (en) 2006-09-28 2008-04-03 Chiaki Kudo Semiconductor device and method for manufacturing the same
US20080079074A1 (en) * 2006-10-02 2008-04-03 Ali Icel Soi semiconductor components and methods for their fabrication
US20080197424A1 (en) 2007-02-21 2008-08-21 International Business Machines Corporation Semiconductor structure including gate electrode having laterally variable work function
US7785946B2 (en) 2007-09-25 2010-08-31 Infineon Technologies Ag Integrated circuits and methods of design and manufacture thereof
US20090114995A1 (en) 2007-11-05 2009-05-07 Masamichi Suzuki Complementary semiconductor device and method of manufacturing the same
US7671469B2 (en) 2007-12-31 2010-03-02 Mediatek Inc. SiGe device with SiGe-embedded dummy pattern for alleviating micro-loading effect
US7915112B2 (en) 2008-09-23 2011-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate stress film for mobility enhancement in FinFET device
US20100148248A1 (en) 2008-12-11 2010-06-17 Elpida Memory, Inc. Semiconductor device having gate trenches and manufacturing method thereof
US20110147765A1 (en) 2009-12-17 2011-06-23 Taiwan Semiconductor Manufatcuring Company, Ltd. Dummy structure for isolating devices in integrated circuits
US8502316B2 (en) 2010-02-11 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned two-step STI formation through dummy poly removal
US20110287600A1 (en) * 2010-05-20 2011-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Selective Etching in the Formation of Epitaxy Regions in MOS Devices
US9184100B2 (en) 2011-08-10 2015-11-10 United Microelectronics Corp. Semiconductor device having strained fin structure and method of making the same
USRE46448E1 (en) * 2011-08-19 2017-06-20 Samsung Electronics Co., Ltd. Isolation region fabrication for replacement gate processing
USRE48616E1 (en) * 2011-08-19 2021-06-29 Samsung Electronics Co., Ltd. Isolation region fabrication for replacement gate processing

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Hirose Shingo, JP2004288685, Oct. 14, 2004, Abstract.
Shinohara Tsuneo, JP2005340461, Dec. 8, 2005, Abstract.

Also Published As

Publication number Publication date
US20130161747A1 (en) 2013-06-27
US8643109B2 (en) 2014-02-04
US20130043535A1 (en) 2013-02-21
USRE46448E1 (en) 2017-06-20
USRE48616E1 (en) 2021-06-29
USRE46303E1 (en) 2017-02-07
US8546208B2 (en) 2013-10-01

Similar Documents

Publication Publication Date Title
USRE50181E1 (en) Isolation region fabrication for replacement gate processing
US11088145B2 (en) Semiconductor device including insulating element
US9196540B2 (en) FinFET structure with novel edge fins
US9865592B2 (en) Method for FinFET integrated with capacitor
US7148541B2 (en) Vertical channel field effect transistors having insulating layers thereon
CN104157604B (en) Standard block and its preparation method for the dense pack of IC products
US7790543B2 (en) Device structures for a metal-oxide-semiconductor field effect transistor and methods of fabricating such device structures
US10804403B2 (en) Method of fabricating semiconductor devices
KR20100105779A (en) Planar substrate devices integrated with finfets and method of manufacture
US10084053B1 (en) Gate cuts after metal gate formation
US20160190143A1 (en) Interdigitated capacitor to integrate with flash memory
US20240379458A1 (en) Semiconductor device and manufacturing method thereof
US9728456B2 (en) Interconnect structure including middle of line (MOL) metal layer local interconnect on etch stop layer
CN111554578B (en) Semiconductor structure and forming method thereof
KR20090125247A (en) Trench Formation in Semiconductor Materials
KR20050055978A (en) Fin field effect transistors and methods of forming the same
US11527409B2 (en) Contact slots forming method applying photoresists
US20240014208A1 (en) Self-aligned bottom spacer
US11545574B2 (en) Single diffusion breaks including stacked dielectric layers
KR20060046879A (en) Manufacturing method of multi-bridge channel type MOS transistor

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY