USRE36475E - Method of forming a via plug in a semiconductor device - Google Patents
Method of forming a via plug in a semiconductor device Download PDFInfo
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- USRE36475E USRE36475E US08/734,784 US73478496A USRE36475E US RE36475 E USRE36475 E US RE36475E US 73478496 A US73478496 A US 73478496A US RE36475 E USRE36475 E US RE36475E
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/06102—Disposition the bonding areas being at different heights
Definitions
- the invention relates to a method of forming a via plug in a semiconductor device, more particularly, it relates to a method of forming a via plug by forming metal nuclei on the surface of a metal layer underlying a via hall and then etching the metal layer exposed between the metal nuclei by the wet etching method so that a plurality of etching grooves are formed thereupon.
- the formation of such grooves has the effect of increasing the bottom surface area of the via hall, thereby increasing the adhesive strength to a contact surface of the via hall and decreasing the via resistance.
- the via hall diminishes while the aspect ratio increases. If the depth of the via halls are different from each other, the via plug is formed on the via halls using tungsten. In order to form a uniform and complete via plug, pretreatment of the via halls is important. If the surface of the via halls is not uniform prior to and during application of the wet etching process, particles, such as a native oxide layer and polymer, are generated on the surface of the metal layer underlying the via halls.
- the tungsten is deposited with a luck of uniformity resulting in increased via resistance to; such increased resistance has a deleterious effect on subsequent processes culminating in the lowering of the electrical connecting characteristic of the semiconductor device.
- the metal layer between the metal nuclei is then exposed and etched by the wet etching method so as to increase the surface area of the adhesive contact area, thereby decreasing the via resistance while increasing the adhesive strength.
- a method of forming a via plug according to the present invention in order to achieve the above object is comprised of the following steps:
- a first metal layer is formed on a substrate and first, second and third insulating layers are sequentially deposited on the resulting substrate; the third insulating layer is then planarized;
- a desired portion of the third, second and first insulating layer are etched using a contact mask until the first metal layer is exposed, thereby forming a via hole;
- the via hole is pretreated by the dry etching method and then metal is selectively deposited on the surface of the first metal layer underlying the via hole using a metal depositing reactor, thereby forming metal nuclei;
- the first metal layer exposed between the metal nuclei is etched so that a plurality of etching grooves is formed on the first metal layer.
- FIGS. 1A through 1E are cross sectional views illustrating steps forming a via hole in a semiconductor device according to the present invention.
- FIGS. 1A through 1E are cross sectional views illustrating steps forming a via hole in a semiconductor device according to the present invention.
- a first metal layers 2 are initially formed on the substrate 1 in such a way so as to be isolated from each other.
- the first, second and third insulating layers 3, 4 and 5 are sequentially formed on the resulting substrate and then the third insulating layer 5 is planarized.
- a desired portion of the first, second and third insulating layers 3, 4 and 5 situated on top of the first metal layers 2 are sequentially etched using the wet etching or dry etching method in order to connect to a second metal layer which will be formed in a later process, and thereby forming via holes 6 the aspect ratios of which are different from each other.
- the via holes 6 are pretreated by the dry etching method in the RIE (Reactive Ion Etch) reactor during approximately one (1) minute using a NF 3 , SF 6 or Ar sputter.
- Metal such as a tungsten(W), aluminum(Al), copper(Cu), molybdenum(Mo), titanium(Ti), cobalt(Co), or chromium(Cr) is then selectively deposited on the surface of the first metal layer 2 underlying the via holes 6 for a duration of approximately one (1) minute in the metal depositing reactor, thereby forming metal nuclei 7.
- the magnitude of the metal nuclei diameter is approximately 500 to 1000 ⁇ .
- the first metal layer partially exposed between the metal nuclei 7 is etched by the wet etchant such as BOE (Buffered Oxide Etchant) in such a way that the metal nuclei 7 remains, and thereby forming a plurality of etching grooves 8 on the surface of the first metal layer 2.
- the wet etchant's etching selectivity is greater for the first metal layer 2 than it is for the metal nuclei 7.
- the wet etching method forms etching grooves 8 on the surface of the partially exposed metal layer, the contact area is increased and a fluorine particle compound, and native oxide layer are removed. As a result, when the via plug is formed on the via hole, the adhesive strength is increased while the via resistance is decreased.
- a via plug 9 is formed on the via holes 6 using a LPCVD reactor, and then a second metal layer 10 is formed to connect with the via plug 9.
- metal nuclei are formed on the via hole and then etching grooves are formed on the partially exposed metal layer under the via hole to increase the area of contact for connection with the via plug. Accordingly, the removal of particles which contribute to the increased via resistance results in a decrease of via resistance and improves the adhesive strength thereof. As a result, the electrical connection characteristic of the semiconductor device is improved.
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A method of forming a via plug in a semiconductor device is disclosed. Metal nuclei are formed on the surface of the metal layer underlying the via hole. The metal layer, which is partially exposed between metal nuclei, is etched by means of a wet etching method, and accordingly, a plurality of etching grooves is formed on the partially exposed surface of the metal layer. As a result, the formation of such grooves has the effect of increasing the bottom surface area of the via hall, thereby increasing the adhesive strength to a contact surface of the via hall and decreasing the via resistance.
Description
The invention relates to a method of forming a via plug in a semiconductor device, more particularly, it relates to a method of forming a via plug by forming metal nuclei on the surface of a metal layer underlying a via hall and then etching the metal layer exposed between the metal nuclei by the wet etching method so that a plurality of etching grooves are formed thereupon. The formation of such grooves has the effect of increasing the bottom surface area of the via hall, thereby increasing the adhesive strength to a contact surface of the via hall and decreasing the via resistance.
Generally, as integration of a semiconductor device is increased, the size of the via hall diminishes while the aspect ratio increases. If the depth of the via halls are different from each other, the via plug is formed on the via halls using tungsten. In order to form a uniform and complete via plug, pretreatment of the via halls is important. If the surface of the via halls is not uniform prior to and during application of the wet etching process, particles, such as a native oxide layer and polymer, are generated on the surface of the metal layer underlying the via halls. Accordingly, when the via plug is formed on the via halls, the tungsten is deposited with a luck of uniformity resulting in increased via resistance to; such increased resistance has a deleterious effect on subsequent processes culminating in the lowering of the electrical connecting characteristic of the semiconductor device.
Therefore, it is an object of the invention to provide a method of forming a via plug in a semiconductor device by which a fluorine particle and a native oxide layer formed on the surface of the metal layer underlying a via hole are removed and metal nuclei are formed on the surface of the metal layer. The metal layer between the metal nuclei is then exposed and etched by the wet etching method so as to increase the surface area of the adhesive contact area, thereby decreasing the via resistance while increasing the adhesive strength.
A method of forming a via plug according to the present invention in order to achieve the above object is comprised of the following steps:
A first metal layer is formed on a substrate and first, second and third insulating layers are sequentially deposited on the resulting substrate; the third insulating layer is then planarized;
A desired portion of the third, second and first insulating layer are etched using a contact mask until the first metal layer is exposed, thereby forming a via hole;
The via hole is pretreated by the dry etching method and then metal is selectively deposited on the surface of the first metal layer underlying the via hole using a metal depositing reactor, thereby forming metal nuclei;
The first metal layer exposed between the metal nuclei is etched so that a plurality of etching grooves is formed on the first metal layer.
For fuller understanding of the nature and objects of the invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings in which:
FIGS. 1A through 1E are cross sectional views illustrating steps forming a via hole in a semiconductor device according to the present invention.
Similar reference characters refer to similar parts throughout the several views of the drawings.
FIGS. 1A through 1E are cross sectional views illustrating steps forming a via hole in a semiconductor device according to the present invention.
Referring to FIG. 1A, a first metal layers 2 are initially formed on the substrate 1 in such a way so as to be isolated from each other. The first, second and third insulating layers 3, 4 and 5 are sequentially formed on the resulting substrate and then the third insulating layer 5 is planarized.
Referring to FIG. 1B, a desired portion of the first, second and third insulating layers 3, 4 and 5 situated on top of the first metal layers 2 are sequentially etched using the wet etching or dry etching method in order to connect to a second metal layer which will be formed in a later process, and thereby forming via holes 6 the aspect ratios of which are different from each other.
Referring to FIG. 1C, the via holes 6 are pretreated by the dry etching method in the RIE (Reactive Ion Etch) reactor during approximately one (1) minute using a NF3, SF6 or Ar sputter. Metal such as a tungsten(W), aluminum(Al), copper(Cu), molybdenum(Mo), titanium(Ti), cobalt(Co), or chromium(Cr) is then selectively deposited on the surface of the first metal layer 2 underlying the via holes 6 for a duration of approximately one (1) minute in the metal depositing reactor, thereby forming metal nuclei 7. The magnitude of the metal nuclei diameter is approximately 500 to 1000 Å. When the via holes 6 are pretreated, a fluorine particle compound and a native oxide layer is generated.
Referring to FIG. 1D, the first metal layer partially exposed between the metal nuclei 7 is etched by the wet etchant such as BOE (Buffered Oxide Etchant) in such a way that the metal nuclei 7 remains, and thereby forming a plurality of etching grooves 8 on the surface of the first metal layer 2. The wet etchant's etching selectivity is greater for the first metal layer 2 than it is for the metal nuclei 7.
As the wet etching method forms etching grooves 8 on the surface of the partially exposed metal layer, the contact area is increased and a fluorine particle compound, and native oxide layer are removed. As a result, when the via plug is formed on the via hole, the adhesive strength is increased while the via resistance is decreased.
Referring to FIG. 1E, a via plug 9 is formed on the via holes 6 using a LPCVD reactor, and then a second metal layer 10 is formed to connect with the via plug 9.
As described above, according to the present invention, metal nuclei are formed on the via hole and then etching grooves are formed on the partially exposed metal layer under the via hole to increase the area of contact for connection with the via plug. Accordingly, the removal of particles which contribute to the increased via resistance results in a decrease of via resistance and improves the adhesive strength thereof. As a result, the electrical connection characteristic of the semiconductor device is improved.
Although this invention has been described in its preferred embodiment with a certain degree of particularity, one skilled in the art would know that the preferred embodiment disclosed here is only an example and that the construction, combination and arrangement of its parts may be varied without departing from the spirit and the scope of the invention.
Claims (30)
1. A method of forming a via plug in a semiconductor device comprises;
forming a first metal layer on a substrate and sequentially depositing a first, second and third insulating layer on the resulting substrate and then planarizing said third insulating layer;
etching a desired portion of said third, second and first insulating layer using a contact mask until said first metal layer is exposed, thereby forming a via hole;
pretreating said via hole by the dry etching method and then, forming metal nuclei on the surface of said first metal layer at the bottom of said via hole;
etching said first metal layer exposed between said metal nuclei so that a plurality of etching grooves is formed on said first metal layer; and
forming a via plug on said via hole.
2. The method of claim 1, wherein said first metal layer exposed between said metal nuclei is etched by .[.the.]. .Iadd.a .Iaddend.wet etchant which .[.the.]. .Iadd.an .Iaddend.etching selectivity of said first metal layer is greater than said that of said metal nuclei.
3. The method of claim 1, wherein said via plug is formed in .[.the.]. .Iadd.an .Iaddend.LPCVD reactor.
4. The method of claim 1, wherein .[.the.]. .Iadd.a .Iaddend.magnitude of each nuclei is 500 to 1000 Å.
5. The method of claim 1, wherein said via hole is pretreated in .[.the.]. .Iadd.a .Iaddend.RIE reactor.
6. The method of claim 1, wherein said via hole is pretreated by a NF3, SF6 or Ar sputter.
7. The method of claim 1, wherein said etching grooves are formed using .[.the.]. .Iadd.a .Iaddend.buffered oxide etchant.
8. The method of claim 1, wherein said metal nuclei are formed by tungsten.
9. The method of claim 1, wherein said metal nuclei are formed by aluminum.
10. The method of claim 1, wherein said metal nuclei are formed by copper.
11. The method of claim 1, wherein said metal nuclei are formed by molybdenum.
12. The method of claim 1, wherein said metal nuclei are formed by titanium.
13. The method of claim 1, wherein said metal nuclei are formed by cobalt.
14. The method of claim 1, wherein said metal nuclei are formed by chromium. .Iadd.
15. A method of forming a via plug in a semiconductor device comprising:
providing a substrate;
forming a conductive layer overlying said substrate;
forming an insulating layer overlying said conductive layer;
forming a via structure in said insulating layer, which exposes a portion of said conductive layer;
forming metal nuclei and a plurality of grooves adjacent to said metal nuclei on said conductive layer within said exposed portion of said conductive layer to increase surface area of said conductive layer, wherein said plurality of grooves are formed by a buffered oxide etching process; and
forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.
16. The method of claim 15, further comprising pretreating said exposed portion of said conductive layer by an etching method..Iaddend..Iadd.17. The method of claim 15, wherein said metal nuclei are formed by a process including deposition..Iaddend..Iadd.18. The method of claim 15, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer..Iaddend..Iadd.19. The method of claim 15, wherein said insulating layer comprises a first insulating layer overlying said conductive layer, a second insulating layer overlying said first insulating layer, and a third insulating layer overlying said second insulating layer..Iaddend..Iadd.20. The method of claim 19, wherein said third insulating layer is planarized..Iaddend..Iadd.21. The method of claim 15, wherein said insulating layer is planarized..Iaddend..Iadd.22. The method of claim 15, wherein said metal nuclei comprise material selected from a group consisting of tungsten, aluminum, copper, molybdenum, titanium, cobalt, and chromium..Iaddend..Iadd.23. The method of claim 15, wherein each of said metal nuclei has a magnitude of 500 to 1,000 Å..Iaddend..Iadd.24. The method of claim 15, wherein said increased surface area reduces a via resistance..Iaddend..Iadd.25. The method of claim 15, wherein said increased surface area increases an
adhesive strength..Iaddend..Iadd.26. A method of forming a via plug in a semiconductor device comprising:
providing a substrate;
forming a conductive layer overlying said substrate;
forming an insulating layer overlying said conductive layer, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer;
forming a via structure in said insulating layer, which exposes a portion of said conductive layer;
forming metal nuclei and a plurality of grooves adjacent to said metal nuclei on said conductive layer within said exposed portion of said conductive layer to increase surface area of said conductive layer; and
forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.27. The method of claim 26, further comprising pretreating said exposed portion of said conductive layer by an etching method..Iaddend..Iadd.28. The method of claim 26, wherein said plurality of grooves are formed by a process including wet etching..Iaddend..Iadd.29. The method of claim 26, wherein said metal nuclei are formed by a process including deposition..Iaddend..Iadd.30. The method of claim 26, wherein said first insulating layer is over and in contact with said conductive layer and said second insulating layer is over and in contact with said first insulating layer..Iaddend..Iadd.31. The method of claim 26, wherein said metal nuclei comprise material selected from a group consisting of tungsten, aluminum, copper, molybdenum, titanium, cobalt, and chromium..Iaddend..Iadd.32. The method of claim 26, wherein each of said metal nuclei has a magnitude of 500 to 1,000 Å..Iaddend..Iadd.33. The method of claim 26, wherein said plurality of grooves is formed by a process including etching..Iaddend..Iadd.34. The method of claim 26, wherein said increased
surface area reduces a via resistance..Iaddend..Iadd.35. The method of claim 26, wherein said increased surface area increases an adhesive strength..Iaddend..Iadd.36. The method of claim 26, wherein said insulating layer further comprises a third insulating layer over said second insulating layer..Iaddend..Iadd.37. A method of forming a via plug in a semiconductor device comprising:
providing a substrate;
forming a conductive layer overlying said substrate;
forming an insulating layer overlying said conductive layer;
forming a via structure in said insulating layer, which exposes a portion of said conductive layer;
forming metal nuclei and a plurality of grooves adjacent to said metal nuclei on said conductive layer within said exposed portion of said conductive layer to increase surface area of said conductive layer, wherein said plurality of grooves is formed by etching; and
forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.38. The method of claim 37, further comprising pretreating said exposed portion of said conductive layer by a process including etching..Iaddend..Iadd.39. The method of claim 37, wherein said plurality of grooves are formed by a process including wet etching..Iaddend..Iadd.40. The method of claim 37, wherein said metal nuclei are formed by a process including deposition..Iaddend..Iadd.41. The method of claim 37, wherein said insulating layer comprises a first insulating layer over said conductive layer and a second insulating layer over said first insulating layer..Iaddend..Iadd.42. The method of claim 37, wherein said insulating layer comprises a first insulating layer over said conductive layer, a second insulating layer over said first insulating layer, and a third insulating layer over said second insulating layer..Iaddend..Iadd.43. The method of claim 37, wherein said insulating layer is planarized..Iaddend..Iadd.44. The method of claim 37, wherein said metal nuclei comprises material selected from a group consisting of tungsten, aluminum, copper, molybdenum, titanium, cobalt, and
chromium..Iaddend..Iadd.45. The method of claim 37, wherein each of said metal nuclei has a magnitude of 500 to 1,000 Å..Iaddend..Iadd.46. The method of claim 37, wherein said increased surface area reduces a via resistance..Iaddend..Iadd.47. The method of claim 37, wherein said increased surface area increases an adhesive strength..Iaddend..Iadd.48. A method of forming a plug layer in a semiconductor device comprising:
providing a substrate;
forming a conductive layer overlying said substrate;
forming an insulating layer overlying said conductive layer;
forming a via structure in said insulating layer, which exposes a portion of said conductive layer;
forming conductive nuclei and a plurality of grooves adjacent to said conductive nuclei on said conductive layer within said exposed portion of said conductive layer to increase surface area of said conductive layer, wherein said plurality of grooves is formed by a buffered oxide etching process; and
forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.49. The method of claim 48, further comprising pretreating said exposed portion of said conductive layer by a process including etching..Iaddend..Iadd.50. The method of claim 48, wherein said conductive nuclei are formed by a process including deposition..Iaddend..Iadd.51. The method of claim 48, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer..Iaddend..Iadd.52. The method of claim 48, wherein said insulating layer is planarized..Iaddend..Iadd.53. The method of claim 48, wherein said conductive nuclei comprise material selected from a group consisting of tungsten, aluminum, copper, molybdenum, titanium, cobalt,
and chromium..Iaddend..Iadd.54. The method of claim 48, wherein each of said conductive nuclei has a magnitude of 500 to 1,000 Å..Iaddend..Iadd.55. The method of claim 48, wherein said increased surface area reduces a via resistance..Iaddend..Iadd.56. The method of claim 48, wherein said increased surface area increases an adhesive strength..Iaddend..Iadd.57. The method of claim 48, wherein said insulating layer comprises a first insulating layer over said conductive layer, a second insulating layer over said first insulating layer, and a third insulating layer over said second insulating layer..Iaddend..Iadd.58. The method of claim 57, wherein said third insulating layer is planarized..Iaddend..Iadd.59. A method of forming a plug layer in a semiconductor device comprising:
providing a substrate;
forming a conductive layer overlying said substrate;
forming an insulating layer overlying said conductive layer, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer;
forming a via structure in said insulating layer, which exposes a portion of said conductive layer;
forming conductive nuclei and a plurality of grooves adjacent to said conductive nuclei on said conductive layer within said exposed portion of said conductive layer to increase surface area of said conductive layer; and
forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.60. The method of claim 59, further comprising pretreating said exposed portion of said conductive layer by a process including etching..Iaddend..Iadd.61. The method of claim 59, wherein said plurality of grooves are formed by a process including wet etching..Iaddend..Iadd.62. The method of claim 59, wherein said conductive nuclei are formed by a process including deposition..Iaddend..Iadd.63. The method of claim 59, wherein said first insulating layer is over and in contact with said conductive layer and said second insulating layer is
over and in contact with said first insulating layer..Iaddend..Iadd.64. The method of claim 59, wherein said conductive nuclei comprise material selected from a group consisting of tungsten, aluminum, copper, molybdenum, titanium, cobalt, and chromium..Iaddend..Iadd.65. The method of claim 59, wherein each of said conductive nuclei has a magnitude of 500 to 1,000 Å..Iaddend..Iadd.66. The method of claim 59, wherein said plurality of grooves is formed by a process including etching..Iaddend..Iadd.67. The method of claim 59, wherein said increased surface area reduces a via resistance..Iaddend..Iadd.68. The method of claim 59, wherein said increased surface area increases an adhesive strength..Iaddend..Iadd.69. The method of claim 59, wherein said insulating layer further comprises a third insulating layer over said second insulating layer..Iaddend..Iadd.70. A method of forming a plug layer in a semiconductor device comprising:
providing a substrate;
forming a conductive layer overlying said substrate;
forming an insulating layer overlying said conductive layer;
forming a via structure in said insulating layer, which exposes a portion of said conductive layer;
forming conductive nuclei and a plurality of grooves adjacent to said conductive nuclei on said conductive layer within said exposed portion of said conductive layer to increase surface area of said conductive layer, wherein said plurality of grooves is formed by etching; and
forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.71. The method of claim 70, further comprising pretreating said exposed portion of said conductive layer by an etching method..Iaddend..Iadd.72. The method of claim 70, wherein said plurality of grooves are formed by a wet etching process..Iaddend..Iadd.73. The method of claim 70, wherein said conductive nuclei are formed by a
deposition process..Iaddend..Iadd.74. The method of claim 70, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer..Iaddend..Iadd.75. The method of claim 70, wherein said insulating layer comprises a first insulating layer overlying said conductive layer, a second insulating layer overlying said first insulating layer, and a third insulating layer overlying said second insulating layer..Iaddend..Iadd.76. The method of claim 70, wherein said insulating layer is planarized..Iaddend..Iadd.77. The method of claim 70, wherein said conductive nuclei comprise material selected from a group consisting of tungsten, aluminum, copper, molybdenum, titanium, cobalt, and chromium..Iaddend..Iadd.78. The method of claim 70, wherein each of said conductive nuclei has a magnitude of 500 to 1,000 Å..Iaddend..Iadd.79. The method of claim 70, wherein said increased surface area reduces a via resistance..Iaddend..Iadd.80. The method of claim 70, wherein said increased surface area increases an adhesive strength..Iaddend..Iadd.81. A method of forming a plug layer in a semiconductor device, comprising:
providing a substrate;
forming a conductive layer overlying said substrate;
forming an insulating layer overlying said conductive layer;
forming a via structure in said insulating layer, which exposes a portion of said conductive layer;
forming nuclei and a plurality of grooves adjacent to said nuclei on said conductive layer within said exposed portion of said conductive layer to increase surface area of said conductive layer, wherein said plurality of grooves is formed by a buffered oxide etching process; and
forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.82. The method of claim 81, further comprising pretreating said exposed portion of said conductive layer by a process including etching..Iaddend..Iadd.83. The method of claim 81, wherein said
nuclei are formed by a process including deposition..Iaddend..Iadd.84. The method of claim 81, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer..Iaddend..Iadd.85. The method of claim 81, wherein said insulating layer is planarized..Iaddend..Iadd.86. The method of claim 81, wherein said nuclei comprise material selected from a group consisting of tungsten, aluminum, copper, molybdenum, titanium, cobalt, and chromium..Iaddend..Iadd.87. The method of claim 81, wherein each of said nuclei has a magnitude of 500 to 1,000 Å..Iaddend..Iadd.88. The method of claim 81, wherein said increased surface area reduces a via resistance..Iaddend..Iadd.89. The method of claim 81, wherein said increased surface area increases an adhesive strength..Iaddend..Iadd.90. The method of claim 81, wherein said insulating layer comprises a first insulating layer over said conductive layer, a second insulating layer over said first insulating layer, and a third insulating layer over said second insulating layer..Iaddend..Iadd.91. The method of claim 90, wherein said third insulating layer is planarized..Iaddend..Iadd.92. A method of forming a plug layer in a semiconductor device, comprising:
providing a substrate;
forming a conductive layer overlying said substrate;
forming an insulating layer overlying said conductive layer, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer;
forming a via structure in said insulating layer, which exposes a portion of said conductive layer;
forming nuclei and a plurality of grooves adjacent to said nuclei on said conductive layer within said exposed portion of said conductive layer to increase surface area of said conductive layer; and
forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.93. The method of claim 92, further comprising pretreating said exposed portion of said conductive layer by an etching method..Iaddend..Iadd.94. The method of claim 92, wherein said plurality of grooves are formed by a process including wet
etching..Iaddend..Iadd. The method of claim 92, wherein said nuclei are formed by a process including deposition..Iaddend..Iadd.96. The method of claim 92, wherein said first insulating layer is over and in contact with said conductive layer and said second insulating layer is over and in contact with said first insulating layer..Iaddend..Iadd.97. The method of claim 92, wherein said nuclei comprise material selected from a group consisting of tungsten, aluminum, copper, molybdenum, titanium, cobalt, and chromium..Iaddend..Iadd.98. The method of claim 92, wherein each of said nuclei has a magnitude of 500 to 1,000 Å..Iaddend..Iadd.99. The method of claim 92, wherein said plurality of grooves is formed by a process including etching..Iaddend..Iadd.100. The method of claim 92, wherein said increased surface area reduces a via resistance..Iaddend..Iadd.101. The method of claim 92, wherein said increased surface area increases an adhesive strength..Iaddend..Iadd.102. The method of claim 92, wherein said insulating layer further comprises a third insulating layer overlying said second insulating
layer..Iaddend..Iadd.103. A method of forming a plug layer in a semiconductor device, comprising:
providing a substrate;
forming a conductive layer overlying said substrate;
forming an insulating layer overlying said conductive layer;
forming a via structure in said insulating layer, which exposes a portion of said conductive layer;
forming nuclei and a plurality of grooves adjacent to said nuclei on said conductive layer within said exposed portion of said conductive layer to increase surface area of said conductive layer, wherein said plurality of grooves is formed by etching; and
forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.104. The method of claim 103, further comprising pretreating said exposed portion of said conductive layer by a process including etching..Iaddend..Iadd.105. The method of claim 103, wherein said plurality of grooves are formed by a process including wet etching..Iaddend..Iadd.106. The method of claim 103, wherein said nuclei are formed by a process including deposition..Iaddend..Iadd.107. The method of claim 103, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer..Iaddend..Iadd.108. The method of claim 103, wherein said insulating layer comprises a first insulating layer overlying said conductive layer, a second insulating layer overlying said first insulating layer, and a third insulating layer overlying said second insulating layer..Iaddend..Iadd.109. The method of claim 103, wherein said insulating layer is planarized..Iaddend..Iadd.110. The method of claim 103, wherein said nuclei comprise material selected from a group consisting of tungsten, aluminum, copper, molybdenum, titanium, cobalt, and chromium..Iaddend..Iadd.111. The method of claim 103, wherein each of said nuclei has a magnitude of 500 to 1,000 Å..Iaddend..Iadd.112. The method of claim 103, wherein said increased surface area reduces a via
resistance..Iaddend..Iadd.113. The method of claim 103, wherein said increased surface area increases an adhesive strength..Iaddend..Iadd.114. A method of forming a semiconductor device comprising:
providing a substrate;
forming a conductive layer overlying said substrate;
forming an insulating layer overlying said conductive layer;
forming a via structure in said insulating layer, which exposes a portion of said conductive layer;
forming a plurality of grooves on said conductive layer within said exposed portion of said conductive layer to increase surface area of said conductive layer, wherein said plurality of grooves is formed by a buffered oxide etching process; and
forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.115. The method of claim 114, further comprising pretreating said exposed portion of said conductive layer by a process including etching..Iaddend..Iadd.116. The method of claim 114, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer..Iaddend..Iadd.117. The method of claim 114, wherein said insulating layer is planarized..Iaddend..Iadd.118. The method of claim 114, wherein said increased surface area reduces a via resistance..Iaddend..Iadd.119. The method of claim 114, wherein said increased surface area increases an adhesive strength..Iaddend..Iadd.120. The method of claim 114, wherein said insulating layer comprises a first insulating layer over said conductive layer, a second insulating layer over said first insulating layer, and a third insulating layer over said second insulating layer..Iaddend..Iadd.121. The method of claim 120, wherein said third insulating layer is planarized..Iaddend..Iadd.122. A method of forming a semiconductor device comprising:
providing a substrate;
forming a conductive layer overlying said substrate;
forming an insulating layer overlying said conductive layer, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer;
forming a via structure in said insulating layer, which exposes a portion of said conductive layer;
forming a plurality of grooves on said conductive layer within said exposed portion of said conductive layer to increase surface area of said conductive layer; and
forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.123. The method of claim 122, further comprising pretreating said exposed portion of said conductive layer by a process
including etching..Iaddend..Iadd.124. The method of claim 122, wherein said plurality of grooves are formed by a process including wet etching..Iaddend..Iadd.125. The method of claim 122, wherein said first insulating layer is over and in contact with said conductive layer and said second insulating layer is over and in contact with said first insulating layer..Iaddend..Iadd.126. The method of claim 122, wherein said plurality of grooves is formed by a process including etching..Iaddend..Iadd.127. The method of claim 122, wherein said increased surface area reduces a via resistance..Iaddend..Iadd.128. The method of claim 122, wherein said increased surface area increases an adhesive strength..Iaddend..Iadd.129. The method of claim 122, wherein said insulating layer further comprises a third insulating layer over said second insulating layer..Iaddend..Iadd.130. A method of forming a semiconductor device comprising:
providing a substrate;
forming a conductive layer overlying said substrate;
forming an insulating layer overlying said conductive layer;
forming a via structure in said insulating layer, which exposes a portion of said conductive layer;
forming a plurality of grooves on said conductive layer within said exposed portion of said conductive layer to increase surface area of said conductive layer, wherein said plurality of grooves is formed by etching; and
forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.131. The method of claim 130, further comprising pretreating said exposed portion of said conductive layer by a process including etching..Iaddend..Iadd.132. The method of claim 130, wherein said plurality of grooves are formed by a process including wet
etching..Iaddend..Iadd.133. The method of claim 130, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer..Iaddend..Iadd.134. The method of claim 130, wherein said insulating layer is planarized..Iaddend..Iadd.135. The method of claim 130, wherein said increased surface area reduces a via resistance..Iaddend..Iadd.136. The method of claim 130, wherein said increased surface area increases an adhesive strength..Iaddend..Iadd.137. The method of claim 130, wherein said insulating layer comprises a first insulating layer over said conductive layer, a second insulating layer over said first insulating layer, and a third insulating layer over said second insulating layer..Iaddend..Iadd.138. A method of forming a semiconductor device comprising:
providing a substrate;
forming a conductive layer overlying said substrate;
forming an insulating layer overlying said conductive layer;
forming a via structure in said insulating layer, which exposes a portion of said conductive layer;
forming a plurality of grooves on said conductive layer within said exposed portion of said conductive layer to increase adhesive strength of said conductive layer, wherein said plurality of grooves is formed by a buffered oxide etching process; and
forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.139. The method of claim 138, comprising pretreating said exposed portion of said conductive layer by a process including etching..Iaddend..Iadd.140. The method of claim 138, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer..Iaddend..Iadd.141. The method of claim 138, wherein said insulating layer comprises a first insulating layer overlying said conductive layer, a second insulating layer overlying said first insulating layer, and a third insulating layer overlying said second insulating layer..Iaddend..Iadd.142. The method of claim 138, wherein said
insulating layer is planarized..Iaddend..Iadd.143. The method of claim 138, wherein said increased adhesive strength reduces a via resistance..Iaddend..Iadd.144. The method of claim 138, wherein said insulating layer comprises a first insulating layer overlying and in contact with said conductive layer, a second insulating layer overlying and in contact with said first insulating layer, and a third insulating layer overlying said second insulating layer..Iaddend..Iadd.145. The method of claim 144, wherein said third insulating layer is planarized..Iaddend..Iadd.146. A method of forming a semiconductor device comprising:
providing a substrate;
forming a conductive layer overlying said substrate;
forming an insulating layer overlying said conductive layer, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer;
forming a via structure in said insulating layer, which exposes a portion of said conductive layer;
forming a plurality of grooves on said conductive layer within said exposed portion of said conductive layer to increase adhesive strength of said conductive layer; and
forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.147. The method of claim 146, further comprising pretreating said exposed portion of said conductive layer by a process including etching..Iaddend..Iadd.148. The method of claim 146, wherein said plurality of grooves are formed by a process including wet etching..Iaddend..Iadd.149. The method of claim 146, wherein said first insulating layer is over said conductive layer and said second insulating layer is over said first insulating layer..Iaddend..Iadd.150. The method of claim 146, wherein said plurality of grooves is formed by a process including etching..Iaddend..Iadd.151. The method of claim 146, wherein said increased adhesive strength reduces a via resistance..Iaddend..Iadd.152. The method of claim 146, wherein said insulating layer further comprises a third insulating layer over said
second insulating layer..Iaddend..Iadd.153. A method of forming a semiconductor device comprising:
providing a substrate;
forming a conductive layer overlying said substrate;
forming an insulating layer overlying said conductive layer;
forming a via structure in said insulating layer, which exposes a portion of said conductive layer;
forming a plurality of grooves on said conductive layer within said exposed portion of said conductive layer to increase adhesive strength of said conductive layer, wherein said plurality of grooves is formed by etching; and
forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.154. The method of claim 153, further comprising pretreating said exposed portion of said conductive layer by a process including etching..Iaddend..Iadd.155. The method of claim 153, wherein said plurality of grooves are formed by a process including wet etching..Iaddend..Iadd.156. The method of claim 153, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer..Iaddend..Iadd.157. The method of claim 153, wherein said insulating layer comprises a first insulating layer overlying said conductive layer, a second insulating layer overlying said first insulating layer, and a third insulating layer overlying said second insulating layer..Iaddend..Iadd.158. The method of claim 153, wherein said insulating layer is planarized..Iaddend..Iadd.159. The method of claim 153, wherein said increased adhesive strength reduces a via resistance..Iaddend.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/734,784 USRE36475E (en) | 1993-09-15 | 1996-10-15 | Method of forming a via plug in a semiconductor device |
| US09/293,207 USRE38383E1 (en) | 1993-09-15 | 1999-04-16 | Method for forming a via plug in a semiconductor device |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930018525A KR100188645B1 (en) | 1993-09-15 | 1993-09-15 | Via plug forming method of semiconductor device |
| KR93-18525 | 1993-09-15 | ||
| US08/305,306 US5409861A (en) | 1993-09-15 | 1994-09-15 | Method of forming a via plug in a semiconductor device |
| US08/734,784 USRE36475E (en) | 1993-09-15 | 1996-10-15 | Method of forming a via plug in a semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US08/305,306 Reissue US5409861A (en) | 1993-09-15 | 1994-09-15 | Method of forming a via plug in a semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US08/305,306 Continuation US5409861A (en) | 1993-09-15 | 1994-09-15 | Method of forming a via plug in a semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| USRE36475E true USRE36475E (en) | 1999-12-28 |
Family
ID=27348999
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US08/734,784 Expired - Lifetime USRE36475E (en) | 1993-09-15 | 1996-10-15 | Method of forming a via plug in a semiconductor device |
| US09/293,207 Expired - Lifetime USRE38383E1 (en) | 1993-09-15 | 1999-04-16 | Method for forming a via plug in a semiconductor device |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US09/293,207 Expired - Lifetime USRE38383E1 (en) | 1993-09-15 | 1999-04-16 | Method for forming a via plug in a semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| US (2) | USRE36475E (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6319817B1 (en) * | 1995-10-23 | 2001-11-20 | Sony Corporation | Method of forming viahole |
| US6333276B1 (en) * | 1997-07-18 | 2001-12-25 | Nec Corporation | Semiconductor device and method of forming semiconductor device |
| US20030000845A1 (en) * | 2001-06-20 | 2003-01-02 | Thomas Brinz | Method for creating a material library |
| USRE38383E1 (en) * | 1993-09-15 | 2004-01-13 | Hyundai Electronics Industries Co. Ltd. | Method for forming a via plug in a semiconductor device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9935051B2 (en) * | 2016-08-18 | 2018-04-03 | International Business Machines Corporation | Multi-level metallization interconnect structure |
| JP7067616B2 (en) * | 2018-04-18 | 2022-05-16 | 株式会社村田製作所 | Capacitors and their manufacturing methods |
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Also Published As
| Publication number | Publication date |
|---|---|
| USRE38383E1 (en) | 2004-01-13 |
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