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USH842H - Metal conductor structure having low electro-migration at high currents for semiconductor devices - Google Patents

Metal conductor structure having low electro-migration at high currents for semiconductor devices Download PDF

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Publication number
USH842H
USH842H US07/374,116 US37411689A USH842H US H842 H USH842 H US H842H US 37411689 A US37411689 A US 37411689A US H842 H USH842 H US H842H
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US
United States
Prior art keywords
conductors
current
metal conductor
metal
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US07/374,116
Inventor
Christopher D. Ochs
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AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Priority to US07/374,116 priority Critical patent/USH842H/en
Assigned to AMERICAN TELEPHONE AND TELEGRAPH COMPANY, 550 MADISON AVENUE, NEW YORK, NY 10022-3201 A CORP. OF NY, BELL TELEPHONE LABORATORIES, INCORPORATED, 600 MOUNTAIN AVENUE, MURRAY HILL, NEW JERSEY, 07974-2070 A CORP. OF NY reassignment AMERICAN TELEPHONE AND TELEGRAPH COMPANY, 550 MADISON AVENUE, NEW YORK, NY 10022-3201 A CORP. OF NY ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: OCHS, CHRISTOPHER D.
Application granted granted Critical
Publication of USH842H publication Critical patent/USH842H/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates to integrated circuits in general and, more particularly, to metal conductors on integrated circuits.
  • Very large scale integrated circuits such as microprocessors
  • logic circuitry buffers
  • external logic circuits such as buffers for driving an address or data bus.
  • the buffers supply relatively large output currents to drive the external logic circuits.
  • the transistors in the buffers are designed to handle more current than their counterparts in the internal logic circuitry.
  • a consequence of using high currents in an integrated circuit (IC) with metal conductors is electro-migration of the metal.
  • Aluminum conductors or aluminum alloyed with copper suffer from electro-migration when the current density in the conductor exceeds a predetermined maximum amount. Electro-migration can lead to premature failure of the IC unless proper care is taken to ensure that the current density in any one conductor does not exceed the predetermined maximum.
  • the metal conductors, within and coupling from the buffers are therefore larger (wider) than the metal conductors interconnecting the internal logic circuitry.
  • a common approach utilizes multiple parallel transistors therein, each transistor being similar in size to other transistors in the IC.
  • Each transistor via relatively thin metal conductors, couples to a relatively wide metal conductor designed to carry the larger current.
  • This approach suffers from wasting large amounts of area on the IC for the buffers due to the relative area inefficiency of the wide metal conductors coupling to the parallel transistors.
  • Still another common approach utilizes one or more relatively large transistors in parallel with the relatively wide metal conductor coupling directly to each transistor.
  • the width of the metal conductor is chosen to minimize the electro-migration of the conductor under a maximum design current flow.
  • this approach suffers from wasting large amounts of area on the IC for the buffers due to the inefficient use of the wide metal conductors to couple to the relatively large transistors.
  • the invention can be applied to parallel transistors in such a way to result in a very area efficient design.
  • the invention may be viewed as a method of fabricating high current carrying metal conductors on an IC by tapering the conductors along the axis of current flow, along with conducting current to or from the conductor along the axis, such that the current density therein is substantially constant along the axis.
  • FIG. 1 is an exemplary high current capacity MOSFET embodying the invention in a first level of metal
  • FIG. 2 is an exemplary multiple high current transistors paralleled and embodying the invention in both a first and a second level of metal.
  • metal conductors such as the widths thereof, on an integrated circuit such that the current density therein is substantially constant by conducting current to or from the conductor along the tapered portion thereof, yet less than a predetermined maximum, high density, high current capacity semiconductor devices can be achieved.
  • This aspect of the invention allows, for example, a single transistor to carry large currents without suffering from the electro-migration of the metal conductors coupling thereto. Electro-migration is not a problem so long as the current density is less than the predetermined maximum, which is the maximum allowed for the type of metal used for the conductor to minimize the electro-migration thereof. For aluminum or aluminum alloyed with copper (typically 5% copper), the maximum current density is an exemplary 10 5 A cm -2 . Other metals, however, also experience electro-migration and are, therefore, within the scope of the invention.
  • An exemplary "rough” feature is a contact window in which the metal conductor contacts a different layer of metal or an underlaying semiconductor surface, such as contacting a source or drain semiconductor region of a metal-oxide-semiconductor field-effect transistor (MOSFET).
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • an exemplary MOSFET 10 (not to scale) is shown utilizing metal conductors 11, 12 tapered along the widths thereof to conduct current to and from the drain 13 and source 14 regions of MOSFET 10.
  • Drain 13 and source 14 regions are conventional diffusions or replants into a semiconductor layer (not shown) and are shown for illustrative purposes only.
  • Contacts 15, such as vias couple the conductors 11, 12 to the corresponding drain 13 and source 14 regions.
  • Arrow 16 shows the relative direction of current in the conductors.
  • Conductor 18, typically polysilicon forms the gate electrode of the MOSFET 10.
  • the amount of currents carried by each contact 15 is substantially the same, allowing for the uniform spacing of the contacts along the tapered metal conductors 11, 12.
  • the amount of current removed from conductor 11 (and, similarly, added to conductor 12) is substantially uniform at each contact.
  • the width of the conductors 11, 12 is tapered along the elongated axis of the conductor so as to form a trapezoidal shape; the widest portion of the taper occurs where the current is the heaviest.
  • each contact 15 carries substantially equal current
  • the cross-sectional area of the conductor 11, 12 immediately adjacent to a given contact 15 must increase proportionally.
  • each conductor 11, 12 is shown with six contacts. If the width of the conductor 11 at the contact 15 nearest the narrowest portion of the taper is X, then the widest width of the conductor 11 is approximately six times X, assuming uniform thickness of the conductor.
  • conductor 12 varies in width along the contacts 15 corresponding thereto.
  • the current densities in the conductors 11, 12 are substantially constant along the length of the conductors 11, 12. This design has allowed MOSFETs to carry more than three times the current without an increase in area, compared to MOSFET designs of the prior art.
  • the contacts 15 are disposed along the center of the conductors 11, 12 and are regularly spaced. It is understood, however, that the current conducted by each contact 15 need not be substantially the same nor in the center of the corresponding conductors 11, 12. Should the current conducted by each contact 15 be substantially different, a different taper would be necessary to achieve the substantially constant current density requirement, such as an logarithmic taper. Further, the taper need not be regular (symmetric) if the contacts 15 are not along the center axis of the corresponding conductors 11, 12.
  • the edges of the taper as shown in FIG. 1 are smooth. But because of lithographic restrictions due to the processing equipment used to manufacture ICs, the taper may be composed of rectangles of varying widths and lengths to approximate the desired taper.
  • FIG. 2 (not to scale), an exemplary structure of paralleled MOSFETs 20 are shown with drain 21,21' regions and source 22,22' regions, regions 21' and 22' being shared.
  • Contacts 23 couple regions 21,21',22,22' to corresponding metal conductors 24, 25, similar to that shown in FIG. 1.
  • the widths of conductors 24,25 are tapered to have substantially constant current density therein and are, as shown here, disposed in the first level of metal above the semiconductor substrate (not shown).
  • Conductors 24, 25 are correspondingly interconnected via contacts 26 to conductors 27, 28, shown here disposed in the second layer of metal above the semiconductor substrate (not shown). It is noted that the two conductors 27 may be merged into one conductor (not shown) for convenience.
  • Conductors 27, 28 are tapered along the direction of current flow such that the current density therein is also substantially constant, as described above in connection with FIG. 1.
  • MOSFET 10 of FIG. 1 are also applicable to the structure shown in FIG. 2 and may be applied in either layer of metal.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A technique for providing high current carrying metal conductors for coupling to transistors or the like to increase the current carrying capacity of the transistor without substantial increase in size. The conductors are tapered along the axis of current flow with current being conducted to or from the tapered portion of the conductors, such that the current density therein is substantially constant.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuits in general and, more particularly, to metal conductors on integrated circuits.
2. Description of the Prior Art
Very large scale integrated circuits, such as microprocessors, have logic circuitry (buffers) which drive external logic circuits, such as buffers for driving an address or data bus. Compared to the logic circuit which are internal to the microprocessor, the buffers supply relatively large output currents to drive the external logic circuits. Hence, the transistors in the buffers are designed to handle more current than their counterparts in the internal logic circuitry.
A consequence of using high currents in an integrated circuit (IC) with metal conductors is electro-migration of the metal. Aluminum conductors (or aluminum alloyed with copper) suffer from electro-migration when the current density in the conductor exceeds a predetermined maximum amount. Electro-migration can lead to premature failure of the IC unless proper care is taken to ensure that the current density in any one conductor does not exceed the predetermined maximum. To keep the current density below the predetermined maximum, the metal conductors, within and coupling from the buffers, are therefore larger (wider) than the metal conductors interconnecting the internal logic circuitry.
For the buffer to achieve the larger current carrying capacity, a common approach utilizes multiple parallel transistors therein, each transistor being similar in size to other transistors in the IC. Each transistor, via relatively thin metal conductors, couples to a relatively wide metal conductor designed to carry the larger current. This approach suffers from wasting large amounts of area on the IC for the buffers due to the relative area inefficiency of the wide metal conductors coupling to the parallel transistors.
Still another common approach utilizes one or more relatively large transistors in parallel with the relatively wide metal conductor coupling directly to each transistor. The width of the metal conductor is chosen to minimize the electro-migration of the conductor under a maximum design current flow. As with the multiple transistor approach, above, this approach suffers from wasting large amounts of area on the IC for the buffers due to the inefficient use of the wide metal conductors to couple to the relatively large transistors.
It is noted that the cost of having larger than necessary buffers, of which there can be hundreds in a particular IC, is the reduced area available on the IC for other logic circuits. This constraint can detrimentally impact the functions or features desired from the IC.
SUMMARY OF THE INVENTION
It has been found that by tapering metal conductors on the IC along with means to conduct current to or from the metal conductor along the tapered portion thereof so as to have a substantially constant current density therein, large currents can be handled by those conductors with minimum area and without suffering from electro-migration effects. This technique can be applied to transistors, diodes or other similar devices, so that the devices can carry relatively large currents without the need for paralleling the devices. This aspect of the invention reduces the amount of area required on the IC for a device with a given current carrying capacity.
However, should extremely high current capacity be desired, the invention can be applied to parallel transistors in such a way to result in a very area efficient design.
Further, the invention may be viewed as a method of fabricating high current carrying metal conductors on an IC by tapering the conductors along the axis of current flow, along with conducting current to or from the conductor along the axis, such that the current density therein is substantially constant along the axis.
BRIEF DESCRIPTION OF THE DRAWING
The foregoing features of this invention, as well as the invention itself, may be more fully understood from the following detailed description of the drawings, in which:
FIG. 1 is an exemplary high current capacity MOSFET embodying the invention in a first level of metal; and,
FIG. 2 is an exemplary multiple high current transistors paralleled and embodying the invention in both a first and a second level of metal.
DETAILED DESCRIPTION
By tapering metal conductors, such as the widths thereof, on an integrated circuit such that the current density therein is substantially constant by conducting current to or from the conductor along the tapered portion thereof, yet less than a predetermined maximum, high density, high current capacity semiconductor devices can be achieved. This aspect of the invention allows, for example, a single transistor to carry large currents without suffering from the electro-migration of the metal conductors coupling thereto. Electro-migration is not a problem so long as the current density is less than the predetermined maximum, which is the maximum allowed for the type of metal used for the conductor to minimize the electro-migration thereof. For aluminum or aluminum alloyed with copper (typically 5% copper), the maximum current density is an exemplary 105 A cm-2. Other metals, however, also experience electro-migration and are, therefore, within the scope of the invention.
It has been discovered that the maximum current density in a metal conductor is greater where the conductor covers "smooth" features on the IC rather than "rough" features. An exemplary "rough" feature is a contact window in which the metal conductor contacts a different layer of metal or an underlaying semiconductor surface, such as contacting a source or drain semiconductor region of a metal-oxide-semiconductor field-effect transistor (MOSFET). Hence, the conductors should be disposed in such a way that the minimum number of "rough" features are beneath the conductors.
EXEMPLARY EMBODIMENTS
In FIG. 1, an exemplary MOSFET 10 (not to scale) is shown utilizing metal conductors 11, 12 tapered along the widths thereof to conduct current to and from the drain 13 and source 14 regions of MOSFET 10. Drain 13 and source 14 regions are conventional diffusions or replants into a semiconductor layer (not shown) and are shown for illustrative purposes only. Contacts 15, such as vias, couple the conductors 11, 12 to the corresponding drain 13 and source 14 regions. Arrow 16 shows the relative direction of current in the conductors. Conductor 18, typically polysilicon, forms the gate electrode of the MOSFET 10. As shown, the amount of currents carried by each contact 15 is substantially the same, allowing for the uniform spacing of the contacts along the tapered metal conductors 11, 12. Hence, the amount of current removed from conductor 11 (and, similarly, added to conductor 12) is substantially uniform at each contact.
As shown, the width of the conductors 11, 12 is tapered along the elongated axis of the conductor so as to form a trapezoidal shape; the widest portion of the taper occurs where the current is the heaviest. Assuming that each contact 15 carries substantially equal current, then the cross-sectional area of the conductor 11, 12 immediately adjacent to a given contact 15 must increase proportionally. For example, each conductor 11, 12 is shown with six contacts. If the width of the conductor 11 at the contact 15 nearest the narrowest portion of the taper is X, then the widest width of the conductor 11 is approximately six times X, assuming uniform thickness of the conductor. Similarly, conductor 12 varies in width along the contacts 15 corresponding thereto. Hence, the current densities in the conductors 11, 12 are substantially constant along the length of the conductors 11, 12. This design has allowed MOSFETs to carry more than three times the current without an increase in area, compared to MOSFET designs of the prior art.
In FIG. 1, the contacts 15 are disposed along the center of the conductors 11, 12 and are regularly spaced. It is understood, however, that the current conducted by each contact 15 need not be substantially the same nor in the center of the corresponding conductors 11, 12. Should the current conducted by each contact 15 be substantially different, a different taper would be necessary to achieve the substantially constant current density requirement, such as an logarithmic taper. Further, the taper need not be regular (symmetric) if the contacts 15 are not along the center axis of the corresponding conductors 11, 12.
It is also understood that the edges of the taper as shown in FIG. 1 are smooth. But because of lithographic restrictions due to the processing equipment used to manufacture ICs, the taper may be composed of rectangles of varying widths and lengths to approximate the desired taper.
In FIG. 2 (not to scale), an exemplary structure of paralleled MOSFETs 20 are shown with drain 21,21' regions and source 22,22' regions, regions 21' and 22' being shared. Contacts 23 couple regions 21,21',22,22' to corresponding metal conductors 24, 25, similar to that shown in FIG. 1. The widths of conductors 24,25 are tapered to have substantially constant current density therein and are, as shown here, disposed in the first level of metal above the semiconductor substrate (not shown). Conductors 24, 25 are correspondingly interconnected via contacts 26 to conductors 27, 28, shown here disposed in the second layer of metal above the semiconductor substrate (not shown). It is noted that the two conductors 27 may be merged into one conductor (not shown) for convenience. Current flow in conductors 27, 28 is shown by arrows 29. As shown, the conductors 27, 28 are tapered along the direction of current flow such that the current density therein is also substantially constant, as described above in connection with FIG. 1. Conductors 30, typically polysilicon, form the gate electrodes for the MOSFET 20.
The above described concepts and implementations of the MOSFET 10 of FIG. 1 are also applicable to the structure shown in FIG. 2 and may be applied in either layer of metal.
It is noted that although the examples given here are for MOSFETs, this technique can also be applied to bipolar transistors, diodes, diffused resistors, etc., or wherever a single conductor supplies high current to a plurality of loads along the length of the conductor.
Having described the preferred embodiment of this invention, it will now be apparent to one of skill in the art that other embodiments incorporating its concept may be used. It is felt, therefore, that this invention should not be limited to the disclosed embodiment, but rather should be limited only by the spirit and scope of the appended claims.

Claims (3)

I claim:
1. An integrated circuit having at least one metal conductor and at least one MOSFET, the MOSFET having a drain region and a source region, characterized by:
multiple contacts, coupled to the metal conductor along a major axis thereof, for conducting current to or from the metal conductor and the drain or source regions; and,
the metal conductor being tapered along the major axis thereof;
wherein the current density in the metal conductor is substantially constant along the major axis.
2. The integrated circuit as recited in claim 1, wherein the metal conductor is tapered into the shape of a trapezoid.
3. The integrated circuit as recited in claim 2, wherein the MOSFET has both the source and drain regions coupling to corresponding tapered metal conductors.
US07/374,116 1989-06-30 1989-06-30 Metal conductor structure having low electro-migration at high currents for semiconductor devices Abandoned USH842H (en)

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Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5737580A (en) * 1995-04-28 1998-04-07 International Business Machines Corporation Wiring design tool improvement for avoiding electromigration by determining optimal wire widths
US5977595A (en) * 1996-06-27 1999-11-02 Samsung Electronics, Co., Ltd. Apparatus and method for electrostatic discharge protection with improved current dispersion
US6126459A (en) * 1997-03-24 2000-10-03 Ford Motor Company Substrate and electrical connector assembly
US6274896B1 (en) 2000-01-14 2001-08-14 Lexmark International, Inc. Drive transistor with fold gate
US6657280B1 (en) 2000-11-13 2003-12-02 International Business Machines Corporation Redundant interconnect high current bipolar device
US6713374B2 (en) 1999-07-30 2004-03-30 Formfactor, Inc. Interconnect assemblies and methods
US6780001B2 (en) 1999-07-30 2004-08-24 Formfactor, Inc. Forming tool for forming a contoured microelectronic spring mold
US6888362B2 (en) 2000-11-09 2005-05-03 Formfactor, Inc. Test head assembly for electronic components with plurality of contoured microelectronic spring contacts
US6939474B2 (en) 1999-07-30 2005-09-06 Formfactor, Inc. Method for forming microelectronic spring structures on a substrate
US20060192194A1 (en) * 2003-04-15 2006-08-31 Luminus Devices, Inc. Electronic device contact structures
US7189077B1 (en) 1999-07-30 2007-03-13 Formfactor, Inc. Lithographic type microelectronic spring structures with improved contours
US20070108617A1 (en) * 2005-09-30 2007-05-17 Infineon Technologies Ag Semiconductor component comprising interconnected cell strips
US20070114636A1 (en) * 2005-11-18 2007-05-24 Luminus Devices, Inc. Electronic device contact structures
US20080092100A1 (en) * 2006-10-16 2008-04-17 Maziasz Robert L System and method for electromigration tolerant cell synthesis
US7435108B1 (en) 1999-07-30 2008-10-14 Formfactor, Inc. Variable width resilient conductive contact structures
US20100117162A1 (en) * 2006-10-24 2010-05-13 Austriamicrosystems Ag Semiconductor Body and Method for the Design of a Semiconductor Body with a Connecting Line
US20110113397A1 (en) * 2009-11-11 2011-05-12 Green Solution Technology Co., Ltd. Layout structure of mosfet and layout method thereof
US20130033301A1 (en) * 2011-08-05 2013-02-07 Himax Technologies Limited Structure of output stage
US8624335B2 (en) * 2011-04-30 2014-01-07 Peregrine Semiconductor Corporation Electronic module metalization system, apparatus, and methods of forming same
US20140117453A1 (en) * 2012-10-31 2014-05-01 International Business Machines Corporation Local interconnects for field effect transistor devices

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Title
Braen, IBM Bulletin-Power Distr. for LSID, Dec. 1973 vol. 16 No. 7 p. 2308.
Layout Plot Of An Exemplary High-Current Capacity MOS Transistor Of The Prior Art From A Proprietary CMOS IC.

Cited By (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5737580A (en) * 1995-04-28 1998-04-07 International Business Machines Corporation Wiring design tool improvement for avoiding electromigration by determining optimal wire widths
US5977595A (en) * 1996-06-27 1999-11-02 Samsung Electronics, Co., Ltd. Apparatus and method for electrostatic discharge protection with improved current dispersion
US6126459A (en) * 1997-03-24 2000-10-03 Ford Motor Company Substrate and electrical connector assembly
US7435108B1 (en) 1999-07-30 2008-10-14 Formfactor, Inc. Variable width resilient conductive contact structures
US7675301B2 (en) 1999-07-30 2010-03-09 Formfactor, Inc. Electronic components with plurality of contoured microelectronic spring contacts
US6713374B2 (en) 1999-07-30 2004-03-30 Formfactor, Inc. Interconnect assemblies and methods
US6780001B2 (en) 1999-07-30 2004-08-24 Formfactor, Inc. Forming tool for forming a contoured microelectronic spring mold
US20070269997A1 (en) * 1999-07-30 2007-11-22 Formfactor, Inc. Electronic components with plurality of contoured microelectronic spring contacts
US20090035959A1 (en) * 1999-07-30 2009-02-05 Formfactor, Inc. Interconnect assemblies and methods
US6939474B2 (en) 1999-07-30 2005-09-06 Formfactor, Inc. Method for forming microelectronic spring structures on a substrate
US7524194B2 (en) 1999-07-30 2009-04-28 Formfactor, Inc. Lithographic type microelectronic spring structures with improved contours
US7189077B1 (en) 1999-07-30 2007-03-13 Formfactor, Inc. Lithographic type microelectronic spring structures with improved contours
US6274896B1 (en) 2000-01-14 2001-08-14 Lexmark International, Inc. Drive transistor with fold gate
US20050189956A1 (en) * 2000-11-09 2005-09-01 Formfactor, Inc. Electronic components with plurality of contoured microelectronic spring contacts
US7245137B2 (en) 2000-11-09 2007-07-17 Formfactor, Inc. Test head assembly having paired contact structures
US6888362B2 (en) 2000-11-09 2005-05-03 Formfactor, Inc. Test head assembly for electronic components with plurality of contoured microelectronic spring contacts
US20060175634A1 (en) * 2000-11-13 2006-08-10 International Business Machines Corporation Redundant interconnect high current bipolar device and method of forming the device
US6998699B2 (en) 2000-11-13 2006-02-14 International Business Machines Corporation Redundant interconnect high current bipolar device and method of forming the device
US20050189618A1 (en) * 2000-11-13 2005-09-01 Hulvey Michael D. Redundant interconnect high current bipolar device and method of forming the device
US6657280B1 (en) 2000-11-13 2003-12-02 International Business Machines Corporation Redundant interconnect high current bipolar device
US7317240B2 (en) 2000-11-13 2008-01-08 International Business Machines Corporation Redundant interconnect high current bipolar device and method of forming the device
US7482640B2 (en) * 2003-04-15 2009-01-27 Luminus Devices, Inc. Electronic device contact structures
US8217415B2 (en) 2003-04-15 2012-07-10 Luminus Devices, Inc. Electronic device contact structures
US20090230545A1 (en) * 2003-04-15 2009-09-17 Luminus Devices, Inc. Electronic device contact structures
US20060192194A1 (en) * 2003-04-15 2006-08-31 Luminus Devices, Inc. Electronic device contact structures
US20070108617A1 (en) * 2005-09-30 2007-05-17 Infineon Technologies Ag Semiconductor component comprising interconnected cell strips
US7687912B2 (en) * 2005-09-30 2010-03-30 Infineon Technologies Ag Semiconductor component comprising interconnected cell strips
US20070114636A1 (en) * 2005-11-18 2007-05-24 Luminus Devices, Inc. Electronic device contact structures
US7598531B2 (en) 2005-11-18 2009-10-06 Luminus Devices, Inc. Electronic device contact structures
US20080092100A1 (en) * 2006-10-16 2008-04-17 Maziasz Robert L System and method for electromigration tolerant cell synthesis
US7721245B2 (en) 2006-10-16 2010-05-18 Freescale Semiconductor, Inc. System and method for electromigration tolerant cell synthesis
US20100117162A1 (en) * 2006-10-24 2010-05-13 Austriamicrosystems Ag Semiconductor Body and Method for the Design of a Semiconductor Body with a Connecting Line
US8399937B2 (en) * 2006-10-24 2013-03-19 Austriamicrosystems Ag Semiconductor body and method for the design of a semiconductor body with a connecting line
DE112007002288B4 (en) * 2006-10-24 2017-03-02 Austriamicrosystems Ag Semiconductor body with a connecting line and a transistor or a diode comprising this and a method for designing a semiconductor body with a connecting line and a computer program product for carrying out this method
US20110113397A1 (en) * 2009-11-11 2011-05-12 Green Solution Technology Co., Ltd. Layout structure of mosfet and layout method thereof
US8138557B2 (en) * 2009-11-11 2012-03-20 Green Solution Technology Co., Ltd. Layout structure of MOSFET and layout method thereof
US8624335B2 (en) * 2011-04-30 2014-01-07 Peregrine Semiconductor Corporation Electronic module metalization system, apparatus, and methods of forming same
US20130033301A1 (en) * 2011-08-05 2013-02-07 Himax Technologies Limited Structure of output stage
US8847407B2 (en) * 2011-08-05 2014-09-30 Himax Technologies Limited Structure of output stage
US20140117453A1 (en) * 2012-10-31 2014-05-01 International Business Machines Corporation Local interconnects for field effect transistor devices
US9000489B2 (en) * 2012-10-31 2015-04-07 International Business Machines Corporation Local interconnects for field effect transistor devices

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