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US9379026B2 - Fin-shaped field-effect transistor process - Google Patents

Fin-shaped field-effect transistor process Download PDF

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US9379026B2
US9379026B2 US14/847,015 US201514847015A US9379026B2 US 9379026 B2 US9379026 B2 US 9379026B2 US 201514847015 A US201514847015 A US 201514847015A US 9379026 B2 US9379026 B2 US 9379026B2
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fin
effect transistor
shaped field
layer
work function
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US20150380319A1 (en
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Chien-Ting Lin
Wen-Tai Chiang
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United Microelectronics Corp
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    • H01L21/823842—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H01L21/823431—
    • H01L21/82345—
    • H01L21/823821—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H10D84/014—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0193—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H01L29/517—
    • H01L29/66545—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 

Definitions

  • the present invention relates generally to a fin-shaped field-effect transistor (FinFET) and a fabricating process thereof, and more specifically to a fin-shaped field-effect transistor (FinFET) and a fabricating process thereof, that changes some chemical or physical properties of metal layers of the field-effect transistor by performing a treatment process.
  • FinFET fin-shaped field-effect transistor
  • Poly-silicon is conventionally used as a gate electrode in semiconductor devices, such as the metal-oxide-semiconductor (MOS).
  • MOS metal-oxide-semiconductor
  • the conventional poly-silicon gates face problems such as lower performances due to boron penetration and unavoidable depletion effect, which increases the equivalent thickness of the gate dielectric layer, reduces the gate capacitance, and worsens the driving force of the devices. Therefore, work function metals that are suitable to serve as high-K gate dielectric layers are used to replace the conventional poly-silicon gate to be the control electrode.
  • the size and properties requirements for the semiconductor components become more demanding as the semiconductor component dimensions shrink. Because of limitations in processes, material properties and sizes, it is difficult to improve the electrical properties of the semiconductor component, such as the threshold voltage of a metal gate of the semiconductor component, to achieve the purposes of the semiconductor component.
  • the present invention provides a fin-shaped field-effect transistor (FinFET) and a process thereof, which performs a treatment process to change physical properties and chemical properties of at least a metal layer of the transistor to improve the electrical performances, such as the threshold voltage of the transistor.
  • FinFET fin-shaped field-effect transistor
  • the present invention provides a fin-shaped field-effect transistor (FinFET) process including the following steps.
  • a substrate is provided.
  • a first fin-shaped field-effect transistor and a second fin-shaped field-effect transistor are formed on the substrate, wherein the first fin-shaped field-effect transistor includes a first metal layer and the second fin-shaped field-effect transistor includes a second metal layer.
  • a treatment process is performed on the first metal layer to adjust the threshold voltage of the first fin-shaped field-effect transistor.
  • the present invention provides a field-effect transistor including a first fin-shaped field-effect transistor and a second fin-shaped field-effect transistor with the same conductivity type located on a substrate.
  • the first fin-shaped field-effect transistor comprises a first metal layer and the second fin-shaped field-effect transistor comprises a second metal layer.
  • the first metal layer and the second metal layer are of the same materials but different thicknesses.
  • the present invention provides a field-effect transistor including a first fin-shaped field-effect transistor and a second fin-shaped field-effect transistor having the same conductivity type located on a substrate.
  • the first fin-shaped field-effect transistor comprises a first metal layer
  • the second fin-shaped field-effect transistor comprises a second metal layer.
  • the first metal layer and the second metal layer are of different materials.
  • the present invention provides a fin-shaped field-effect transistor and a process thereof, which performs a treatment process on at least one of two or more than two fin-shaped field-effect transistors, in order to change some of the physical or chemical properties of at least a metal layer in each fin-shaped field-effect transistor.
  • electrical properties, such as the threshold voltage, of at least one of the fin-shaped field-effect transistors can be improved.
  • FIGS. 1-2 schematically depict three dimensional diagrams of a fin-shaped field-effect transistor process according to one embodiment of the present invention.
  • FIGS. 3-10 schematically depict cross-sectional views of a fin-shaped field-effect transistor process alone AA′ sectional line and BB′ sectional line of FIG. 2 .
  • FIGS. 1-2 schematically depict three dimensional diagrams of a fin-shaped field-effect transistor process according to one embodiment of the present invention.
  • a substrate 110 is provided.
  • a first fin-shaped field-effect transistor 120 ′ and a second fin-shaped field-effect transistor 130 ′ are formed on the substrate 110 .
  • the method of forming the first fin-shaped field-effect transistor 120 ′ and the second fin-shaped field-effect transistor 130 ′ includes the following steps.
  • a bulk substrate (not shown) is provided.
  • a hard mask (not shown) is formed thereon.
  • the hard mask (not shown) is patterned to define the locations of the first fin-shaped structure 124 for forming the first fin-shaped field-effect transistor 120 ′ and the second fin-shaped structure 134 for forming the second fin-shaped field-effect transistor 130 ′ in the substrate 110 .
  • An etching process is performed on the bulk substrate (not shown) so that the first fin-shaped structure 124 and the second fin-shaped structure 134 are formed.
  • the fabrication of the first fin-shaped structure 124 and the second fin-shaped structure 134 on the substrate 110 is then finished.
  • An isolation structure 112 is formed on the substrate 110 between the first fin-shaped structure 124 and the second fin-shaped structure 134 .
  • the isolation structure 112 may be a shallow trench isolation structure, but it is not limited thereto.
  • the hard mask (not shown) is removed after the first fin-shaped structure 124 and the second fin-shaped structure 134 are formed, and a tri-gate MOSFET can be formed in the following processes. There are three contact faces between the first fin-shaped structure 124 and a later formed dielectric layer, and between the second fin-shaped structure 134 and the later formed dielectric layer, used as a carrier channel whose width is wider than a channel width of a conventional planar MOSFET.
  • the tri-gate MOSFET When a driving voltage is applied, the tri-gate MOSFET produces an on-current twice higher compared to the conventional planar MOSFET.
  • the hard mask layer (not shown) is reserved to form another kind of multi-gate MOSFET. Due to the hard mask layer (not shown) being reserved, there are only two contact faces between the first fin-shaped structure 124 and a later formed dielectric layer, and between the second fin-shaped structure 134 and the later formed dielectric layer.
  • the present invention can also be applied to other semiconductor substrates.
  • a silicon-on-insulator substrate (not shown) is provided, and then a single crystalline silicon layer being a top part of the silicon-on-insulator substrate (not shown) is etched until an oxide layer being a middle part of the silicon-on-insulator substrate (not shown) is exposed, meaning that the fin-shaped structure formed on the silicon-on-insulator substrate (not shown) is finished.
  • first fin-shaped structure 124 and the second fin-shaped structure 134 are depicted in this embodiment, but the present invention can also be applied to a plurality of fin-shaped structures in the first fin-shaped field-effect transistor 120 ′ and the second fin-shaped field-effect transistor 130 ′.
  • a dielectric layer (not shown), an electrode layer (not shown) and a cap layer (not shown) are formed across the first fin-shaped structure 124 and the second fin-shaped structure 134 and then three of them are patterned to form a dielectric layer 142 , an electrode layer 144 and a cap layer 146 .
  • a spacer 148 is formed beside the dielectric layer 142 , the electrode layer 144 and the cap layer 146 .
  • the dielectric layer 142 may be an oxide layer; the electrode layer 144 may be a polysilicon layer; the cap layer 146 may be a nitride layer, but they are not limited thereto.
  • a source/drain region 149 may be respectively formed on the first fin-shaped structure 124 and the second fin-shaped structure 134 beside the spacer 148 by methods such as an inclination ion implantation process.
  • the fabrication of the first fin-shaped field-effect transistor 120 ′ and the second fin-shaped field-effect transistor 130 ′ is finished.
  • the first fin-shaped field-effect transistor 120 ′ and the second fin-shaped field-effect transistor 130 ′ have polysilicon electrode gates but they will be replaced by metal gates in subsequent processes.
  • the present invention can also be applied to a gate-first process, and the electrode layer 144 is therefore formed with suitable metal material layer/layers in combination with a polysilicon layer.
  • an interdielectric layer (not shown) is formed and covers the substrate 110 , the first fin-shaped structure 124 , the second fin-shaped structure 134 , the spacer 148 and the cap layer 146 . Then, the interdielectric layer (not shown) is planarized to form an interdielectric layer 150 .
  • the planarization process may include a chemical mechanical polishing (CMP) process or an etching process, but not limited to. AS the planarization process is performed, the cap layer 146 is also removed to expose the electrode layer 144 . Then, the electrode layer 144 is removed and a recess R is thereby formed.
  • CMP chemical mechanical polishing
  • FIGS. 3-10 schematically depict cross-sectional views of the first fin-shaped field-effect transistor 120 and the second fin-shaped field-effect transistor 130 along an AA′ section line and a BB′ section line of FIG. 2 .
  • the spacer 148 and the interdielectric layer 150 are respectively formed across the first fin-shaped structure 124 and the second fin-shaped structure 134 .
  • the source/drain region 149 is formed in the first fin-shaped structure 124 and the second fin-shaped structure 134 beside the spacer 148 .
  • the spacer 148 surrounds a recess R, which exposes parts of the first fin-shaped structure 124 and the second fin-shaped structure 134 . More precisely, along the AA′ section line of FIG. 2 is shown the first fin-shaped field-effect transistor 120 will be formed on the first fin-shaped structure 124 , and an area C corresponds to the area desired to form the first fin-shaped field-effect transistor 120 on; along BB′ section line of FIG. 2 is shown the second fin-shaped field-effect transistor 130 will be formed on the second fin-shaped structure 134 , and an area D corresponds to the area desired to form the first fin-shaped field-effect transistor 130 on.
  • a buffer layer 162 and a dielectric layer 164 are sequentially formed on the first fin-shaped structure 124 and the second fin-shaped structure 134 .
  • the buffer layer 162 may be an oxide layer
  • the dielectric layer 164 may be a dielectric layer having a high dielectric constant, such as the group selected from hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO 4 ), strontium bismuth tantalite (SrBi 2 Ta 2 O 9
  • a bottom barrier layer 172 is formed on the dielectric layer 164 , wherein the bottom barrier layer 172 may be a titanium nitride layer, but it is not limited thereto.
  • a treatment process P 1 may be selectively performed on the bottom barrier layer 172 in the area D, in order to change some chemical or physical properties of the bottom barrier layer 172 in the area D, thereby changing the work function value of the gate electrodes of transistors formed in the area D, and therefore changing the threshold voltage of transistors formed in the area D.
  • a treatment process P 1 may be selectively performed on the bottom barrier layer 172 in the area C, in order to change the threshold voltage of transistors formed in the area C; or, different treatment processes may be performed respectively on the bottom barrier layer 172 in the areas C and D to change the threshold voltage of transistors formed in the areas C and D.
  • the treatment process P 1 is just depicted in the area D. That means that the treatment process P 1 just affects the bottom barrier layer 172 in the area D.
  • a patterned mask (not shown) may cover the area C and expose the area D and the treatment process P 1 is performed in the areas C and D, having only the bottom barrier layer 172 in the area D affected by the treatment process P 1 .
  • the treatment process P 1 may also only affect the bottom barrier layer 172 in the area C.
  • an etching stop layer may be selectively formed on the bottom barrier layer 172 , wherein the etching stop layer (not shown) may be a tantalum nitride layer, but it is not limited thereto.
  • the treatment process P 1 comprises an etching process, a doping process, an oxidation process, a nitridation process or a fluoride process, but it is not limited thereto.
  • the treatment process P 1 is used to change physical and/or chemical properties of the bottom barrier layer 172 , wherein the physical properties may include the thickness, the hardness, the density or the reflectivity of the bottom barrier layer 172 , and the chemical properties may include the bonding, the reaction activity or the etching rate of the bottom barrier layer 172 .
  • the physical properties or the chemical properties of the bottom barrier layer 172 can be changed by performing at least a treatment process; the electrical properties, such as the threshold voltage of transistors, can thereby be adjusted.
  • the treatment process P 1 may be performed after the bottom barrier layer 172 is formed, after the etching stop layer (not shown) is formed, or after both of them are formed.
  • the treatment process of the present invention may be performed after metal layers are formed in subsequent processes.
  • a first work function layer 174 is formed on the bottom barrier layer 172 , wherein the first work function layer 174 may include a titanium nitride layer or an aluminum titanium layer etc, depending upon electrical types.
  • a treatment process P 2 may be selectively performed on the first work function layer 174 in the area D to change the work function value of gate electrodes of transistors formed in the area D, and therefore change the threshold voltage of transistors formed in the area D.
  • the treatment process P 2 is just depicted in the area D. That means the treatment process P 2 just affects the first work function layer 174 in the area D.
  • a patterned mask (not shown) may cover the area C and expose the area D and the treatment process P 2 is performed in the areas C and D, thereby only the first work function layer 174 in the area D will be affected by performing the treatment process P 2 .
  • the treatment process P 2 may also only affect the first work function layer 174 in the area C.
  • the treatment process P 2 comprises an etching process, a doping process, an oxidation process, a nitridation process or a fluoride process, but it is not limited thereto.
  • the treatment process P 2 is used to change physical and/or chemical properties of the first work function layer 174 , wherein the physical properties may include the thickness, the hardness, the density or the reflectivity of the first work function layer 174 and the chemical properties may include the bonding, the reaction activity or the etching rate of the first work function layer 174 .
  • the physical properties or the chemical properties of the first work function layer 174 can be changed by performing at least a treatment process, the electrical performances, such as the threshold voltage of transistors, can thereby be adjusted.
  • metal layers such as the work function layers of the first fin-shaped field-effect transistor and the second fin-shaped field-effect transistor may have different materials or may have stacked layer structures, as depicted in FIGS. 7-8 .
  • a mask layer P is formed and covers the area D to remove the first work function layer 174 in the area C.
  • a second work function layer 176 is formed on the bottom barrier layer 172 in the area C.
  • the second work function layer 176 includes a titanium nitride layer or an aluminum titanium layer, depending upon electrical types.
  • a treatment process P 3 may be selectively performed on the second work function layer 176 . Due to the mask P covering the area D, the treatment process P 3 just affects the second work function layer 176 .
  • the treatment process P 3 is similar to the treatment process P 1 and P 2 , and is therefore not described again.
  • a second work function layer 176 may be formed on the bottom barrier layer 172 in the area C and on the first work function layer 174 in the area D at the same time.
  • a treatment process P 3 may be selectively performed on the second work function layer 176 in the area C and/or the area D to change the work function value of transistors formed in the area C and/or the area D, and therefore change the threshold voltage of transistors formed in the area C and/or the area D.
  • the treatment process P 3 is similar to the treatment process P 1 and P 2 , and is therefore not described again.
  • a top barrier layer 178 is formed on the second work function layer 176 in the area C and on the first work function layer 174 in the area D at the same time.
  • the top barrier layer 178 may be a titanium nitride layer.
  • a low resistivity material 180 is formed on the top barrier layer 178 .
  • the low resistivity material 180 may be composed of materials such as aluminum or copper, etc.
  • the first fin-shaped field-effect transistor 120 may include a first metal layer, which includes a stacked metal layer such as a barrier layer (a bottom barrier layer 172 and a top barrier layer 178 for example), a first work function layer 174 and a low resistivity material 180 , etc;
  • the second fin-shaped field-effect transistor 130 may include a second metal layer, which includes a stacked metal layer such as a barrier layer (a bottom barrier layer 172 and a top barrier layer 178 for example), a second work function layer 176 and a low resistivity material 180 , etc.
  • At least a treatment process is performed in the present invention to change physical or/and chemical properties of at least one of the first metal layers or at least one of the second metal layers.
  • the electrical properties of the first fin-shaped field-effect transistor 120 or the second fin-shaped field-effect transistor 130 can be adjusted.
  • the threshold voltage of the first fin-shaped field-effect transistor 120 or the second fin-shaped field-effect transistor 130 can be adjusted.
  • the treatment process comprises an etching process, a doping process, an oxidation process, a nitridation process or a fluoride process, but it is not limited thereto. After the treatment process is performed, the properties of the transistors, such as work function values, volumes, gate leakages, effective current density, etc, can be improved.
  • the first fin-shaped field-effect transistor 120 and the second fin-shaped field-effect transistor 130 all have the same conductivity type in the present invention.
  • the first fin-shaped field-effect transistor 120 and the second fin-shaped field-effect transistor 130 may all be N-type transistors or P-type transistors.
  • the electrical properties, such as the threshold voltage of the fin-shaped field-effect transistors, having the same conductivity type can be changed by performing the treatment process of the present invention, so that the properties of the transistors having the same conductivity type can be adjusted similarly by applying the present invention to reach the requirements of each component.
  • a field-effect transistor can be formed by applying the present invention.
  • the field-effect transistor includes a first fin-shaped field-effect transistor 120 and a second fin-shaped field-effect transistor 130 having the same conductivity type located on a substrate 110 .
  • transistors 120 and 130 are both NMOS.
  • transistors 120 and 130 are both PMOS.
  • the first fin-shaped field-effect transistor 120 may include a first metal layer, which may include at least a barrier layer (a bottom barrier layer 172 and a top barrier layer 178 for example), a first work function layer 174 and a low resistivity material 180 ;
  • the second fin-shaped field-effect transistor 130 may include a second metal layer, which may include at least a barrier layer (a bottom barrier layer 172 and a top barrier layer 178 for example), a second work function layer 176 and a low resistivity material 180 .
  • a treatment process is performed on at least one of the first metal layer and the second metal layer to change the thickness, so the first metal layer and the second metal layer are of the same material but of different thickness.
  • a material changing process may be performed on at least one of the first metal layer and the second metal layer to change chemical properties of it, the first metal layer and the second metal layer thereby having different materials.
  • the present invention may also be applied to fin-shaped field-effect transistors having different conductivity types.
  • the first fin-shaped field-effect transistor 120 may be a P-type transistor and the second fin-shaped field-effect transistor 130 may be an N-type transistor.
  • the first work function layer 174 of the first fin-shaped field-effect transistor 120 may be a titanium nitride layer and the second work function layer 176 of the second fin-shaped field-effect transistor 130 may be an aluminum titanium layer, for pairing with the first fin-shaped field-effect transistor 120 and the second fin-shaped field-effect transistor 130 with different conductivity types, but it is not limited thereto.
  • the present invention provides a fin-shaped field-effect transistor and a process thereof, which performs a treatment process on at least one of two or more than two fin-shaped field-effect transistors, to change physical or chemical properties of at least a metal layer in fin-shaped field-effect transistors.
  • the electrical properties, such as the threshold voltage, of at least one of the fin-shaped field-effect transistors can be improved.
  • the treatment process may include an etching process, a doping process, an oxidation process, a nitridation process or a fluoride process, but it is not limited thereto.
  • the treatment process is used to change physical properties of metal layers, such as the thickness, the hardness, the density or the reflectivity and to change the chemical properties of metal layers such as the bonding, the reaction activity or the etching rate.

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A fin-shaped field-effect transistor process includes the following steps. A substrate is provided. A first fin-shaped field-effect transistor and a second fin-shaped field-effect transistor are formed on the substrate, wherein the first fin-shaped field-effect transistor includes a first metal layer and the second fin-shaped field-effect transistor includes a second metal layer. A treatment process is performed on the first fin-shaped field-effect transistor to adjust the threshold voltage of the first fin-shaped field-effect transistor. A fin-shaped field-effect transistor formed by said process is also provided.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
This application is a divisional application of and claims the benefit of U.S. patent application Ser. No. 13/418,367, filed Mar. 13, 2012.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a fin-shaped field-effect transistor (FinFET) and a fabricating process thereof, and more specifically to a fin-shaped field-effect transistor (FinFET) and a fabricating process thereof, that changes some chemical or physical properties of metal layers of the field-effect transistor by performing a treatment process.
2. Description of the Prior Art
Poly-silicon is conventionally used as a gate electrode in semiconductor devices, such as the metal-oxide-semiconductor (MOS). However, with the trend towards scaling down the size of semiconductor devices, the conventional poly-silicon gates face problems such as lower performances due to boron penetration and unavoidable depletion effect, which increases the equivalent thickness of the gate dielectric layer, reduces the gate capacitance, and worsens the driving force of the devices. Therefore, work function metals that are suitable to serve as high-K gate dielectric layers are used to replace the conventional poly-silicon gate to be the control electrode.
The size and properties requirements for the semiconductor components become more demanding as the semiconductor component dimensions shrink. Because of limitations in processes, material properties and sizes, it is difficult to improve the electrical properties of the semiconductor component, such as the threshold voltage of a metal gate of the semiconductor component, to achieve the purposes of the semiconductor component.
SUMMARY OF THE INVENTION
The present invention provides a fin-shaped field-effect transistor (FinFET) and a process thereof, which performs a treatment process to change physical properties and chemical properties of at least a metal layer of the transistor to improve the electrical performances, such as the threshold voltage of the transistor.
The present invention provides a fin-shaped field-effect transistor (FinFET) process including the following steps. A substrate is provided. A first fin-shaped field-effect transistor and a second fin-shaped field-effect transistor are formed on the substrate, wherein the first fin-shaped field-effect transistor includes a first metal layer and the second fin-shaped field-effect transistor includes a second metal layer. A treatment process is performed on the first metal layer to adjust the threshold voltage of the first fin-shaped field-effect transistor.
The present invention provides a field-effect transistor including a first fin-shaped field-effect transistor and a second fin-shaped field-effect transistor with the same conductivity type located on a substrate. The first fin-shaped field-effect transistor comprises a first metal layer and the second fin-shaped field-effect transistor comprises a second metal layer. The first metal layer and the second metal layer are of the same materials but different thicknesses.
The present invention provides a field-effect transistor including a first fin-shaped field-effect transistor and a second fin-shaped field-effect transistor having the same conductivity type located on a substrate. The first fin-shaped field-effect transistor comprises a first metal layer, and the second fin-shaped field-effect transistor comprises a second metal layer. The first metal layer and the second metal layer are of different materials.
According to the above, the present invention provides a fin-shaped field-effect transistor and a process thereof, which performs a treatment process on at least one of two or more than two fin-shaped field-effect transistors, in order to change some of the physical or chemical properties of at least a metal layer in each fin-shaped field-effect transistor. Thus, electrical properties, such as the threshold voltage, of at least one of the fin-shaped field-effect transistors can be improved.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1-2 schematically depict three dimensional diagrams of a fin-shaped field-effect transistor process according to one embodiment of the present invention.
FIGS. 3-10 schematically depict cross-sectional views of a fin-shaped field-effect transistor process alone AA′ sectional line and BB′ sectional line of FIG. 2.
 DETAILED DESCRIPTION
FIGS. 1-2 schematically depict three dimensional diagrams of a fin-shaped field-effect transistor process according to one embodiment of the present invention. As shown in FIG. 1, a substrate 110 is provided. A first fin-shaped field-effect transistor 120′ and a second fin-shaped field-effect transistor 130′ are formed on the substrate 110. More precisely, the method of forming the first fin-shaped field-effect transistor 120′ and the second fin-shaped field-effect transistor 130′ includes the following steps. A bulk substrate (not shown) is provided. A hard mask (not shown) is formed thereon. The hard mask (not shown) is patterned to define the locations of the first fin-shaped structure 124 for forming the first fin-shaped field-effect transistor 120′ and the second fin-shaped structure 134 for forming the second fin-shaped field-effect transistor 130′ in the substrate 110. An etching process is performed on the bulk substrate (not shown) so that the first fin-shaped structure 124 and the second fin-shaped structure 134 are formed. The fabrication of the first fin-shaped structure 124 and the second fin-shaped structure 134 on the substrate 110 is then finished.
An isolation structure 112 is formed on the substrate 110 between the first fin-shaped structure 124 and the second fin-shaped structure 134. The isolation structure 112 may be a shallow trench isolation structure, but it is not limited thereto. In one embodiment, the hard mask (not shown) is removed after the first fin-shaped structure 124 and the second fin-shaped structure 134 are formed, and a tri-gate MOSFET can be formed in the following processes. There are three contact faces between the first fin-shaped structure 124 and a later formed dielectric layer, and between the second fin-shaped structure 134 and the later formed dielectric layer, used as a carrier channel whose width is wider than a channel width of a conventional planar MOSFET. When a driving voltage is applied, the tri-gate MOSFET produces an on-current twice higher compared to the conventional planar MOSFET. In another embodiment, the hard mask layer (not shown) is reserved to form another kind of multi-gate MOSFET. Due to the hard mask layer (not shown) being reserved, there are only two contact faces between the first fin-shaped structure 124 and a later formed dielectric layer, and between the second fin-shaped structure 134 and the later formed dielectric layer.
The present invention can also be applied to other semiconductor substrates. For example, a silicon-on-insulator substrate (not shown) is provided, and then a single crystalline silicon layer being a top part of the silicon-on-insulator substrate (not shown) is etched until an oxide layer being a middle part of the silicon-on-insulator substrate (not shown) is exposed, meaning that the fin-shaped structure formed on the silicon-on-insulator substrate (not shown) is finished.
For clarifying the present invention, only the first fin-shaped structure 124 and the second fin-shaped structure 134 are depicted in this embodiment, but the present invention can also be applied to a plurality of fin-shaped structures in the first fin-shaped field-effect transistor 120′ and the second fin-shaped field-effect transistor 130′.
After the first fin-shaped structure 124 and the second fin-shaped structure 134 are formed, a dielectric layer (not shown), an electrode layer (not shown) and a cap layer (not shown) are formed across the first fin-shaped structure 124 and the second fin-shaped structure 134 and then three of them are patterned to form a dielectric layer 142, an electrode layer 144 and a cap layer 146. A spacer 148 is formed beside the dielectric layer 142, the electrode layer 144 and the cap layer 146. The dielectric layer 142 may be an oxide layer; the electrode layer 144 may be a polysilicon layer; the cap layer 146 may be a nitride layer, but they are not limited thereto. A source/drain region 149 may be respectively formed on the first fin-shaped structure 124 and the second fin-shaped structure 134 beside the spacer 148 by methods such as an inclination ion implantation process. Thus, the fabrication of the first fin-shaped field-effect transistor 120′ and the second fin-shaped field-effect transistor 130′ is finished. At this time, the first fin-shaped field-effect transistor 120′ and the second fin-shaped field-effect transistor 130′ have polysilicon electrode gates but they will be replaced by metal gates in subsequent processes. In another way, the present invention can also be applied to a gate-first process, and the electrode layer 144 is therefore formed with suitable metal material layer/layers in combination with a polysilicon layer.
As shown in FIG. 2, an interdielectric layer (not shown) is formed and covers the substrate 110, the first fin-shaped structure 124, the second fin-shaped structure 134, the spacer 148 and the cap layer 146. Then, the interdielectric layer (not shown) is planarized to form an interdielectric layer 150. The planarization process may include a chemical mechanical polishing (CMP) process or an etching process, but not limited to. AS the planarization process is performed, the cap layer 146 is also removed to expose the electrode layer 144. Then, the electrode layer 144 is removed and a recess R is thereby formed. In following processes, metal materials will be filled into the recess R on the first fin-shaped structure 124 and the second fin-shaped structure 134 to form a first fin-shaped field-effect transistor 120 and a second fin-shaped field-effect transistor 130 respectively. The first fin-shaped field-effect transistor 120 and the second fin-shaped field-effect transistor 130 may include common or different metal layers. For clarifying the structures of the first fin-shaped field-effect transistor 120 and the second fin-shaped field-effect transistor 130, FIGS. 3-10 schematically depict cross-sectional views of the first fin-shaped field-effect transistor 120 and the second fin-shaped field-effect transistor 130 along an AA′ section line and a BB′ section line of FIG. 2.
As shown in FIG. 3, the spacer 148 and the interdielectric layer 150 are respectively formed across the first fin-shaped structure 124 and the second fin-shaped structure 134. The source/drain region 149 is formed in the first fin-shaped structure 124 and the second fin-shaped structure 134 beside the spacer 148. The spacer 148 surrounds a recess R, which exposes parts of the first fin-shaped structure 124 and the second fin-shaped structure 134. More precisely, along the AA′ section line of FIG. 2 is shown the first fin-shaped field-effect transistor 120 will be formed on the first fin-shaped structure 124, and an area C corresponds to the area desired to form the first fin-shaped field-effect transistor 120 on; along BB′ section line of FIG. 2 is shown the second fin-shaped field-effect transistor 130 will be formed on the second fin-shaped structure 134, and an area D corresponds to the area desired to form the first fin-shaped field-effect transistor 130 on.
As shown in FIG. 4, a buffer layer 162 and a dielectric layer 164 are sequentially formed on the first fin-shaped structure 124 and the second fin-shaped structure 134. The buffer layer 162 may be an oxide layer, and the dielectric layer 164 may be a dielectric layer having a high dielectric constant, such as the group selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalite (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT) and barium strontium titanate (BaxSr1-xTiO3, BST).
As shown in FIG. 5, a bottom barrier layer 172 is formed on the dielectric layer 164, wherein the bottom barrier layer 172 may be a titanium nitride layer, but it is not limited thereto. In this embodiment, a treatment process P1 may be selectively performed on the bottom barrier layer 172 in the area D, in order to change some chemical or physical properties of the bottom barrier layer 172 in the area D, thereby changing the work function value of the gate electrodes of transistors formed in the area D, and therefore changing the threshold voltage of transistors formed in the area D. In another embodiment, a treatment process P1 may be selectively performed on the bottom barrier layer 172 in the area C, in order to change the threshold voltage of transistors formed in the area C; or, different treatment processes may be performed respectively on the bottom barrier layer 172 in the areas C and D to change the threshold voltage of transistors formed in the areas C and D. As shown in FIG. 5, the treatment process P1 is just depicted in the area D. That means that the treatment process P1 just affects the bottom barrier layer 172 in the area D. In actual practice, a patterned mask (not shown) may cover the area C and expose the area D and the treatment process P1 is performed in the areas C and D, having only the bottom barrier layer 172 in the area D affected by the treatment process P1. Reciprocally, the treatment process P1 may also only affect the bottom barrier layer 172 in the area C.
After the bottom barrier layer 172 is formed on the dielectric layer 164, an etching stop layer (not shown) may be selectively formed on the bottom barrier layer 172, wherein the etching stop layer (not shown) may be a tantalum nitride layer, but it is not limited thereto.
The treatment process P1 comprises an etching process, a doping process, an oxidation process, a nitridation process or a fluoride process, but it is not limited thereto. The treatment process P1 is used to change physical and/or chemical properties of the bottom barrier layer 172, wherein the physical properties may include the thickness, the hardness, the density or the reflectivity of the bottom barrier layer 172, and the chemical properties may include the bonding, the reaction activity or the etching rate of the bottom barrier layer 172. In this way, the physical properties or the chemical properties of the bottom barrier layer 172 can be changed by performing at least a treatment process; the electrical properties, such as the threshold voltage of transistors, can thereby be adjusted. In another way, the treatment process P1 may be performed after the bottom barrier layer 172 is formed, after the etching stop layer (not shown) is formed, or after both of them are formed. In addition, the treatment process of the present invention may be performed after metal layers are formed in subsequent processes.
As shown in FIG. 6, a first work function layer 174 is formed on the bottom barrier layer 172, wherein the first work function layer 174 may include a titanium nitride layer or an aluminum titanium layer etc, depending upon electrical types. A treatment process P2 may be selectively performed on the first work function layer 174 in the area D to change the work function value of gate electrodes of transistors formed in the area D, and therefore change the threshold voltage of transistors formed in the area D. Likewise, as shown in FIG. 6, the treatment process P2 is just depicted in the area D. That means the treatment process P2 just affects the first work function layer 174 in the area D. In actual practice, a patterned mask (not shown) may cover the area C and expose the area D and the treatment process P2 is performed in the areas C and D, thereby only the first work function layer 174 in the area D will be affected by performing the treatment process P2. Reciprocally, the treatment process P2 may also only affect the first work function layer 174 in the area C.
The treatment process P2 comprises an etching process, a doping process, an oxidation process, a nitridation process or a fluoride process, but it is not limited thereto. The treatment process P2 is used to change physical and/or chemical properties of the first work function layer 174, wherein the physical properties may include the thickness, the hardness, the density or the reflectivity of the first work function layer 174 and the chemical properties may include the bonding, the reaction activity or the etching rate of the first work function layer 174. In this way, the physical properties or the chemical properties of the first work function layer 174 can be changed by performing at least a treatment process, the electrical performances, such as the threshold voltage of transistors, can thereby be adjusted.
In addition, in another embodiment of the present invention, metal layers such as the work function layers of the first fin-shaped field-effect transistor and the second fin-shaped field-effect transistor may have different materials or may have stacked layer structures, as depicted in FIGS. 7-8. As shown in FIG. 7, a mask layer P is formed and covers the area D to remove the first work function layer 174 in the area C. As shown in FIG. 8, a second work function layer 176 is formed on the bottom barrier layer 172 in the area C. In this embodiment, the second work function layer 176 includes a titanium nitride layer or an aluminum titanium layer, depending upon electrical types. A treatment process P3 may be selectively performed on the second work function layer 176. Due to the mask P covering the area D, the treatment process P3 just affects the second work function layer 176. The treatment process P3 is similar to the treatment process P1 and P2, and is therefore not described again.
In another case, after the first work function layer 174 in the area C is removed as shown in FIG. 7, the mask P is removed. Then, a second work function layer 176 may be formed on the bottom barrier layer 172 in the area C and on the first work function layer 174 in the area D at the same time. Thereafter, a treatment process P3 may be selectively performed on the second work function layer 176 in the area C and/or the area D to change the work function value of transistors formed in the area C and/or the area D, and therefore change the threshold voltage of transistors formed in the area C and/or the area D. The treatment process P3 is similar to the treatment process P1 and P2, and is therefore not described again.
As shown in FIG. 9, a top barrier layer 178 is formed on the second work function layer 176 in the area C and on the first work function layer 174 in the area D at the same time. The top barrier layer 178 may be a titanium nitride layer. As shown in FIG. 10, a low resistivity material 180 is formed on the top barrier layer 178. The low resistivity material 180 may be composed of materials such as aluminum or copper, etc. After the top barrier layer 178 is formed or the low resistivity material 180 is formed, a treatment process (similar to the treatment processes P1, P2 and P3) may be selectively performed to change physical properties and/or chemical properties of the top barrier layer 178 or the low resistivity material 180. Then, metal layers are planarized until the interdielectric layer 150 is exposed, and then subsequent transistor processes may be performed.
To sum up, the first fin-shaped field-effect transistor 120 may include a first metal layer, which includes a stacked metal layer such as a barrier layer (a bottom barrier layer 172 and a top barrier layer 178 for example), a first work function layer 174 and a low resistivity material 180, etc; the second fin-shaped field-effect transistor 130 may include a second metal layer, which includes a stacked metal layer such as a barrier layer (a bottom barrier layer 172 and a top barrier layer 178 for example), a second work function layer 176 and a low resistivity material 180, etc. At least a treatment process is performed in the present invention to change physical or/and chemical properties of at least one of the first metal layers or at least one of the second metal layers. Therefore, the electrical properties of the first fin-shaped field-effect transistor 120 or the second fin-shaped field-effect transistor 130 can be adjusted. For instance, the threshold voltage of the first fin-shaped field-effect transistor 120 or the second fin-shaped field-effect transistor 130 can be adjusted. Specifically, the treatment process comprises an etching process, a doping process, an oxidation process, a nitridation process or a fluoride process, but it is not limited thereto. After the treatment process is performed, the properties of the transistors, such as work function values, volumes, gate leakages, effective current density, etc, can be improved.
It is worth noting that, the first fin-shaped field-effect transistor 120 and the second fin-shaped field-effect transistor 130 all have the same conductivity type in the present invention. Specifically, the first fin-shaped field-effect transistor 120 and the second fin-shaped field-effect transistor 130 may all be N-type transistors or P-type transistors. In other words, the electrical properties, such as the threshold voltage of the fin-shaped field-effect transistors, having the same conductivity type can be changed by performing the treatment process of the present invention, so that the properties of the transistors having the same conductivity type can be adjusted similarly by applying the present invention to reach the requirements of each component.
For example, as shown in FIG. 10, a field-effect transistor can be formed by applying the present invention. The field-effect transistor includes a first fin-shaped field-effect transistor 120 and a second fin-shaped field-effect transistor 130 having the same conductivity type located on a substrate 110. For example, transistors 120 and 130 are both NMOS. For example, transistors 120 and 130 are both PMOS. The first fin-shaped field-effect transistor 120 may include a first metal layer, which may include at least a barrier layer (a bottom barrier layer 172 and a top barrier layer 178 for example), a first work function layer 174 and a low resistivity material 180; the second fin-shaped field-effect transistor 130 may include a second metal layer, which may include at least a barrier layer (a bottom barrier layer 172 and a top barrier layer 178 for example), a second work function layer 176 and a low resistivity material 180.
In one case, a treatment process is performed on at least one of the first metal layer and the second metal layer to change the thickness, so the first metal layer and the second metal layer are of the same material but of different thickness. In another case, a material changing process may be performed on at least one of the first metal layer and the second metal layer to change chemical properties of it, the first metal layer and the second metal layer thereby having different materials.
In addition, the present invention may also be applied to fin-shaped field-effect transistors having different conductivity types. For instance, the first fin-shaped field-effect transistor 120 may be a P-type transistor and the second fin-shaped field-effect transistor 130 may be an N-type transistor. Thus, the first work function layer 174 of the first fin-shaped field-effect transistor 120 may be a titanium nitride layer and the second work function layer 176 of the second fin-shaped field-effect transistor 130 may be an aluminum titanium layer, for pairing with the first fin-shaped field-effect transistor 120 and the second fin-shaped field-effect transistor 130 with different conductivity types, but it is not limited thereto.
In summary, the present invention provides a fin-shaped field-effect transistor and a process thereof, which performs a treatment process on at least one of two or more than two fin-shaped field-effect transistors, to change physical or chemical properties of at least a metal layer in fin-shaped field-effect transistors. Thus, the electrical properties, such as the threshold voltage, of at least one of the fin-shaped field-effect transistors can be improved. Furthermore, the treatment process may include an etching process, a doping process, an oxidation process, a nitridation process or a fluoride process, but it is not limited thereto. The treatment process is used to change physical properties of metal layers, such as the thickness, the hardness, the density or the reflectivity and to change the chemical properties of metal layers such as the bonding, the reaction activity or the etching rate.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (10)

What is claimed is:
1. A fin-shaped field-effect transistor (FinFET) process, comprising:
providing a substrate;
forming a first fin-shaped field-effect transistor and a second fin-shaped field-effect transistor having a same conductivity type on the substrate, wherein the first fin-shaped field-effect transistor comprises a buffer layer, a dielectric layer, a bottom barrier layer and a first work function layer all having U-shaped cross-sectional profiles stacked on each other and the second fin-shaped field-effect transistor comprises a buffer layer, a dielectric layer, a bottom barrier layer and a second work function layer all having U-shaped cross-sectional profiles stacked on each other, wherein the first work function layer and the second work function layer are formed sequentially; and
performing a treatment process on the first work function layer to change the threshold voltage of the first fin-shaped field-effect transistor.
2. The fin-shaped field-effect transistor process according to claim 1, wherein the first fin-shaped field-effect transistor and the second fin-shaped field-effect transistor are N-type transistors or P-type transistors.
3. The fin-shaped field-effect transistor process according to claim 1, wherein the treatment process comprises an etching process, a doping process, an oxidation process, a nitridation process or a fluoride process.
4. The fin-shaped field-effect transistor process according to claim 1, wherein the treatment process is performed on the first work function layer to change physical properties of the first work function layer.
5. The fin-shaped field-effect transistor process according to claim 4, wherein the physical properties comprise the thickness, the hardness, the density or the reflectivity of the first work function layer.
6. The fin-shaped field-effect transistor process according to claim 1, wherein the treatment process is performed on the first work function layer to change chemical properties of the first work function layer.
7. The fin-shaped field-effect transistor process according to claim 6, wherein the chemical properties comprise the bonding, the reaction activity or the etching rate of the first work function layer.
8. The fin-shaped field-effect transistor process according to claim 1, wherein the first fin-shaped field-effect transistor and the second fin-shaped field-effect transistor further comprise a top barrier layer, a low resistivity material or a combination of the two.
9. The fin-shaped field-effect transistor process according to claim 8, wherein steps of forming the first fin-shaped field-effect transistor and the second fin-shaped field-effect transistor on the substrate comprise:
forming a first fin-shaped structure and a second fin-shaped structure on the substrate;
respectively forming the dielectric layer on the first fin-shaped structure and the second fin-shaped structure;
respectively forming the bottom barrier layer on each of the dielectric layers;
forming the first work function layer on the bottom barrier layer on the first fin-shaped structure;
forming the second work function layer on the bottom barrier layer on the second fin-shaped structure;
respectively forming the top barrier layer on the first work function layer and the second work function layer; and
respectively forming the low resistivity material on each of the top barrier layers.
10. The fin-shaped field-effect transistor process according to claim 9, wherein the treatment process is performed after the bottom barrier layer, the first work function layer, the second work function layer, the top barrier layer or the low resistivity material is formed.
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