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US9111851B2 - Enhancement mode gallium nitride based transistor device having a P type metal oxide layer comprising plurality of extension parts extending into the epitaxial stacked layer - Google Patents

Enhancement mode gallium nitride based transistor device having a P type metal oxide layer comprising plurality of extension parts extending into the epitaxial stacked layer Download PDF

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US9111851B2
US9111851B2 US13/686,935 US201213686935A US9111851B2 US 9111851 B2 US9111851 B2 US 9111851B2 US 201213686935 A US201213686935 A US 201213686935A US 9111851 B2 US9111851 B2 US 9111851B2
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metal oxide
type metal
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epitaxial stacked
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Wei-Hung Kuo
Suh-Fang Lin
Rong Xuan
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Industrial Technology Research Institute ITRI
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H01L29/2003—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28264—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
    • H01L29/42316—
    • H01L29/432—
    • H01L29/778—
    • H01L29/7786—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/602—Heterojunction gate electrodes for FETs
    • H01L29/1066—
    • H01L29/452—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/343—Gate regions of field-effect devices having PN junction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor

Definitions

  • the technical field relates to an enhancement mode gallium nitride-based (GaN-based) transistor device.
  • HEMT horizontal GaN-based high electron mobility transistor
  • 2DEG two-dimensional electron gas
  • the device cannot be normally off due to the 2DEG distribution of the gate region.
  • Vt threshold voltage
  • a p-type AlGaN layer is formed in the gate region by a selectivity area growth. Using the characteristic of the depletion region, the 2DEG distribution below the gate region is depleted so that the device can be normally off.
  • the turn-on current of such device is not much affected, but the threshold voltage of the same is generally lower because the threshold voltage (Vth) is limited by whether the p-type carrier concentration (about 1 ⁇ 10 17 /cm 2 ) of the p-type AlGaN layer can effectively deplete the 2DEG. Therefore, attention is drawn to an enhancement mode hetero-structure field effect transistor (HFET) device in which the threshold voltage is improved but the turn-on current is not much affected.
  • HFET hetero-structure field effect transistor
  • One of exemplary embodiments includes an enhancement mode GaN-based transistor device, which includes an epitaxial stacked layer having an undoped GaN layer disposed on a substrate; a source layer and a drain layer disposed on a surface of the epitaxial stacked layer; a p-type metal oxide layer disposed between the source layer and the drain layer; and a gate layer disposed on the p-type metal oxide layer.
  • the p-type metal oxide layer includes a body part disposed on the surface of the epitaxial stacked layer, and a plurality of extension parts connecting the body part and extending into the epitaxial stacked layer.
  • One of exemplary embodiments includes an enhancement mode GaN-based transistor device, which includes an epitaxial stacked layer disposed on a substrate, including an undoped GaN layer and having a recess on a surface of the epitaxial stacked layer; a source layer and a drain layer disposed on the surface of the epitaxial stacked layer beside the recess; a plurality of p-type metal oxide layers disposed on the recess between the source layer and the drain layer and having different p-type carrier concentrations from each other; and a gate layer disposed on the p-type metal oxide layer.
  • FIG. 1 is a schematic diagram illustrating a cross-sectional view of an enhancement mode GaN-based transistor device having a single-layer p-type metal oxide layer with extension parts according to a first embodiment.
  • FIG. 1A is a top view along the line I-I of FIG. 1 .
  • FIG. 1B is another top view along the line I-I of FIG. 1 .
  • FIG. 2 is a schematic diagram illustrating a cross-sectional view of an enhancement mode GaN-based transistor device having a multi-layer p-type metal oxide layer with extension parts according to a second embodiment.
  • FIG. 3 is a schematic diagram illustrating a cross-sectional view of a recessed enhancement mode GaN-based transistor device having a multi-layer p-type metal oxide layer according to a third embodiment.
  • FIG. 4 shows the current decay performance of the MOS-HEMT device structure of Example 1 in which the gate region has a nanoporous pattern.
  • FIG. 5 shows the current decay performance of the conventional MOS-HEMT.
  • FIG. 6 shows the gate leakage current of each of the transistor having a recessed gate of Example 2 and the conventional transistor having a recessed Schottky gate.
  • FIG. 7 shows the transfer I-V characteristic curve of each of the transistor having a recessed gate of Example 3 and the conventional transistor having a recessed Schottky gate.
  • FIG. 1 is a schematic diagram illustrating a cross-sectional view of an enhancement mode GaN-based transistor device having a single-layer p-type metal oxide layer with extension parts according to a first embodiment.
  • the enhancement mode GaN-based transistor device of the first embodiment includes an epitaxial stacked layer 11 , a source layer 20 , a drain layer 22 , a gate layer 28 and a p-type metal oxide layer 24 .
  • the source layer 20 , the drain layer 22 and the p-type metal oxide layer 24 are disposed on the surface 11 a of the epitaxial stacked layer 11 .
  • the gate layer 28 is disposed on the p-type metal oxide layer 24 .
  • the p-type metal oxide layer 24 is disposed between the source layer 20 and the drain layer 22 .
  • the p-type metal oxide layer 24 includes a body part 34 and a plurality of extension parts 44 .
  • the body part 34 is disposed on the surface 11 a of the epitaxial stacked layer 11 .
  • the extension parts 44 connect the body part 34 and extend into the epitaxial stacked layer 11 .
  • the enhancement mode GaN-based transistor device further includes a dielectric layer 18 on the surface 11 a of the epitaxial stacked layer 11 .
  • the epitaxial stacked layer 11 is disposed on a substrate 10 .
  • the substrate 10 can be a silicon substrate, SiC substrate or a sapphire substrate.
  • the epitaxial stacked layer 11 includes semiconductor, such as III-V compound semiconductor.
  • the epitaxial stacked layer 11 includes GaN.
  • the epitaxial stacked layer includes a buffer layer 12 , an undoped GaN layer (u-GaN layer) 14 and a barrier layer 16 sequentially stacked on the substrate 10 , but the present disclosure is not limited thereto.
  • the buffer layer 12 can include III-V compound semiconductor.
  • the buffer layer 12 can be a GaN-based buffer layer or an AlN-based buffer layer.
  • the forming method of the buffer layer 12 includes a metal-organic chemical vapour deposition (MOCVD) process or a molecular beam epitaxy (MBE) process.
  • MOCVD metal-organic chemical vapour deposition
  • MBE molecular beam epitaxy
  • the thickness of the buffer layer 12 ranges, for example, from about 1 ⁇ m to about 10 ⁇ m. In an embodiment, the thickness of the buffer layer 12 can be about 4.2 ⁇ m.
  • the u-GaN layer 14 and the barrier layer 16 form a GaN hetero-structure with a two-dimensional electron gas.
  • the forming method of the u-GaN layer 14 includes a MOCVD process or a MBE process, and the thickness of the same ranges, for example, from about 0.5 ⁇ m to about 5 ⁇ m. In an embodiment, the thickness of the u-GaN layer 14 can be about 1.6 ⁇ m.
  • the barrier layer 16 can be an undoped Al x Ga 1-x N layer (u-Al x Ga 1-x N layer), wherein 0.1 ⁇ x ⁇ 1.
  • the u-Al x Ga 1-x N layer has an aluminium content x of 20 to 30%.
  • the forming method of the u-Al x Ga 1-x N layer includes a MOCVD process or a MBE process, and the thickness of the same ranges, for example, from about 5 nm to about 40 nm. In an embodiment, the thickness of the barrier layer 16 can be about 20 nm.
  • the dielectric layer 18 is disposed on the epitaxial stacked layer 11 .
  • the dielectric layer 18 includes SiO 2 , Si 3 N 4 or Si 3 N 4 /SiO 2 and the forming method thereof includes a plasma-enhanced chemical vapour deposition (PECVD) process or a sputtering process.
  • PECVD plasma-enhanced chemical vapour deposition
  • the thickness of the dielectric layer 18 ranges, for example, from about 10 nm to about 500 nm.
  • the dielectric layer 18 defines the positions for the source layer 20 , the drain layer 22 and the p-type metal oxide layer 24 (or the gate layer 28 ) with one or more photolithography-and-etching patterning processes.
  • a plurality of mesh holes, trenches or columns can be formed in the area, in which the p-type metal oxide layer 24 is subsequently formed, of the epitaxial stacked layer 11 with various patterning processes, so that the extension parts of the p-type metal oxide layer 24 can be subsequently formed into the epitaxial stacked layer 11 .
  • the depth of the mesh holes or trenches or the length of the columns ranges, for example, from 5 nm to 50 nm, and extends to the barrier layer 16 or the u-GaN layer 14 .
  • the size of the mesh holes, trenches or columns can be from 50 nm to 500 nm.
  • a nano-imprint process is performed on the dielectric layer 18 to form nano-mesh holes, nano-columns or nano-strips. Thereafter, a patterned photoresist layer which defines a gate region is formed with a photolithography process. Afterwards, an etching step is performed, in which CHF 3 gas is used to etch the dielectric layer 18 , and a mixture gas including SF 6 and Cl 2 is then used until the etched depth reaches the barrier layer 16 or the u-GaN layer 14 .
  • a buffered oxide etch (BOE) solution is used to remove the residual dielectric layer 18 in the gate region, and a H 2 SO 4 /H 2 O 2 solution in a volume ratio of 2:1 is used to remove the residual photoresist layer outside of the gate region.
  • BOE buffered oxide etch
  • the depth thereof is about 15 nm.
  • the depth thereof is about 30 nm.
  • the source layer 20 and the drain layer 22 are disposed on the surface 11 a of the epitaxial stacked layer 11 and on the dielectric layer 18 .
  • the source layer 20 includes an Ohmic metal electrode 20 a and a metal electrode 20 b .
  • the drain layer 22 includes an Ohmic metal electrode 22 a and a metal electrode 22 b .
  • Each of the Ohmic metal electrodes includes Ti (100 nm)/Al (300 nm), Ti (100 nm)/Al (300 nm)/Ni (40 nm)/Au (300 nm) or Ti (100 nm)/Al (300 nm)/Pt (40 nm)/Au (300 nm), but the disclosure is not limited thereto.
  • Ti (100 nm)/Al (300 nm) indicates a stacked layer including a titanium layer of 100 nm thick and an aluminum layer of 300 nm thick.
  • the same rule can be applied to other cases.
  • the Ohmic metal electrodes 20 a and 22 a of the source and drain layers 20 and 22 can be fabricated with an electron beam (e-beam) evaporation process followed by an annealing treatment.
  • the annealing treatment can be a rapid thermal annealing (RTA) at 600° C. under nitrogen atmosphere for 1 minute.
  • the Ohmic metal electrodes 20 a and 22 a of the source and drain layers 20 and 22 can be fabricated, after the patterning of the dielectric layer 18 and before the formation of the p-type metal oxide layer 24 , on the surface 11 a of the epitaxial stacked layer 11 and on the dielectric layer 18 .
  • the Ohmic metal electrodes 20 a and 22 a of the source and drain layers 20 and 22 can be fabricated, after the patterning of the dielectric layer 18 and the formation of the p-type metal oxide layer 24 , on the surface 11 a of the epitaxial stacked layer 11 and on the dielectric layer 18 .
  • the forming method of the metal electrodes 20 b and 22 b of the source and drain layers 20 and 22 includes a photoresist lift off process and a selective evaporation process such as an e-beam evaporation.
  • Each of the metal electrodes 20 b and 22 b of the source and drain layers 20 and 22 includes a high work function metal or an alloy, such as Ni (20 nm)/Au (300 nm), Ti (20 nm)/Au (300 nm) or Pt (20 nm)/Au (300 nm).
  • the metal electrodes 20 b and 22 b of the source and drain layers 20 and 22 can be fabricated with an e-beam evaporation process followed by an annealing treatment.
  • the annealing treatment can be a rapid thermal annealing (RTA) or a furnace annealing at 500° C. under nitrogen atmosphere for 1 minute to 30 minutes.
  • RTA rapid thermal annealing
  • the metal electrodes 20 b and 22 b of the source and drain layers 20 and 22 can be formed on the Ohmic metal electrodes 20 a and 22 a of the source and drain layers 20 and 22 after the formation of the p-type metal oxide layer 24 .
  • the p-type metal oxide layer 24 is disposed between the source and drain layers 20 and 22 .
  • the extension parts 44 of the p-type metal oxide layer 24 at least extend into the barrier layer 16 .
  • the extension parts 44 of the p-type metal oxide layer 24 at least extend into the u-GaN layer 14 , as shown in FIG. 1 .
  • the epitaxial stacked layer 11 (or the barrier layer 16 ) has a plurality of mesh holes, and the extension parts 44 of the p-type metal oxide layer 24 are shaped as a plurality of columns respectively extending into the mesh holes, top view of which is shown in FIG. 1A .
  • the epitaxial stacked layer 11 (or the barrier layer 16 ) has a plurality of columns, and the extension parts 44 of the p-type metal oxide layer 24 extend into a space around the columns and are shaped as a mesh. Besides, the length of the p-type metal oxide layer 24 corresponds to the gate length.
  • the p-type metal oxide layer 24 has a p-type carrier concentration of 1 ⁇ 10 15 to 5 ⁇ 10 19 /cm 3 .
  • the p-type metal oxide layer 24 includes multiple NiO y layers, and — 1_ ⁇ y ⁇ 1.2.
  • the p-type metal oxide layer 24 can be made of a single material layer, as shown in FIG. 1 .
  • the forming method of the p-type metal oxide layer 24 includes an atomic layer deposition (ALD) process, a vapour deposition process, a sputtering process, a chemical vapour deposition (CVD) process, a spraying method, a sol-gel method or a pulse laser deposition (PLD) process.
  • the p-type metal oxide layer 24 can be formed after the formation of the dielectric layer 18 and before the formation of the gate layer 28 and the metal electrodes 20 b and 22 b of the source and drain layers 20 and 22 .
  • the gate layer 28 is disposed on the p-type metal oxide layer 24 .
  • the gate layer 28 can be a metal electrode.
  • the metal gate includes a high work function metal or an alloy, such as Ni (20 nm)/Au (300 nm), Ti (20 nm)/Au (300 nm) or Pt (20 nm)/Au (300 nm).
  • the length of the gate layer 28 is about 2 ⁇ m, for example.
  • the forming method of the gate layer 28 includes a photoresist lift off process and a selective evaporation process. The step of forming the gate layer 28 can be simultaneously performed during the step of forming the metal electrodes 20 b and 22 b of the source and drain layers 20 and 22 .
  • an Al 2 O 3 layer or another metal oxide layer can be used instead of the p-type metal oxide layer 24 of the said embodiments.
  • FIG. 2 is a schematic diagram illustrating a cross-sectional view of an enhancement mode GaN-based transistor device having a multi-layer p-type metal oxide layer with extension parts according to a second embodiment.
  • the enhancement mode GaN-based transistor device has a single-layer p-type metal oxide layer 24 with extension parts.
  • the present disclosure is not limited thereto.
  • the enhancement mode GaN-based transistor device has a multi-layer p-type metal oxide layer 26 with extension parts, as shown in FIG. 2 .
  • the p-type metal oxide layer 26 can include a plurality of p-type metal oxide layers 26 a - 26 c with different p-type carrier concentrations.
  • the p-type metal oxide layer 26 is made of multiple NiO y layers with different p-type carrier concentrations, in which one NiO y layer has a p-type carrier concentration of less than 1 ⁇ 10 15 /cm 3 , another NiO y layer has a p-type carrier concentration of 1 ⁇ 10 15 to 1 ⁇ 10 17 /cm 3 , yet another NiO y layer has a p-type carrier concentration of more than 1 ⁇ 10 17 /cm 3 , and each of the NiO y layers has a thickness of 1 nm to 200 nm.
  • the forming method of the multi-layer p-type metal oxide layer 26 includes an atomic layer deposition (ALD) process, a vapour deposition process, a sputtering process, a chemical vapour deposition (CVD) process, a spraying method, a sol-gel method or a pulse laser deposition (PLD) process.
  • ALD atomic layer deposition
  • vapour deposition a vapour deposition process
  • sputtering process a chemical vapour deposition (CVD) process
  • a spraying method a sol-gel method or a pulse laser deposition (PLD) process.
  • PLD pulse laser deposition
  • the above embodiments in which the enhancement mode GaN-based transistor device having a single-layer or multi-layer p-type metal oxide layer with extension parts is provided for illustration purposes and is not construed as limiting the present disclosure.
  • the third embodiment discloses a recessed enhancement mode GaN-based transistor device having a multi-layer p-type metal oxide layer.
  • FIG. 3 is a schematic diagram illustrating a cross-sectional view of a recessed enhancement mode GaN-based transistor device having a multi-layer p-type metal oxide layer according to a third embodiment.
  • the enhancement mode GaN-based transistor device of the third embodiment includes an epitaxial stacked layer 11 , a source layer 20 , a drain layer 22 , a gate layer 28 and a p-type metal oxide layer 26 .
  • the epitaxial stacked layer 11 has a recess 30 , which corresponds to the gate layer 28 , on the surface 11 a thereof.
  • the epitaxial stacked layer includes a buffer layer 12 , an undoped GaN layer (u-GaN layer) 14 and a barrier layer 16 sequentially stacked on the substrate 10 , but the present disclosure is not limited thereto.
  • the bottom of the recess 30 can expose the barrier layer 16 or the u-GaN layer 14 .
  • the source layer 20 and the drain layer 22 are disposed on the surface 11 a of the epitaxial stacked layer 11 .
  • the gate layer 28 is disposed on the p-type metal oxide layer 24 , corresponds to the recess 30 of the epitaxial stacked layer 11 , and located between the source and drain layers 20 and 22 .
  • the multi-layer p-type metal oxide layer 26 including p-type metal oxide layers 26 a - 26 c is disposed between the source and drain layers 20 and 22 and on the recess 30 of the epitaxial stacked layer 11 .
  • the multi-layer p-type metal oxide layer 26 is disposed on the recess 30 of the epitaxial stacked layer 11 and extends, along the sidewall of the opening 32 of the dielectric layer 18 , onto a portion of the surface of the dielectric layer 18 .
  • the material and forming method of the multi-layer p-type metal oxide layer 26 of the third embodiment are similar to those described in the second embodiment, and the materials and forming methods of other components or layers are similar to those described in the first embodiment, so that the details are not iterated herein.
  • the substrate 10 is a silicon substrate
  • the epitaxial stacked layer 11 includes a GaN-based buffer layer 12 of 4.2 ⁇ m thick, an u-GaN layer 14 of 1.6 ⁇ m thick and an u-AlGaN layer 16 of 1.6 ⁇ m thick, wherein the u-AlGaN layer 16 has an aluminum content of 25%.
  • the dielectric layer 18 is a SiO 2 layer of 300 nm thick formed through PECVD. An etching step is performed, in which CHF 3 gas is used to etch the dielectric layer 18 , and a mixture gas including SF 6 and Cl 2 is then used until the etched depth reaches the barrier layer 16 or the u-GaN layer 14 .
  • the Ohmic metal electrodes 20 a and 22 a of the source and drain layers 20 and 22 include Ti (100 nm)/Al (300 nm), and the forming method thereof include performing an e-beam evaporation process at 600° C. under nitrogen atmosphere for 1 minute.
  • the metal electrodes 20 b and 22 b of the source and drain layers 20 and 22 include Ni (20 nm)/Au (300 nm), and the forming method thereof include performing an e-beam evaporation process.
  • An epitaxial stacked layer 11 is grown on a substrate 10 .
  • a dielectric layer 18 is formed on the epitaxial stacked layer 11 .
  • an nano-imprint process is performed on the dielectric layer 18 to form a nanoporous pattern having a pitch of 450 nm, a pore size of 225 nm and a thickness of 150 nm.
  • the gate region is then defined with a photolithography process.
  • an etching step is performed to the dielectric layer 18 and downward to the u-GaN layer 14 of the epitaxial stacked layer 11 , so as to form a plurality of mesh holes or columns having a total depth of 30 nm and a total length of about 2 ⁇ m corresponding to the gate length.
  • an Al 2 O 3 layer of 10 nm thick is deposited on the gate region with an ALD process.
  • the Al 2 O 3 layer is then patterned to form a metal oxide layer (in the same position of the p-type metal oxide layer 24 of FIG. 1 ).
  • source and drain regions are defined through a photolithography process and followed by an etching of the dielectric layer 18 .
  • Ohmic metal electrodes 20 a and 22 a of source and drain layers 20 and 22 are then evaporated, and metal electrodes 20 b and 22 b of the source and drain layers 20 and 22 are formed through a photoresist lift off process and followed by a selective evaporation process.
  • Example 1 is a MOS-HEMT device structure in which the gate region has a nanoporous pattern.
  • the current decay performance of the MOS-HEMT of Example 1 is shown in FIG. 4
  • the current decay performance of the conventional MOS-HEMT is shown in FIG. 5 .
  • the turn on current (Id) at gate voltage (Vgs) of 10 V of the MOS-HEMT of Example 1 is 3 ⁇ 10 ⁇ 1 A/mm
  • the turn on current (Id) at gate voltage (Vgs) of 10 V of the conventional MOS-HEMT is 2 ⁇ 10 ⁇ 5 A/mn
  • the ratio is about 1.5 ⁇ 10 4 .
  • the MOS-HEMT of Example 1 in which the gate region has a nanoporous pattern is capable of significantly suppressing the current decay.
  • An epitaxial stacked layer 11 is grown on a substrate 10 .
  • a dielectric layer 18 is formed on the epitaxial stacked layer 11 .
  • source and drain regions are defined through a photolithography process and followed by an etching of the dielectric layer 18 .
  • Ohmic metal electrodes 20 a and 22 a of source and drain layers 20 and 22 are then evaporated.
  • the gate region is then defined with a photolithography process.
  • an etching step is performed to the dielectric layer 18 and downward to the u-AlGaN layer 16 of the epitaxial stacked layer 11 , and a total depth of the etching step is 15 nm.
  • An e-beam evaporation process is performed with Ni and NiO x as a horrt and an O 2 flow rate of 5 sccm, so as to form a p-type NiO y layer of 50 nm thick, wherein each of x and y is more than 1, and the p-type NiO y layer has a p-type carrier concentration of less than 1 ⁇ 10 15 /cm 3 .
  • a gate layer 28 and metal electrodes 20 b and 22 b of the source and drain layers 20 and 22 are formed through a photoresist lift off process and followed by a selective evaporation process.
  • FIG. 6 shows the gate leakage current of each of the transistor having a recessed NiO y gate of Example 2 and the conventional transistor having a recessed Schottky gate.
  • the result of FIG. 6 indicates that the gate leakage current of the transistor of Example 2 is lower than the conventional transistor having a recessed Schottky gate by 1 ⁇ 10 3 .
  • the transistor device structure of Example 2 can suppress the gate leakage current at a low p-type carrier concentration ( ⁇ 1 ⁇ 10 15 /cm 3 ).
  • An epitaxial stacked layer 11 is grown on a substrate 10 .
  • a dielectric layer 18 is formed on the epitaxial stacked layer 11 .
  • source and drain regions are defined through a photolithography process and followed by an etching of the dielectric layer 18 .
  • Ohmic metal electrodes 20 a and 22 a of source and drain layers 20 and 22 are then evaporated.
  • the gate region is then defined with a photolithography process.
  • an etching step is performed to the dielectric layer 18 and downward to the u-AlGaN layer 16 of the epitaxial stacked layer 11 , and a total depth of the etching step is 15 nm.
  • An e-beam evaporation process is performed with Ni as a horrt, an O 2 flow rate of 9 sccm and a chamber temperature of 250° C., so as to form a NiO y layer of 250 nm thick, wherein y is more than 1.
  • the sample is then transferred out and put in a RTA furnace at 500° C. under N 2 (100 sccm) for 1 minute, wherein y is more than 1 and the p-type NiO y layer has a p-type carrier concentration of less than 1 ⁇ 10 16 /cm 3 .
  • a gate layer 28 and metal electrodes 20 b and 22 b of the source and drain layers 20 and 22 are formed through a photoresist lift off process and followed by a selective evaporation.
  • FIG. 7 shows the transfer I-V characteristic curve of each of the transistor having a recessed NiO y gate of Example 3 and the conventional transistor having a recessed Schottky gate.
  • the result of FIG. 7 indicates that the transistor of Example 3 has a threshold voltage (Vth) of 0.2 V and can be a normally off device.
  • Vth threshold voltage
  • the transistor of Example 3 with such a p-type carrier concentration can effectively enhance the threshold voltage (Vth).
  • the epitaxial stacked layer 11 is grown on a substrate 10 .
  • the epitaxial stacked layer 11 includes a GaN-based buffer layer 12 of about 1-10 ⁇ m thick, an u-GaN layer 14 of about 1-5 ⁇ m thick and an u-AlGaN layer 16 of about 5-40 ⁇ m thick, wherein the aluminum content of the u-AlGaN layer 16 is 25%.
  • a dielectric layer 18 is formed on the epitaxial stacked layer 11 .
  • the dielectric layer 18 can be a SiO 2 layer, a Si 3 N 4 layer or a Si 3 N 4 /SiO 2 layer.
  • the dielectric layer 18 is deposited with a PECVD process or a sputtering process, and the thickness thereof is 10-500 nm.
  • a nano-pattern including a plurality of nano-strips, nano-columns, nano-rods or nano-pores is formed on the dielectric layer 18 with an e-beam lithography process or an nano-imprint process, and the minimum width of the nano-pattern is 50-500 nm.
  • a gate region is defined through a photolithography process, and then an etching step is performed, in which CHF 3 gas is used to etch the dielectric layer 18 , and a mixture gas including SF 6 and Cl 2 is then used until the etched depth reaches the barrier layer 16 (with a total depth of 15 nm) or the u-GaN layer 14 (with a total depth of 30 nm), wherein the gate length (Lg) is 1-10 ⁇ m.
  • Ohmic metal electrodes 20 a and 22 a of source and drain layers 20 and 22 are then formed with an e-beam evaporation process or a sputtering process.
  • the Ohmic metal electrodes 20 a and 22 a includes Ti (100 nm)/Al (300 nm), Ti (100 nm)/Al (300 nm)/Ni (40 nm)/Au (300 nm) or Ti (100 nm)/Al (300 nm)/Pt (40 nm)/Au (300 nm).
  • a rapid thermal annealing (RTA) treatment is performed thereto at 600-1000° C. under nitrogen atmosphere for 1 minute.
  • a p-type metal oxide layer 26 multiple NiO y layers with different p-type carrier concentrations are formed with an atomic layer deposition (ALD) process, a vapour deposition process, a sputtering process, a chemical vapour deposition (CVD) process, a spraying method, a sol-gel method or a pulse laser deposition (PLD) process, wherein y is more than 1.
  • ALD atomic layer deposition
  • vapour deposition process a vapour deposition process
  • a sputtering process a chemical vapour deposition (CVD) process
  • a spraying method a sol-gel method or a pulse laser deposition (PLD) process
  • PLD pulse laser deposition
  • one NiO y layer has a p-type carrier concentration of less than 1 ⁇ 10 15 /cm 3
  • another NiO y layer has a p-type carrier concentration of 1 ⁇ 10 15 to 1 ⁇ 10 17 /cm 3
  • yet another NiO y layer has a p-type carrier concentration of more than 1 ⁇ 10 17 /cm 3
  • each of the NiO y layers has a thickness of 1 nm to 200 nm.
  • a metal layer is formed with an e-beam evaporation process, and an annealing treatment is performed thereto.
  • the annealing treatment includes a rapid thermal annealing or a furnace annealing is performed at 500° C. under nitrogen atmosphere for 1 minute to 30 minutes.
  • the resulting transistor structure is shown in FIG. 2 .
  • a p-type metal oxide layer having multiple extension parts is formed in the gate region.
  • the device can be normally off, i.e., the threshold voltage (Vth) is greater than zero. Meanwhile, the turn on current of such device is not much affected, i.e., the 2DEG concentration is not much influenced.
  • Vth threshold voltage
  • multiple layers with different p-type carrier concentrations are formed as a p-type metal oxide layer can effectively suppress generation of the gate leakage current.

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Abstract

Provided is an enhancement mode GaN-based transistor device including an epitaxial stacked layer disposed on a substrate; a source layer and a drain layer disposed on a surface of the epitaxial stacked layer; a p-type metal oxide layer disposed between the source layer and the drain layer; and a gate layer disposed on the p-type metal oxide layer. Besides, the p-type metal oxide layer includes a body part disposed on the surface of the epitaxial stacked layer, and a plurality of extension parts connecting the body part and extending into the epitaxial stacked layer. With such structure, the enhancement mode GaN-based transistor device can effectively suppress generation of the gate leakage current.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 100149705, filed on Dec. 30, 2011. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
BACKGROUND Technical Field
The technical field relates to an enhancement mode gallium nitride-based (GaN-based) transistor device.
BACKGROUND
In a conventional horizontal GaN-based high electron mobility transistor (HEMT) device with a two-dimensional electron gas (2DEG), the device cannot be normally off due to the 2DEG distribution of the gate region. It has been proposed that the 2DEG distribution of the gate region is destroyed to enhance the threshold voltage (Vt), but such method may lower the output current. It also has been proposed that a p-type AlGaN layer is formed in the gate region by a selectivity area growth. Using the characteristic of the depletion region, the 2DEG distribution below the gate region is depleted so that the device can be normally off. The turn-on current of such device is not much affected, but the threshold voltage of the same is generally lower because the threshold voltage (Vth) is limited by whether the p-type carrier concentration (about 1×1017/cm2) of the p-type AlGaN layer can effectively deplete the 2DEG. Therefore, attention is drawn to an enhancement mode hetero-structure field effect transistor (HFET) device in which the threshold voltage is improved but the turn-on current is not much affected.
SUMMARY
One of exemplary embodiments includes an enhancement mode GaN-based transistor device, which includes an epitaxial stacked layer having an undoped GaN layer disposed on a substrate; a source layer and a drain layer disposed on a surface of the epitaxial stacked layer; a p-type metal oxide layer disposed between the source layer and the drain layer; and a gate layer disposed on the p-type metal oxide layer. Besides, the p-type metal oxide layer includes a body part disposed on the surface of the epitaxial stacked layer, and a plurality of extension parts connecting the body part and extending into the epitaxial stacked layer.
One of exemplary embodiments includes an enhancement mode GaN-based transistor device, which includes an epitaxial stacked layer disposed on a substrate, including an undoped GaN layer and having a recess on a surface of the epitaxial stacked layer; a source layer and a drain layer disposed on the surface of the epitaxial stacked layer beside the recess; a plurality of p-type metal oxide layers disposed on the recess between the source layer and the drain layer and having different p-type carrier concentrations from each other; and a gate layer disposed on the p-type metal oxide layer.
Several exemplary embodiments accompanied with figures are described in detail below to further describe the disclosure in details.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide further understanding, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments and, together with the description, serve to explain the principles of the disclosure.
FIG. 1 is a schematic diagram illustrating a cross-sectional view of an enhancement mode GaN-based transistor device having a single-layer p-type metal oxide layer with extension parts according to a first embodiment.
FIG. 1A is a top view along the line I-I of FIG. 1.
FIG. 1B is another top view along the line I-I of FIG. 1.
FIG. 2 is a schematic diagram illustrating a cross-sectional view of an enhancement mode GaN-based transistor device having a multi-layer p-type metal oxide layer with extension parts according to a second embodiment.
FIG. 3 is a schematic diagram illustrating a cross-sectional view of a recessed enhancement mode GaN-based transistor device having a multi-layer p-type metal oxide layer according to a third embodiment.
FIG. 4 shows the current decay performance of the MOS-HEMT device structure of Example 1 in which the gate region has a nanoporous pattern.
FIG. 5 shows the current decay performance of the conventional MOS-HEMT.
FIG. 6 shows the gate leakage current of each of the transistor having a recessed gate of Example 2 and the conventional transistor having a recessed Schottky gate.
FIG. 7 shows the transfer I-V characteristic curve of each of the transistor having a recessed gate of Example 3 and the conventional transistor having a recessed Schottky gate.
 DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS
FIG. 1 is a schematic diagram illustrating a cross-sectional view of an enhancement mode GaN-based transistor device having a single-layer p-type metal oxide layer with extension parts according to a first embodiment.
Referring to FIG. 1, the enhancement mode GaN-based transistor device of the first embodiment includes an epitaxial stacked layer 11, a source layer 20, a drain layer 22, a gate layer 28 and a p-type metal oxide layer 24. The source layer 20, the drain layer 22 and the p-type metal oxide layer 24 are disposed on the surface 11 a of the epitaxial stacked layer 11. The gate layer 28 is disposed on the p-type metal oxide layer 24. The p-type metal oxide layer 24 is disposed between the source layer 20 and the drain layer 22. The p-type metal oxide layer 24 includes a body part 34 and a plurality of extension parts 44. The body part 34 is disposed on the surface 11 a of the epitaxial stacked layer 11. The extension parts 44 connect the body part 34 and extend into the epitaxial stacked layer 11. The enhancement mode GaN-based transistor device further includes a dielectric layer 18 on the surface 11 a of the epitaxial stacked layer 11.
The epitaxial stacked layer 11 is disposed on a substrate 10. The substrate 10 can be a silicon substrate, SiC substrate or a sapphire substrate. The epitaxial stacked layer 11 includes semiconductor, such as III-V compound semiconductor. For example, the epitaxial stacked layer 11 includes GaN. In the first embodiment, the epitaxial stacked layer includes a buffer layer 12, an undoped GaN layer (u-GaN layer) 14 and a barrier layer 16 sequentially stacked on the substrate 10, but the present disclosure is not limited thereto.
The buffer layer 12 can include III-V compound semiconductor. For example, the buffer layer 12 can be a GaN-based buffer layer or an AlN-based buffer layer. The forming method of the buffer layer 12 includes a metal-organic chemical vapour deposition (MOCVD) process or a molecular beam epitaxy (MBE) process. The thickness of the buffer layer 12 ranges, for example, from about 1 μm to about 10 μm. In an embodiment, the thickness of the buffer layer 12 can be about 4.2 μm.
The u-GaN layer 14 and the barrier layer 16 form a GaN hetero-structure with a two-dimensional electron gas. The forming method of the u-GaN layer 14 includes a MOCVD process or a MBE process, and the thickness of the same ranges, for example, from about 0.5 μm to about 5 μm. In an embodiment, the thickness of the u-GaN layer 14 can be about 1.6 μm. The barrier layer 16 can be an undoped AlxGa1-xN layer (u-AlxGa1-xN layer), wherein 0.1≦x≦1. The u-AlxGa1-xN layer has an aluminium content x of 20 to 30%. The forming method of the u-AlxGa1-xN layer includes a MOCVD process or a MBE process, and the thickness of the same ranges, for example, from about 5 nm to about 40 nm. In an embodiment, the thickness of the barrier layer 16 can be about 20 nm.
The dielectric layer 18 is disposed on the epitaxial stacked layer 11. The dielectric layer 18 includes SiO2, Si3N4 or Si3N4/SiO2 and the forming method thereof includes a plasma-enhanced chemical vapour deposition (PECVD) process or a sputtering process. The thickness of the dielectric layer 18 ranges, for example, from about 10 nm to about 500 nm. The dielectric layer 18 defines the positions for the source layer 20, the drain layer 22 and the p-type metal oxide layer 24 (or the gate layer 28) with one or more photolithography-and-etching patterning processes.
A plurality of mesh holes, trenches or columns can be formed in the area, in which the p-type metal oxide layer 24 is subsequently formed, of the epitaxial stacked layer 11 with various patterning processes, so that the extension parts of the p-type metal oxide layer 24 can be subsequently formed into the epitaxial stacked layer 11. The depth of the mesh holes or trenches or the length of the columns ranges, for example, from 5 nm to 50 nm, and extends to the barrier layer 16 or the u-GaN layer 14. The size of the mesh holes, trenches or columns can be from 50 nm to 500 nm. In an embodiment, a nano-imprint process is performed on the dielectric layer 18 to form nano-mesh holes, nano-columns or nano-strips. Thereafter, a patterned photoresist layer which defines a gate region is formed with a photolithography process. Afterwards, an etching step is performed, in which CHF3 gas is used to etch the dielectric layer 18, and a mixture gas including SF6 and Cl2 is then used until the etched depth reaches the barrier layer 16 or the u-GaN layer 14. Next, a buffered oxide etch (BOE) solution is used to remove the residual dielectric layer 18 in the gate region, and a H2SO4/H2O2 solution in a volume ratio of 2:1 is used to remove the residual photoresist layer outside of the gate region. In an embodiment, when the formed nano-mesh holes, nano-columns or nano-strips are deepened into the barrier layer 16, the depth thereof is about 15 nm. In another embodiment, when the formed nano-mesh holes, nano-columns or nano-strips are deepened into the u-GaN layer 14, the depth thereof is about 30 nm.
The source layer 20 and the drain layer 22 are disposed on the surface 11 a of the epitaxial stacked layer 11 and on the dielectric layer 18. The source layer 20 includes an Ohmic metal electrode 20 a and a metal electrode 20 b. The drain layer 22 includes an Ohmic metal electrode 22 a and a metal electrode 22 b. Each of the Ohmic metal electrodes includes Ti (100 nm)/Al (300 nm), Ti (100 nm)/Al (300 nm)/Ni (40 nm)/Au (300 nm) or Ti (100 nm)/Al (300 nm)/Pt (40 nm)/Au (300 nm), but the disclosure is not limited thereto. Herein, for example, Ti (100 nm)/Al (300 nm) indicates a stacked layer including a titanium layer of 100 nm thick and an aluminum layer of 300 nm thick. The same rule can be applied to other cases. The Ohmic metal electrodes 20 a and 22 a of the source and drain layers 20 and 22 can be fabricated with an electron beam (e-beam) evaporation process followed by an annealing treatment. The annealing treatment can be a rapid thermal annealing (RTA) at 600° C. under nitrogen atmosphere for 1 minute. In an embodiment, the Ohmic metal electrodes 20 a and 22 a of the source and drain layers 20 and 22 can be fabricated, after the patterning of the dielectric layer 18 and before the formation of the p-type metal oxide layer 24, on the surface 11 a of the epitaxial stacked layer 11 and on the dielectric layer 18. In another embodiment, the Ohmic metal electrodes 20 a and 22 a of the source and drain layers 20 and 22 can be fabricated, after the patterning of the dielectric layer 18 and the formation of the p-type metal oxide layer 24, on the surface 11 a of the epitaxial stacked layer 11 and on the dielectric layer 18.
The forming method of the metal electrodes 20 b and 22 b of the source and drain layers 20 and 22 includes a photoresist lift off process and a selective evaporation process such as an e-beam evaporation. Each of the metal electrodes 20 b and 22 b of the source and drain layers 20 and 22 includes a high work function metal or an alloy, such as Ni (20 nm)/Au (300 nm), Ti (20 nm)/Au (300 nm) or Pt (20 nm)/Au (300 nm). The metal electrodes 20 b and 22 b of the source and drain layers 20 and 22 can be fabricated with an e-beam evaporation process followed by an annealing treatment. The annealing treatment can be a rapid thermal annealing (RTA) or a furnace annealing at 500° C. under nitrogen atmosphere for 1 minute to 30 minutes. The metal electrodes 20 b and 22 b of the source and drain layers 20 and 22 can be formed on the Ohmic metal electrodes 20 a and 22 a of the source and drain layers 20 and 22 after the formation of the p-type metal oxide layer 24.
The p-type metal oxide layer 24 is disposed between the source and drain layers 20 and 22. The extension parts 44 of the p-type metal oxide layer 24 at least extend into the barrier layer 16. In an embodiment, the extension parts 44 of the p-type metal oxide layer 24 at least extend into the u-GaN layer 14, as shown in FIG. 1. In an embodiment, the epitaxial stacked layer 11 (or the barrier layer 16) has a plurality of mesh holes, and the extension parts 44 of the p-type metal oxide layer 24 are shaped as a plurality of columns respectively extending into the mesh holes, top view of which is shown in FIG. 1A. In another embodiment, the epitaxial stacked layer 11 (or the barrier layer 16) has a plurality of columns, and the extension parts 44 of the p-type metal oxide layer 24 extend into a space around the columns and are shaped as a mesh. Besides, the length of the p-type metal oxide layer 24 corresponds to the gate length.
The p-type metal oxide layer 24 has a p-type carrier concentration of 1×1015 to 5×1019/cm3. The p-type metal oxide layer 24 includes multiple NiOy layers, and—1_≦y≦1.2. The p-type metal oxide layer 24 can be made of a single material layer, as shown in FIG. 1. The forming method of the p-type metal oxide layer 24 includes an atomic layer deposition (ALD) process, a vapour deposition process, a sputtering process, a chemical vapour deposition (CVD) process, a spraying method, a sol-gel method or a pulse laser deposition (PLD) process. The p-type metal oxide layer 24 can be formed after the formation of the dielectric layer 18 and before the formation of the gate layer 28 and the metal electrodes 20 b and 22 b of the source and drain layers 20 and 22.
The gate layer 28 is disposed on the p-type metal oxide layer 24. The gate layer 28 can be a metal electrode. The metal gate includes a high work function metal or an alloy, such as Ni (20 nm)/Au (300 nm), Ti (20 nm)/Au (300 nm) or Pt (20 nm)/Au (300 nm). The length of the gate layer 28 is about 2 μm, for example. In an embodiment, the forming method of the gate layer 28 includes a photoresist lift off process and a selective evaporation process. The step of forming the gate layer 28 can be simultaneously performed during the step of forming the metal electrodes 20 b and 22 b of the source and drain layers 20 and 22.
Besides, an Al2O3 layer or another metal oxide layer can be used instead of the p-type metal oxide layer 24 of the said embodiments.
FIG. 2 is a schematic diagram illustrating a cross-sectional view of an enhancement mode GaN-based transistor device having a multi-layer p-type metal oxide layer with extension parts according to a second embodiment.
In the first embodiment, the enhancement mode GaN-based transistor device has a single-layer p-type metal oxide layer 24 with extension parts. However, the present disclosure is not limited thereto. In the second embodiment, the enhancement mode GaN-based transistor device has a multi-layer p-type metal oxide layer 26 with extension parts, as shown in FIG. 2.
The p-type metal oxide layer 26 can include a plurality of p-type metal oxide layers 26 a-26 c with different p-type carrier concentrations. In an embodiment, the p-type metal oxide layer 26 is made of multiple NiOy layers with different p-type carrier concentrations, in which one NiOy layer has a p-type carrier concentration of less than 1×1015/cm3, another NiOy layer has a p-type carrier concentration of 1×1015 to 1×1017/cm3, yet another NiOy layer has a p-type carrier concentration of more than 1×1017/cm3, and each of the NiOy layers has a thickness of 1 nm to 200 nm. The forming method of the multi-layer p-type metal oxide layer 26 includes an atomic layer deposition (ALD) process, a vapour deposition process, a sputtering process, a chemical vapour deposition (CVD) process, a spraying method, a sol-gel method or a pulse laser deposition (PLD) process. The multi-layer p-type metal oxide layer 26 can be formed after the formation of the dielectric layer 18 and before the formation of the gate layer 28 and source and drain layers 20 and 22.
The above embodiments in which the enhancement mode GaN-based transistor device having a single-layer or multi-layer p-type metal oxide layer with extension parts is provided for illustration purposes and is not construed as limiting the present disclosure. The third embodiment discloses a recessed enhancement mode GaN-based transistor device having a multi-layer p-type metal oxide layer.
FIG. 3 is a schematic diagram illustrating a cross-sectional view of a recessed enhancement mode GaN-based transistor device having a multi-layer p-type metal oxide layer according to a third embodiment.
Referring to FIG. 3, the enhancement mode GaN-based transistor device of the third embodiment includes an epitaxial stacked layer 11, a source layer 20, a drain layer 22, a gate layer 28 and a p-type metal oxide layer 26. The epitaxial stacked layer 11 has a recess 30, which corresponds to the gate layer 28, on the surface 11 a thereof. In the third embodiment, the epitaxial stacked layer includes a buffer layer 12, an undoped GaN layer (u-GaN layer) 14 and a barrier layer 16 sequentially stacked on the substrate 10, but the present disclosure is not limited thereto. The bottom of the recess 30 can expose the barrier layer 16 or the u-GaN layer 14. The source layer 20 and the drain layer 22 are disposed on the surface 11 a of the epitaxial stacked layer 11. The gate layer 28 is disposed on the p-type metal oxide layer 24, corresponds to the recess 30 of the epitaxial stacked layer 11, and located between the source and drain layers 20 and 22. The multi-layer p-type metal oxide layer 26 including p-type metal oxide layers 26 a-26 c is disposed between the source and drain layers 20 and 22 and on the recess 30 of the epitaxial stacked layer 11. In an embodiment, the multi-layer p-type metal oxide layer 26 is disposed on the recess 30 of the epitaxial stacked layer 11 and extends, along the sidewall of the opening 32 of the dielectric layer 18, onto a portion of the surface of the dielectric layer 18.
The material and forming method of the multi-layer p-type metal oxide layer 26 of the third embodiment are similar to those described in the second embodiment, and the materials and forming methods of other components or layers are similar to those described in the first embodiment, so that the details are not iterated herein.
In the following Examples 1-3, the substrate 10 is a silicon substrate, and the epitaxial stacked layer 11 includes a GaN-based buffer layer 12 of 4.2 μm thick, an u-GaN layer 14 of 1.6 μm thick and an u-AlGaN layer 16 of 1.6 μm thick, wherein the u-AlGaN layer 16 has an aluminum content of 25%. The dielectric layer 18 is a SiO2 layer of 300 nm thick formed through PECVD. An etching step is performed, in which CHF3 gas is used to etch the dielectric layer 18, and a mixture gas including SF6 and Cl2 is then used until the etched depth reaches the barrier layer 16 or the u-GaN layer 14. Next, a buffered oxide etch (BOE) solution is used to remove the residual dielectric layer 18 in the gate region, and a H2SO4/H2O2 solution in a volume ratio of 2:1 is used to remove the residual photoresist layer outside of the gate region. The Ohmic metal electrodes 20 a and 22 a of the source and drain layers 20 and 22 include Ti (100 nm)/Al (300 nm), and the forming method thereof include performing an e-beam evaporation process at 600° C. under nitrogen atmosphere for 1 minute. The metal electrodes 20 b and 22 b of the source and drain layers 20 and 22 include Ni (20 nm)/Au (300 nm), and the forming method thereof include performing an e-beam evaporation process.
EXAMPLE 1
An epitaxial stacked layer 11 is grown on a substrate 10. A dielectric layer 18 is formed on the epitaxial stacked layer 11. Thereafter, an nano-imprint process is performed on the dielectric layer 18 to form a nanoporous pattern having a pitch of 450 nm, a pore size of 225 nm and a thickness of 150 nm. The gate region is then defined with a photolithography process. Afterwards, an etching step is performed to the dielectric layer 18 and downward to the u-GaN layer 14 of the epitaxial stacked layer 11, so as to form a plurality of mesh holes or columns having a total depth of 30 nm and a total length of about 2 μm corresponding to the gate length. Next, an Al2O3 layer of 10 nm thick is deposited on the gate region with an ALD process. The Al2O3 layer is then patterned to form a metal oxide layer (in the same position of the p-type metal oxide layer 24 of FIG. 1). Thereafter, source and drain regions are defined through a photolithography process and followed by an etching of the dielectric layer 18. Ohmic metal electrodes 20 a and 22 a of source and drain layers 20 and 22 are then evaporated, and metal electrodes 20 b and 22 b of the source and drain layers 20 and 22 are formed through a photoresist lift off process and followed by a selective evaporation process.
Example 1 is a MOS-HEMT device structure in which the gate region has a nanoporous pattern. The current decay performance of the MOS-HEMT of Example 1 is shown in FIG. 4, while the current decay performance of the conventional MOS-HEMT is shown in FIG. 5. From the results of FIG. 4 and FIG. 5, the turn on current (Id) at gate voltage (Vgs) of 10 V of the MOS-HEMT of Example 1 is 3×10−1 A/mm, and the turn on current (Id) at gate voltage (Vgs) of 10 V of the conventional MOS-HEMT is 2×10−5 A/mn, and the ratio is about 1.5×104. Apparently, the MOS-HEMT of Example 1 in which the gate region has a nanoporous pattern is capable of significantly suppressing the current decay.
EXAMPLE 2
An epitaxial stacked layer 11 is grown on a substrate 10. A dielectric layer 18 is formed on the epitaxial stacked layer 11. Thereafter, source and drain regions are defined through a photolithography process and followed by an etching of the dielectric layer 18. Ohmic metal electrodes 20 a and 22 a of source and drain layers 20 and 22 are then evaporated.
Afterwards, the gate region is then defined with a photolithography process. Afterwards, an etching step is performed to the dielectric layer 18 and downward to the u-AlGaN layer 16 of the epitaxial stacked layer 11, and a total depth of the etching step is 15 nm. An e-beam evaporation process is performed with Ni and NiOx as a traget and an O2 flow rate of 5 sccm, so as to form a p-type NiOy layer of 50 nm thick, wherein each of x and y is more than 1, and the p-type NiOy layer has a p-type carrier concentration of less than 1×1015/cm3. Next, a gate layer 28 and metal electrodes 20 b and 22 b of the source and drain layers 20 and 22 are formed through a photoresist lift off process and followed by a selective evaporation process.
FIG. 6 shows the gate leakage current of each of the transistor having a recessed NiOy gate of Example 2 and the conventional transistor having a recessed Schottky gate. The result of FIG. 6 indicates that the gate leakage current of the transistor of Example 2 is lower than the conventional transistor having a recessed Schottky gate by 1×103. Apparently, the transistor device structure of Example 2 can suppress the gate leakage current at a low p-type carrier concentration (<1×1015/cm3).
EXAMPLE 3
An epitaxial stacked layer 11 is grown on a substrate 10. A dielectric layer 18 is formed on the epitaxial stacked layer 11. Thereafter, source and drain regions are defined through a photolithography process and followed by an etching of the dielectric layer 18. Ohmic metal electrodes 20 a and 22 a of source and drain layers 20 and 22 are then evaporated. Afterwards, the gate region is then defined with a photolithography process. Next, an etching step is performed to the dielectric layer 18 and downward to the u-AlGaN layer 16 of the epitaxial stacked layer 11, and a total depth of the etching step is 15 nm.
An e-beam evaporation process is performed with Ni as a traget, an O2 flow rate of 9 sccm and a chamber temperature of 250° C., so as to form a NiOy layer of 250 nm thick, wherein y is more than 1. The sample is then transferred out and put in a RTA furnace at 500° C. under N2 (100 sccm) for 1 minute, wherein y is more than 1 and the p-type NiOy layer has a p-type carrier concentration of less than 1×1016/cm3. Next, a gate layer 28 and metal electrodes 20 b and 22 b of the source and drain layers 20 and 22 are formed through a photoresist lift off process and followed by a selective evaporation.
FIG. 7 shows the transfer I-V characteristic curve of each of the transistor having a recessed NiOy gate of Example 3 and the conventional transistor having a recessed Schottky gate. The result of FIG. 7 indicates that the transistor of Example 3 has a threshold voltage (Vth) of 0.2 V and can be a normally off device. As compared to the conventional transistor having a recessed Schottky gate, the transistor of Example 3 with such a p-type carrier concentration can effectively enhance the threshold voltage (Vth).
EXAMPLE 4
An epitaxial stacked layer 11 is grown on a substrate 10. The epitaxial stacked layer 11 includes a GaN-based buffer layer 12 of about 1-10 μm thick, an u-GaN layer 14 of about 1-5 μm thick and an u-AlGaN layer 16 of about 5-40 μm thick, wherein the aluminum content of the u-AlGaN layer 16 is 25%. Thereafter, a dielectric layer 18 is formed on the epitaxial stacked layer 11. The dielectric layer 18 can be a SiO2 layer, a Si3N4 layer or a Si3N4/SiO2 layer. The dielectric layer 18 is deposited with a PECVD process or a sputtering process, and the thickness thereof is 10-500 nm.
Thereafter, a nano-pattern including a plurality of nano-strips, nano-columns, nano-rods or nano-pores is formed on the dielectric layer 18 with an e-beam lithography process or an nano-imprint process, and the minimum width of the nano-pattern is 50-500 nm.
A gate region is defined through a photolithography process, and then an etching step is performed, in which CHF3 gas is used to etch the dielectric layer 18, and a mixture gas including SF6 and Cl2 is then used until the etched depth reaches the barrier layer 16 (with a total depth of 15 nm) or the u-GaN layer 14 (with a total depth of 30 nm), wherein the gate length (Lg) is 1-10 μm.
Thereafter, source and drain regions are defined through a photolithography process and followed by an etching of the dielectric layer 18. Ohmic metal electrodes 20 a and 22 a of source and drain layers 20 and 22 are then formed with an e-beam evaporation process or a sputtering process. The Ohmic metal electrodes 20 a and 22 a includes Ti (100 nm)/Al (300 nm), Ti (100 nm)/Al (300 nm)/Ni (40 nm)/Au (300 nm) or Ti (100 nm)/Al (300 nm)/Pt (40 nm)/Au (300 nm). A rapid thermal annealing (RTA) treatment is performed thereto at 600-1000° C. under nitrogen atmosphere for 1 minute.
Thereafter, as a p-type metal oxide layer 26, multiple NiOy layers with different p-type carrier concentrations are formed with an atomic layer deposition (ALD) process, a vapour deposition process, a sputtering process, a chemical vapour deposition (CVD) process, a spraying method, a sol-gel method or a pulse laser deposition (PLD) process, wherein y is more than 1. In the multiple NiOy layers, one NiOy layer has a p-type carrier concentration of less than 1×1015/cm3, another NiOy layer has a p-type carrier concentration of 1×1015 to 1×1017/cm3, yet another NiOy layer has a p-type carrier concentration of more than 1×1017/cm3, and each of the NiOy layers has a thickness of 1 nm to 200 nm. Next, a gate layer 28 and metal electrodes 20 b and 22 b of the source and drain layers 20 and 22 are formed through a photoresist lift off process and followed by a selective evaporation process. For example, a metal layer is formed with an e-beam evaporation process, and an annealing treatment is performed thereto. The annealing treatment includes a rapid thermal annealing or a furnace annealing is performed at 500° C. under nitrogen atmosphere for 1 minute to 30 minutes. The resulting transistor structure is shown in FIG. 2.
In the enhancement mode GaN-based hetero-structure field effect transistor device of the disclosure, a p-type metal oxide layer having multiple extension parts is formed in the gate region. With such structure, the device can be normally off, i.e., the threshold voltage (Vth) is greater than zero. Meanwhile, the turn on current of such device is not much affected, i.e., the 2DEG concentration is not much influenced. A wider process window is also provided. In addition, multiple layers with different p-type carrier concentrations are formed as a p-type metal oxide layer can effectively suppress generation of the gate leakage current.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.

Claims (9)

What is claimed is:
1. An enhancement mode GaN-based transistor device, comprising:
an epitaxial stacked layer, disposed on a substrate and comprising an undoped GaN layer, the epitaxial stacked layer having a continuous pattern and comprising a plurality of mesh holes separated from one another;
a source layer and a drain layer, disposed on a surface of the epitaxial stacked layer;
a p-type metal oxide layer, disposed between the source layer and the drain layer and comprising:
one body part, disposed on the surface of the epitaxial stacked layer; and
a plurality of extension columns, the extension columns being separated from one another, wherein the extension columns extend into the mesh holes of the epitaxial stacked layer from the body part, and the extension columns are in contact with and surrounded by the epitaxial stacked layer; and
a gate layer, disposed on the p-type metal oxide layer.
2. The enhancement mode GaN-based transistor device of claim 1, wherein the epitaxial stacked layer comprises:
a buffer layer;
the undoped GaN layer, disposed on the buffer layer; and
a barrier layer, disposed on the undoped GaN layer.
3. The enhancement mode GaN-based transistor device of claim 2, wherein the buffer layer comprises a GaN-based buffer layer or an AlN-based buffer layer.
4. The enhancement mode GaN-based transistor device of claim 2, wherein the barrier layer comprises an undoped AlxGa1-xN layer, and 0.1≦x≦1.
5. The enhancement mode GaN-based transistor device of claim 2, wherein the extension parts of the p-type metal oxide layer at least extends into the barrier layer.
6. The enhancement mode GaN-based transistor device of claim 2, wherein the extension parts of the p-type metal oxide layer at least extends into the undoped GaN layer.
7. The enhancement mode GaN-based transistor device of claim 1, wherein the p-type metal oxide layer comprises a NiOy layer having a p-type carrier concentration of 1×1015 to 5×1019/cm3, and 1≦y≦1.2.
8. The enhancement mode GaN-based transistor device of claim 1, wherein the p-type metal oxide layer comprises a plurality of NiOy layers with different p-type carrier concentrations, and 1≦y≦1.2, and wherein one NiOy layer has a p-type carrier concentration of less than 1×1015/cm3, another NiOy layer has a p-type carrier concentration of 1×1015 to 1×1017/cm3, and yet another NiOy layer has a p-type carrier concentration of more than 1×1017/cm3.
9. The enhancement mode GaN-based transistor device of claim 1, further comprising a dielectric layer disposed between the p-type metal oxide layer and the source layer and between the p-type metal oxide layer and the drain layer.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10566450B2 (en) * 2017-06-09 2020-02-18 Stmicroelectronics S.R.L. Normally-off HEMT transistor with selective generation of 2DEG channel, and manufacturing method thereof
US11222969B2 (en) * 2015-11-24 2022-01-11 Stmicroelectronics S.R.L. Normally-off transistor with reduced on-state resistance and manufacturing method

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014020809A1 (en) * 2012-08-03 2014-02-06 パナソニック株式会社 Nitride semiconductor device and method for manufacturing nitride semiconductor device
CN104051522B (en) * 2014-07-02 2018-05-11 苏州晶湛半导体有限公司 A kind of enhanced nitride compound semiconductor device and its manufacture method
CN104409431B (en) * 2014-10-24 2017-07-04 苏州能讯高能半导体有限公司 A kind of semiconductor devices
US9653462B2 (en) * 2014-12-26 2017-05-16 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same
US9985121B1 (en) * 2015-04-13 2018-05-29 Hrl Laboratories, Llc P-type diamond gate-GaN heterojunction FET structure
CN105070701B (en) * 2015-08-23 2018-09-14 华南理工大学 A kind of GaN base upside-down mounting HEMT device structure and preparation method thereof
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US10170580B2 (en) 2017-05-23 2019-01-01 Industrial Technology Research Institute Structure of GaN-based transistor and method of fabricating the same
TWI681561B (en) * 2017-05-23 2020-01-01 財團法人工業技術研究院 Structure of gan-based transistor and method of fabricating the same
WO2018230136A1 (en) * 2017-06-13 2018-12-20 パナソニックＩｐマネジメント株式会社 Nitride semiconductor device and method for producing same
US10388746B2 (en) * 2017-07-06 2019-08-20 Teledyne Scientific & Imaging, Llc FET with buried gate structure
DE102017125803B4 (en) 2017-11-06 2021-04-29 Institut Für Mikroelektronik Stuttgart A semiconductor device having an enhancement type transistor structure
US10700190B2 (en) 2018-01-23 2020-06-30 Vanguard International Semiconductor Corporation Semiconductor devices and methods for manufacturing the same
CN108447899A (en) * 2018-02-09 2018-08-24 江苏如高第三代半导体产业研究院有限公司 A kind of preparation method of vertical structure GaN power device
TWI678731B (en) * 2018-08-28 2019-12-01 世界先進積體電路股份有限公司 Semiconductor devices and methods for manufacturing the same
TWI714909B (en) * 2018-11-13 2021-01-01 新唐科技股份有限公司 High electron mobility transistor device and manufacturing method thereof
CN110797390B (en) * 2019-09-30 2021-12-28 西安交通大学 Enhanced GaNHEMT integrated structure and preparation method thereof
US20220069113A1 (en) * 2019-11-26 2022-03-03 Enkris Semiconductor, Inc. Semiconductor structures and manufacturing methods thereof
CN112993018A (en) * 2019-12-02 2021-06-18 吴俊鹏 Method for reducing parasitic capacitance of III-V semiconductor device and III-V semiconductor device structure
CN113823675B (en) * 2021-08-23 2023-09-29 华南理工大学 HEMT device with novel source drain field plate structure and preparation method
TWI820979B (en) * 2022-10-25 2023-11-01 世界先進積體電路股份有限公司 Semiconductor device

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050023555A1 (en) * 2002-02-21 2005-02-03 The Furukawa Electric Co., Ltd. GaN-based field effect transistor
CN101246902A (en) 2008-03-24 2008-08-20 西安电子科技大学 InAlN/GaN Heterojunction Enhanced High Electron Mobility Transistor Structure and Fabrication Method
US7442635B2 (en) 2005-01-31 2008-10-28 Interuniversitair Microelektronica Centrum (Imec) Method for producing a semiconductor device and resulting device
US20090057720A1 (en) * 2007-08-29 2009-03-05 Sanken Electric Co., Ltd. Field-Effect Semiconductor Device, and Method of Fabrication
US7576373B1 (en) 2006-02-16 2009-08-18 Panasonic Corporation Nitride semiconductor device and method for manufacturing the same
WO2009132039A2 (en) 2008-04-23 2009-10-29 Transphorm Inc. Enhancement mode iii-n hemts
US20100148184A1 (en) * 2008-12-16 2010-06-17 Furukawa Electric Co., Ltd. Gan-based field effect transistor
US20100155720A1 (en) * 2008-12-24 2010-06-24 Sanken Electric Co., Ltd Field-effect semiconductor device, and method of fabrication
US20110068371A1 (en) 2009-09-24 2011-03-24 Toyoda Gosei Co., Ltd. Group III nitride semiconductor device, production method therefor, power converter
US20110140121A1 (en) 2009-12-14 2011-06-16 Kyungpook National University Industry Academic Cooperation Foundation Enhancement normally off nitride semiconductor device and method of manufacturing the same
US20110147795A1 (en) * 2009-12-23 2011-06-23 Willy Rachmady Materials for interfacing high-k dielectric layers with iii-v semiconductors
US20110254055A1 (en) * 2010-03-29 2011-10-20 Furukawa Electric Co., Ltd. Field effect transistor and manufacturing method thereof
TW201220405A (en) 2010-11-12 2012-05-16 Univ Nat Chiao Tung A method for fabricating a GaN thin film transistor

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11791385B2 (en) * 2005-03-11 2023-10-17 Wolfspeed, Inc. Wide bandgap transistors with gate-source field plates
US7388236B2 (en) * 2006-03-29 2008-06-17 Cree, Inc. High efficiency and/or high power density wide bandgap transistors
US8212290B2 (en) * 2007-03-23 2012-07-03 Cree, Inc. High temperature performance capable gallium nitride transistor
JP2010114219A (en) * 2008-11-05 2010-05-20 Toshiba Corp Semiconductor device and method of manufacturing the same

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050023555A1 (en) * 2002-02-21 2005-02-03 The Furukawa Electric Co., Ltd. GaN-based field effect transistor
US7442635B2 (en) 2005-01-31 2008-10-28 Interuniversitair Microelektronica Centrum (Imec) Method for producing a semiconductor device and resulting device
US7576373B1 (en) 2006-02-16 2009-08-18 Panasonic Corporation Nitride semiconductor device and method for manufacturing the same
US20110062438A1 (en) * 2007-08-29 2011-03-17 Sanken Electric Co., Ltd. Field-Effect Semiconductor Device
US20090057720A1 (en) * 2007-08-29 2009-03-05 Sanken Electric Co., Ltd. Field-Effect Semiconductor Device, and Method of Fabrication
US7985987B2 (en) 2007-08-29 2011-07-26 Sanken Electric Co., Ltd. Field-effect semiconductor device
CN101246902A (en) 2008-03-24 2008-08-20 西安电子科技大学 InAlN/GaN Heterojunction Enhanced High Electron Mobility Transistor Structure and Fabrication Method
WO2009132039A2 (en) 2008-04-23 2009-10-29 Transphorm Inc. Enhancement mode iii-n hemts
US20100148184A1 (en) * 2008-12-16 2010-06-17 Furukawa Electric Co., Ltd. Gan-based field effect transistor
US20100155720A1 (en) * 2008-12-24 2010-06-24 Sanken Electric Co., Ltd Field-effect semiconductor device, and method of fabrication
US20110068371A1 (en) 2009-09-24 2011-03-24 Toyoda Gosei Co., Ltd. Group III nitride semiconductor device, production method therefor, power converter
US20110140121A1 (en) 2009-12-14 2011-06-16 Kyungpook National University Industry Academic Cooperation Foundation Enhancement normally off nitride semiconductor device and method of manufacturing the same
US20110147795A1 (en) * 2009-12-23 2011-06-23 Willy Rachmady Materials for interfacing high-k dielectric layers with iii-v semiconductors
US20110254055A1 (en) * 2010-03-29 2011-10-20 Furukawa Electric Co., Ltd. Field effect transistor and manufacturing method thereof
TW201220405A (en) 2010-11-12 2012-05-16 Univ Nat Chiao Tung A method for fabricating a GaN thin film transistor

Non-Patent Citations (9)

* Cited by examiner, † Cited by third party
Title
Chen et al, "Preparation and properties of p-type transparent conductive Cu-doped NiO films", Thin Solid Films 519 (2011), p. 4944-4947. *
Chiu et al, "Characterization of enhancement-mode AIGaN/GaN high electron mobility transistor using N2O plasma oxidation technology," Applied Physics Letters 99, Oct. 13, 2011, pp. 153508-1-153508-3.
Ganguly et al., "Presence and origin of interface charges at atomic-layer deposited Al2O3/lll-nitride heterojunctions," Applied Physics Letters 99, Nov. 9, 2011, pp. 193504-1-193504-3.
Lee et al., "Novel of Normally-off GaN HEMT Device Structure by Using Nano-rods Technology," International Conference on Compound Semiconductor Manufacturing Technology, 2012.
Lu et al., "High-Performance Integrated Dual-Gate AIGaN/GaN Enhancement-Mode Transistor," IEEE Electron Device Letters 31 (9), Sep. 2010, pp. 990-992.
Roccaforte et al, "Epitaxial NiO gate dielectric on AIGaN/GaN heterostructures," Applied Physics Letters 100, Feb. 10, 2012, pp. 063511-1-063511-4.
Uemoto et al, "Gate Injection Transistor (GIT)-A Normally-Off AIGaN/GaN Power Transistor Using Conductivity Modulation," IEEE Transactions on Electron Devices 54 (12), Dec. 2007, pp. 3393-3399.
Xuan et al, "Enhancing threshold voltage of AlGan/GaN high electron mobility transistors by nano rod structure: From depletion mode to enhancement mode," Applied Physics Letters, 2012, pp. 112105.
Yanagihara et al., "Recent advances in GaN transistors for future emerging applications," Physica Status Solidi A 206 (6), Feb. 2, 2009, pp. 1221-1227.

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11222969B2 (en) * 2015-11-24 2022-01-11 Stmicroelectronics S.R.L. Normally-off transistor with reduced on-state resistance and manufacturing method
US10566450B2 (en) * 2017-06-09 2020-02-18 Stmicroelectronics S.R.L. Normally-off HEMT transistor with selective generation of 2DEG channel, and manufacturing method thereof
US11038047B2 (en) 2017-06-09 2021-06-15 Stmicroelectronics S.R.L. Normally-off HEMT transistor with selective generation of 2DEG channel, and manufacturing method thereof
US11699748B2 (en) 2017-06-09 2023-07-11 Stmicroelectronics S.R.L. Normally-off HEMT transistor with selective generation of 2DEG channel, and manufacturing method thereof

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