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US8927387B2 - Robust isolation for thin-box ETSOI MOSFETS - Google Patents

Robust isolation for thin-box ETSOI MOSFETS Download PDF

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US8927387B2
US8927387B2 US13/442,168 US201213442168A US8927387B2 US 8927387 B2 US8927387 B2 US 8927387B2 US 201213442168 A US201213442168 A US 201213442168A US 8927387 B2 US8927387 B2 US 8927387B2
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Prior art keywords
spacers
etching
semiconductor layer
forming
layer
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US20130264641A1 (en
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Kangguo Cheng
Bruce B Doris
Balasubramanian S Haran
Sanjay Mehta
Stefan Schmitz
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GlobalFoundries Inc
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International Business Machines Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI

Definitions

  • the present invention generally relates to ETSOI MOSFETS, and more specifically to robust isolation for ETSOI MOSFETS.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistors
  • SOI semiconductor-on-insulator
  • ETSOI semiconductor-on-insulator
  • FIG. 1A illustrates a wafer including a substrate 102 , a buried oxide layer 104 and an ETSOI layer 106 . It also includes raised source/drain regions overlying the ETSOI layer 106 and adjacent to the gate structures 108 . Also shown is a dielectric 110 within the illustrated shallow trench isolation region. During normal processing, epitaxially grown silicon can develop along the sidewall of the shallow trench isolation region. In FIG. 1A , this is illustrated as epitaxially grown silicon 114 . As illustrated in FIG. 1A , epitaxially grown silicon 114 forms an unwanted connection from the substrate 102 to the raised source/drain region 112 .
  • FIG. 1B illustrates the device after the deposition of a pre-metal dielectric 116 and the formation of contact holes.
  • the hole can be etched partially into the shallow trench. This presents a problem when metal is later added, as it can also create a short between the substrate 102 and a raised source/drain region
  • the present invention provides a method of manufacturing a semiconductor device, including: providing a wafer including at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less; etching a shallow trench into the wafer, extending partially into the second semiconductor layer; forming first spacers on the sidewalls of the shallow trench; etching an area directly below and between the first spacers, exposing the underside of the first spacers; forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed; and forming a gate structure over the first semiconductor wafer.
  • the present invention provides a semiconductor device, including: a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less; at least one shallow trench isolation region extending partially into the second semiconductor layer, separating regions of the semiconductor device; a first sidewall spacer adjacent to the sidewall of the shallow trench isolation region, extending from the first semiconductor layer to the semiconductor layer, wherein a gap exists between the bottom of the first sidewall spacer and the bottom of the shallow trench isolation region; a second sidewall spacer covering the first sidewall spacer and completely filling the gap; and a gate structure overlying the first semiconductor layer.
  • the present invention provides a method of manufacturing a semiconductor device, including: providing a wafer including at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less; etching a shallow trench into the wafer, extending until the second semiconductor layer; forming first spacers on the sidewalls of the shallow trench; etching an area directly below and between the first spacers, exposing the underside of the first spacers; forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed; and forming a gate structure over the first semiconductor wafer.
  • FIG. 1A is a prior art illustration of an ETSOI device with epitaxial growth shorting.
  • FIG. 1B is a prior art illustration of an ETSOI device with a mis-aligned contact and shorting due to the metal filling.
  • FIG. 2A is a starting wafer according to an embodiment of the invention.
  • FIG. 2B illustrates the formation of shallow trenches according to an embodiment of the invention.
  • FIG. 3A illustrates the formation of first spacers according to an embodiment of the invention.
  • FIG. 3B illustrates an alternative embodiment with larger shallow trenches.
  • FIG. 4A illustrates additional etching of the shallow trenches according to an embodiment of the invention.
  • FIG. 4B illustrates an alternative embodiment with large shallow trenches and additional etching.
  • FIG. 5A illustrates the addition of insulating materials to the device according to an embodiment of the invention.
  • FIG. 5B illustrates an alternative embodiment with the addition of insulating materials.
  • FIG. 6A illustrates the device after removing several layers.
  • FIG. 6B illustrates an alternative embodiment after removing several layers.
  • FIG. 7A illustrates an alternative embodiment with an extended spacer.
  • FIG. 7B illustrates an alternative embodiment with additional substrate undercutting.
  • FIG. 7C illustrates an alternative embodiment without a second spacer.
  • FIG. 8A illustrates the device with the addition of gate structures.
  • FIG. 8B illustrates an alternative embodiment with added raised source/drain regions.
  • FIG. 9 illustrates the device with contact holes added.
  • This embodiment includes a substrate layer 200 , a thin buried oxide (thin BOX) layer 202 , an extremely thin silicon-on-insulator layer (ETSOI) 204 and a pad layer 206 as the starting wafer.
  • the present invention is not limited to this setup, and other starting wafer setups containing alternative layers can be used.
  • the substrate layer 200 is silicon.
  • different semiconductor materials can be used, including but not limited to strained silicon, silicon germanium, silicon alloys, germanium, germanium alloys.
  • a thin buried oxide layer (thin BOX) 202 overlies the substrate layer 200 .
  • thin BOX layer 202 can be deposited or grown prior to the formation of ETSOI layer 204 .
  • wafer bonding techniques can be used, using glue, adhesive polymer, or direct bonding.
  • a high energy dopant can be implanted into the substrate 200 and annealed to form thin BOX layer 202 .
  • ETSOI layer 204 includes silicon.
  • ETSOI layer 204 can include any known semiconductor material, including but not limited to strained silicon, silicon germanium, silicon alloys, germanium, germanium alloys, and the like.
  • ETSOI layer 204 can be reduced to the desired thickness by any method as is known in the art, including planarization, grinding and etching.
  • ETSOI layer 204 has a thickness ranging from 1 to 10 nm.
  • pad layer 206 ETSOI layer 204 .
  • pad layer 206 is pad oxide layer 206 .
  • Pad oxide layer 206 includes, for example, silicon dioxide.
  • pad oxide layer 206 has an overall thickness of 2 to 10 nm.
  • a shallow trench isolation (STI) region 208 is defined.
  • the dimensions of the trench formed are relevant to the size of the device and dependent on the technology for which the device is being used.
  • the width of the STI region 208 is in a range of 30-60 nm.
  • the STI can be formed by selectively removing portions of the pad oxide 206 , the ETSOI layer 204 , the thin BOX 202 , and the substrate 200 .
  • the bottom 210 of the STI 208 extends partially into substrate 200 , e.g. by approximately 5 nm. In other embodiments, it extends until reaching the substrate 200 without etching into it.
  • the shallow trench isolation is formed by known techniques of lithography, masking and etching.
  • furnace silicon nitride 300 is deposited using low pressure chemical vapor deposition (LPCVD). In an alternative embodiment, it can be deposited using plasma enhanced chemical vapor deposition (PECVD). In other embodiments, alternative spacer materials can be used as are known in the art.
  • LPCVD low pressure chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • alternative spacer materials can be used as are known in the art.
  • the furnace silicon nitride is removed from all horizontal surfaces using an anisotropic etch process.
  • this is done using plasma Reactive Ion Etching (RIE), a highly directional etching process where the ions are normal to the surface, a preferred direction, which facilitates the removal of the silicon nitride from the horizontal surfaces but leaves a layer on the vertical surfaces.
  • RIE plasma Reactive Ion Etching
  • the end result of this process is the formation of spacers 300 on the sidewalls of the STI 208 .
  • the bottom 210 of the STI 208 extends about 5 nm into the substrate 300 .
  • the spacer 300 covers the 5 nm on the sidewall of the substrate 200 .
  • the spacers 300 would not cover any of the sidewall of the substrate 200 .
  • FIG. 3B an alternative embodiment is shown.
  • large pads are used with the transistors built as isolated features as opposed to separated by shallow trenches.
  • the spacing between semiconductor layers can be between 40 and 100 ⁇ m, as is illustrated in FIG. 3B .
  • feature 208 represents the large void in between the transistor locations.
  • an additional etching step is performed.
  • the STI 208 is etched further into the substrate 200 , opening up a void below the spacers 300 .
  • an isotropic etch is performed, done primarily to etch the space between and below the recently formed spacers 300 .
  • a wet, isotropic etch is performed using potassium hydroxide (KOH) as the wet etchant.
  • KOH potassium hydroxide
  • different types of wet etchants can be used, as are known in the art.
  • a dry, anisotropic etch can be performed to clear out the space 402 underneath the spacers 300 .
  • plasma RIE can be used to etch the space 402 as illustrated in FIG. 4A .
  • This anisotropic etching process uses the hole created by the isotropic etch to carve out sidewalls below the spacers 300 , and will later be filled with another insulating material.
  • these two etching processes combine to extend bottom of the previously etched STI 208 an additional 10-100 nm into the substrate.
  • this same process can be carried out on a wafer with large pads/isolated features, as illustrated in FIG. 4B .
  • a layer of insulating material 502 is deposited over the device.
  • a hydrogen rich nitride such as hydrogen rich silicon nitride is deposited.
  • Insulating material 502 can be deposited by any number of known techniques, including but not limited to PECVD and LPCVD. In the embodiment shown in FIG. 5A , insulating material 502 completely fills the STI locations including the recently opened void 402 .
  • an oxide material 500 is deposited over the device.
  • high density plasma oxide can be used.
  • spin-on oxide or spin-on glass can be used.
  • a chemical mechanical polishing (CMP) is performed, stopping on the insulating material 502 .
  • CMP chemical mechanical polishing
  • FIG. 5A FIG. 5B is an alternative embodiment using large pads/isolated features. The process to get to this point, however, is the same. Notably, in the embodiment of FIG. 5B , there is more oxide material 500 remaining due to the larger void between features.
  • a directional nitride etch can be performed to remove it, for example a directional RIE process. Due in part to the directional nature of the etching process, the insulating material 502 inside the STI 208 remains. Other processes to remove the excess hydrogen rich nitride as are known in the art can be used here as well.
  • the pad oxide 206 is stripped from the device, exposing the ETSOI layer 204 .
  • a hydrofluoric acid (HF) etch can be performed to strip the pad oxide.
  • the oxide material 500 can also be reduced to a level equal with the ETSOI layer 204 in this or a separate etching step, depending on the embodiment and the materials chosen.
  • a high temperature densification anneal can be performed on the insulating layer 502 .
  • the high temperature densification anneal will densify the nitride.
  • the STI 208 now contains a spacer 300 covering the sidewalls of the ETSOI layer 204 and the thin BOX layer 202 .
  • the sidewall spacer terminates at the substrate sidewall. This is dependent on, if during the initial STI process, the substrate was etched into or if the etching was terminated on contact with the substrate. In the embodiment shown, the substrate was etched into, e.g. by about 5 nm, and the spacer 300 will cover these additional 5 nm of the substrate sidewall.
  • insulating material 502 has been added into the STI 208 and underneath the spacers 300 . Insulating material 502 will later act as a second spacer when gate structures are added, adding an extra layer of protection.
  • the sidewall spacer 300 extends from ETSOI layer 204 into substrate layer 200 . There is a gap between the bottom of sidewall spacer 300 and the bottom of STI 208 . Insulating material 502 covers sidewall spacer 300 , including completely filling the gap between the bottom of sidewall spacer 300 and the bottom of STI 208 .
  • FIG. 6B an alternative embodiment of the device is shown. In this embodiment with large pads/isolated features, the processing steps remain the same as in FIG. 6A .
  • FIGS. 7A-7C several different embodiments of the present invention are illustrated. All three of these illustrations represent further embodiments of the present invention when having large pads/isolated features.
  • FIG. 7A illustrates an embodiment of the invention with a spacer 300 that extends to the bottom of the substrate 200 .
  • the initial etch illustrated in FIG. 2B , extends to the bottom of the substrate 200 .
  • the additional etching as in FIG. 7B is performed; the additional nitride layer, however, is omitted.
  • this may be suitable as the additional etching of the substrate can provide enough protection from the potential shorting problems that can occur in ETSOI devices.
  • FIGS. 8A , 8 B, and 9 illustrate an embodiment of the invention with a gate structure added.
  • the following example is for illustrative purposes only, and does not represent the only embodiment in which a gate structure can be added.
  • Other gate structures that are known in the art and can be built over an ETSOI layer can serve the same purpose in the present invention.
  • the gate structure can be formed using known techniques of deposition, photolithography and etching.
  • a pattern is created over the deposited materials by first applying a photoresist to the surface to be etched. Next the photoresist is exposed to a pattern of radiation which is developed into the desired pattern using a resist developer. This allows removal of the photoresist in areas that overly the portions of the device that are to be etched. After the completion of the patterning, the portions covered by the photoresist are protected from etching while the uncovered regions are etched using a selective etching process.
  • a hard mask can be deposited over the device, and it can include silicon nitride, silicon dioxide, and the like.
  • the gate structure can include at least a gate conductor 802 overlying a gate dielectric.
  • the gate conductor 802 can include any metal known in the art to act as a conductor.
  • the gate structure can additionally include a second conductive material (not shown) overlying the gate conductor 802 .
  • This additional conducting material can include a doped semiconductor material, including a doped silicon material, such as doped polysilicon.
  • the gate dielectric can be a dielectric material, such as silicon dioxide. Additionally, the gate dielectric can include a high-k dielectric material, such as hafnium oxide, hafnium silicate, hafnium silicon oxynitride, zirconium silicate, zirconium oxide, and the like.
  • a set of first spacers 804 can be formed adjacent to and in direct contact with the sidewalls of the gate structure. In this embodiment, this first set of spacers is typically narrow, with a thickness under 15 nm. First spacers 804 can be formed using known techniques of deposition and etching. First spacers 804 can include, for example, silicon nitride.
  • Raised source/drain regions 808 can be formed adjacent to the first spacers 804 .
  • the extension regions are formed using an epitaxial growth process over the ETSOI layer.
  • the raised source/drain regions are formed by epitaxial growth of silicon germanium over the ETSOI layer. In other embodiments, the raised source/drain regions are formed by epitaxially grown carbon doped silicon.
  • second spacers 806 can be formed adjacent to and in direct contact with first spacers 804 , so as to prevent any contact from the raised source/drain regions and the gate structure.
  • the second spacers 806 can be formed by depositing a conformal film and using a highly directional etch.
  • Second spacers 806 can include a dielectric, such as silicon dioxide.
  • silicides can be formed over the raised source/drain regions.
  • high-k liner 902 can be deposited over the device.
  • High-k liner 902 can act to protect the insulating material 502 that is acting as a protective spacer from the formation mis-aligned contacts.
  • a pre-metal dielectric is additionally deposited over the device.
  • a high-density plasma oxide is used as the pre-metal dielectric, and it is deposited, for example, by high-density plasma chemical vapor deposition.
  • spin on glass is deposited over the device as the pre-metal dielectric.
  • silicon dioxide is deposited over the device.
  • Other dielectric materials can also be used as the pre-metal dielectric.
  • the deposited dielectric is patterned and etched to form the holes needed to contact the source/drain regions and gate conductor regions of the device.
  • the contact holes are filled with a metal, for example tungsten, silver, copper, gold, and the like, and then a CMP is performed until flat.
  • a metal for example tungsten, silver, copper, gold, and the like.
  • the sidewall of the device covered by the spacers 300 is protected. Due to the presence of first spacers 300 , second spacers 502 , and in some embodiments the high-k liner 902 , the formation of mis-aligned contact holes does not cause the sidewalls to become exposed. Such exposure can lead to shorting between the substrate and the raised source/drain regions when the metal is added to the contact holes.
  • Aligned contacts 904 illustrate correctly aligned contacts with no etching into the STI 208 .
  • Raised source/drain region 810 can be formed over ETSOI layer 204 in the same manner as raised source/drain region 808 .
  • the method as described above can be used in the fabrication of integrated circuit chips.
  • many field effect transistors are fabricated by this method, separated by at least one shallow trench isolation region, and electrically connected to form an integrated circuit.
  • the resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form.
  • the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections).
  • the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product.
  • the end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

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Abstract

A thin BOX ETSOI device with robust isolation and method of manufacturing. The method includes providing a wafer with at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less. The process continues with etching a shallow trench into the wafer, extending partially into the second semiconductor layer and forming first spacers on the sidewalls of said shallow trench. After spacer formation, the process continues by etching an area directly below and between the first spacers, exposing the underside of the first spacers, forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed, and forming a gate structure over the first semiconductor wafer.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to ETSOI MOSFETS, and more specifically to robust isolation for ETSOI MOSFETS.
2. Description of Related Art
Metal Oxide Semiconductor Field Effect Transistors (MOSFETS) are commonly used today in almost all electronic circuit applications. An emerging technology in the field of semiconductor-on-insulator (SOI) FET devices is the extremely thin semiconductor-on-insulator (ETSOI) MOSFET. Such a device shows excellent short channel control, which is desirable. With the trend toward continued scaling of MOSFET devices, ETSOI is a promising candidate for next generation technology.
There are, however, several manufacturing issues that can limit yield. Specifically, as the STI divot erodes as a function of the HF based cleaning and other process steps during manufacturing, the back gate or substrate wafer is exposed, leaving it susceptible to shorting due to source/drain epitaxial growth and unwanted metal gate connections, among other processes.
Referring now to FIG. 1A, a problem inherent in some current ETSOI devices is illustrated. FIG. 1A illustrates a wafer including a substrate 102, a buried oxide layer 104 and an ETSOI layer 106. It also includes raised source/drain regions overlying the ETSOI layer 106 and adjacent to the gate structures 108. Also shown is a dielectric 110 within the illustrated shallow trench isolation region. During normal processing, epitaxially grown silicon can develop along the sidewall of the shallow trench isolation region. In FIG. 1A, this is illustrated as epitaxially grown silicon 114. As illustrated in FIG. 1A, epitaxially grown silicon 114 forms an unwanted connection from the substrate 102 to the raised source/drain region 112.
Referring now to FIG. 1B, another problem inherent in some current ETSOI devices is illustrated. FIG. 1B illustrates the device after the deposition of a pre-metal dielectric 116 and the formation of contact holes. In the case of a mis-aligned contact hole 118, the hole can be etched partially into the shallow trench. This presents a problem when metal is later added, as it can also create a short between the substrate 102 and a raised source/drain region
BRIEF SUMMARY OF THE INVENTION
To overcome these deficiencies, the present invention provides a method of manufacturing a semiconductor device, including: providing a wafer including at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less; etching a shallow trench into the wafer, extending partially into the second semiconductor layer; forming first spacers on the sidewalls of the shallow trench; etching an area directly below and between the first spacers, exposing the underside of the first spacers; forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed; and forming a gate structure over the first semiconductor wafer.
According to another aspect, the present invention provides a semiconductor device, including: a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less; at least one shallow trench isolation region extending partially into the second semiconductor layer, separating regions of the semiconductor device; a first sidewall spacer adjacent to the sidewall of the shallow trench isolation region, extending from the first semiconductor layer to the semiconductor layer, wherein a gap exists between the bottom of the first sidewall spacer and the bottom of the shallow trench isolation region; a second sidewall spacer covering the first sidewall spacer and completely filling the gap; and a gate structure overlying the first semiconductor layer.
According to yet another aspect, the present invention provides a method of manufacturing a semiconductor device, including: providing a wafer including at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less; etching a shallow trench into the wafer, extending until the second semiconductor layer; forming first spacers on the sidewalls of the shallow trench; etching an area directly below and between the first spacers, exposing the underside of the first spacers; forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed; and forming a gate structure over the first semiconductor wafer.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
FIG. 1A is a prior art illustration of an ETSOI device with epitaxial growth shorting.
FIG. 1B is a prior art illustration of an ETSOI device with a mis-aligned contact and shorting due to the metal filling.
FIG. 2A is a starting wafer according to an embodiment of the invention.
FIG. 2B illustrates the formation of shallow trenches according to an embodiment of the invention.
FIG. 3A illustrates the formation of first spacers according to an embodiment of the invention.
FIG. 3B illustrates an alternative embodiment with larger shallow trenches.
FIG. 4A illustrates additional etching of the shallow trenches according to an embodiment of the invention.
FIG. 4B illustrates an alternative embodiment with large shallow trenches and additional etching.
FIG. 5A illustrates the addition of insulating materials to the device according to an embodiment of the invention.
FIG. 5B illustrates an alternative embodiment with the addition of insulating materials.
FIG. 6A illustrates the device after removing several layers.
FIG. 6B illustrates an alternative embodiment after removing several layers.
FIG. 7A illustrates an alternative embodiment with an extended spacer.
FIG. 7B illustrates an alternative embodiment with additional substrate undercutting.
FIG. 7C illustrates an alternative embodiment without a second spacer.
FIG. 8A illustrates the device with the addition of gate structures.
FIG. 8B illustrates an alternative embodiment with added raised source/drain regions.
FIG. 9 illustrates the device with contact holes added.
 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring now to FIG. 2A, a starting wafer according to an embodiment of the invention is presented. This embodiment includes a substrate layer 200, a thin buried oxide (thin BOX) layer 202, an extremely thin silicon-on-insulator layer (ETSOI) 204 and a pad layer 206 as the starting wafer. The present invention is not limited to this setup, and other starting wafer setups containing alternative layers can be used.
In an embodiment, the substrate layer 200 is silicon. In other embodiments, different semiconductor materials can be used, including but not limited to strained silicon, silicon germanium, silicon alloys, germanium, germanium alloys.
In an embodiment, a thin buried oxide layer (thin BOX) 202, i.e. an insulating layer, overlies the substrate layer 200. In an embodiment, thin BOX layer 202 can be deposited or grown prior to the formation of ETSOI layer 204. In other embodiments, wafer bonding techniques can be used, using glue, adhesive polymer, or direct bonding. In yet another embodiment, a high energy dopant can be implanted into the substrate 200 and annealed to form thin BOX layer 202.
In an embodiment, ETSOI layer 204 includes silicon. In other embodiments, ETSOI layer 204 can include any known semiconductor material, including but not limited to strained silicon, silicon germanium, silicon alloys, germanium, germanium alloys, and the like. ETSOI layer 204 can be reduced to the desired thickness by any method as is known in the art, including planarization, grinding and etching. In an embodiment, ETSOI layer 204 has a thickness ranging from 1 to 10 nm.
In an embodiment, pad layer 206 ETSOI layer 204. In an embodiment, pad layer 206 is pad oxide layer 206. Pad oxide layer 206 includes, for example, silicon dioxide. In an embodiment, pad oxide layer 206 has an overall thickness of 2 to 10 nm.
Referring now to FIG. 2B, a shallow trench isolation (STI) region 208 is defined. The dimensions of the trench formed are relevant to the size of the device and dependent on the technology for which the device is being used. In an embodiment, the width of the STI region 208 is in a range of 30-60 nm. As illustrated in FIG. 2B, the STI can be formed by selectively removing portions of the pad oxide 206, the ETSOI layer 204, the thin BOX 202, and the substrate 200. In one embodiment, as shown in FIG. 2B, the bottom 210 of the STI 208 extends partially into substrate 200, e.g. by approximately 5 nm. In other embodiments, it extends until reaching the substrate 200 without etching into it. In an embodiment, the shallow trench isolation is formed by known techniques of lithography, masking and etching.
Referring now to FIG. 3A, furnace silicon nitride 300 is deposited using low pressure chemical vapor deposition (LPCVD). In an alternative embodiment, it can be deposited using plasma enhanced chemical vapor deposition (PECVD). In other embodiments, alternative spacer materials can be used as are known in the art.
In a next processing step, the furnace silicon nitride is removed from all horizontal surfaces using an anisotropic etch process. In an embodiment this is done using plasma Reactive Ion Etching (RIE), a highly directional etching process where the ions are normal to the surface, a preferred direction, which facilitates the removal of the silicon nitride from the horizontal surfaces but leaves a layer on the vertical surfaces. The end result of this process is the formation of spacers 300 on the sidewalls of the STI 208. In the embodiment illustrated in FIG. 3A, the bottom 210 of the STI 208 extends about 5 nm into the substrate 300. As a result of this, the spacer 300 covers the 5 nm on the sidewall of the substrate 200. In an embodiment where the bottom 210 of the substrate does not extend into the substrate 200, the spacers 300 would not cover any of the sidewall of the substrate 200.
Referring now to FIG. 3B, an alternative embodiment is shown. In this embodiment, large pads are used with the transistors built as isolated features as opposed to separated by shallow trenches. In this embodiment, the spacing between semiconductor layers can be between 40 and 100 μm, as is illustrated in FIG. 3B. The processing steps taken to this point, however, remain the same. In this embodiment, feature 208 represents the large void in between the transistor locations.
Referring now to FIG. 4A, an additional etching step is performed. In this step, the STI 208 is etched further into the substrate 200, opening up a void below the spacers 300. In a first etching step, an isotropic etch is performed, done primarily to etch the space between and below the recently formed spacers 300. In an embodiment, a wet, isotropic etch is performed using potassium hydroxide (KOH) as the wet etchant. In other embodiments, different types of wet etchants can be used, as are known in the art.
Following the isotropic etch, a dry, anisotropic etch can be performed to clear out the space 402 underneath the spacers 300. In an embodiment, plasma RIE can be used to etch the space 402 as illustrated in FIG. 4A. This anisotropic etching process uses the hole created by the isotropic etch to carve out sidewalls below the spacers 300, and will later be filled with another insulating material. In an embodiment, these two etching processes combine to extend bottom of the previously etched STI 208 an additional 10-100 nm into the substrate. In another embodiment, this same process can be carried out on a wafer with large pads/isolated features, as illustrated in FIG. 4B.
Referring now to FIG. 5A, this embodiment continues with the addition of two more materials. In one processing step, a layer of insulating material 502 is deposited over the device. In an example, a hydrogen rich nitride, such as hydrogen rich silicon nitride is deposited. Insulating material 502 can be deposited by any number of known techniques, including but not limited to PECVD and LPCVD. In the embodiment shown in FIG. 5A, insulating material 502 completely fills the STI locations including the recently opened void 402.
In a next processing step, an oxide material 500 is deposited over the device. In an embodiment, high density plasma oxide can be used. In other embodiments, spin-on oxide or spin-on glass can be used.
In a next processing step, a chemical mechanical polishing (CMP) is performed, stopping on the insulating material 502. This removes most of the oxide material 500 except for on the outer edges, away from the transistor regions. This is illustrated in FIG. 5A. FIG. 5B is an alternative embodiment using large pads/isolated features. The process to get to this point, however, is the same. Notably, in the embodiment of FIG. 5B, there is more oxide material 500 remaining due to the larger void between features.
Referring now to FIG. 6A, some of the insulating material 502 and oxide 500 are removed. In an embodiment using hydrogen rich silicon nitride as the insulating material 502, a directional nitride etch can be performed to remove it, for example a directional RIE process. Due in part to the directional nature of the etching process, the insulating material 502 inside the STI 208 remains. Other processes to remove the excess hydrogen rich nitride as are known in the art can be used here as well.
In a next processing step, the pad oxide 206 is stripped from the device, exposing the ETSOI layer 204. In an embodiment, a hydrofluoric acid (HF) etch can be performed to strip the pad oxide. The oxide material 500 can also be reduced to a level equal with the ETSOI layer 204 in this or a separate etching step, depending on the embodiment and the materials chosen.
Following the stripping of pad oxide 206, a high temperature densification anneal can be performed on the insulating layer 502. In an embodiment with hydrogen rich silicon nitride as the insulating layer 502, the high temperature densification anneal will densify the nitride.
As a result of these etching steps, the STI 208 now contains a spacer 300 covering the sidewalls of the ETSOI layer 204 and the thin BOX layer 202. In one embodiment, the sidewall spacer terminates at the substrate sidewall. This is dependent on, if during the initial STI process, the substrate was etched into or if the etching was terminated on contact with the substrate. In the embodiment shown, the substrate was etched into, e.g. by about 5 nm, and the spacer 300 will cover these additional 5 nm of the substrate sidewall.
In addition to the spacer 300, insulating material 502 has been added into the STI 208 and underneath the spacers 300. Insulating material 502 will later act as a second spacer when gate structures are added, adding an extra layer of protection. In this embodiment, the sidewall spacer 300 extends from ETSOI layer 204 into substrate layer 200. There is a gap between the bottom of sidewall spacer 300 and the bottom of STI 208. Insulating material 502 covers sidewall spacer 300, including completely filling the gap between the bottom of sidewall spacer 300 and the bottom of STI 208.
Referring now to FIG. 6B, an alternative embodiment of the device is shown. In this embodiment with large pads/isolated features, the processing steps remain the same as in FIG. 6A.
Referring now to FIGS. 7A-7C, several different embodiments of the present invention are illustrated. All three of these illustrations represent further embodiments of the present invention when having large pads/isolated features. FIG. 7A illustrates an embodiment of the invention with a spacer 300 that extends to the bottom of the substrate 200. In this embodiment, the initial etch, illustrated in FIG. 2B, extends to the bottom of the substrate 200.
In the embodiment illustrated in FIG. 7B, there is an additional undercutting of the substrate. Prior to the deposition of the insulating material 502, additional isotropic etching is performed which cuts into substrate 200 underlying the thin BOX layer 202. From this, the process continues as the embodiment previously described. As a result, extra protection from shorting and epitaxial growth from the substrate to a later added raised source/drain region is provided by the extra insulation.
In the embodiment illustrated in FIG. 7C, the additional etching as in FIG. 7B is performed; the additional nitride layer, however, is omitted. For some applications, this may be suitable as the additional etching of the substrate can provide enough protection from the potential shorting problems that can occur in ETSOI devices.
The remaining FIGS. 8A, 8B, and 9 illustrate an embodiment of the invention with a gate structure added. The following example is for illustrative purposes only, and does not represent the only embodiment in which a gate structure can be added. Other gate structures that are known in the art and can be built over an ETSOI layer can serve the same purpose in the present invention.
Referring now to FIG. 8A, one embodiment of a gate structure that can be fabricated over the ETSOI layer is illustrated. The gate structure can be formed using known techniques of deposition, photolithography and etching. A pattern is created over the deposited materials by first applying a photoresist to the surface to be etched. Next the photoresist is exposed to a pattern of radiation which is developed into the desired pattern using a resist developer. This allows removal of the photoresist in areas that overly the portions of the device that are to be etched. After the completion of the patterning, the portions covered by the photoresist are protected from etching while the uncovered regions are etched using a selective etching process. A hard mask can be deposited over the device, and it can include silicon nitride, silicon dioxide, and the like.
The gate structure can include at least a gate conductor 802 overlying a gate dielectric. The gate conductor 802 can include any metal known in the art to act as a conductor. The gate structure can additionally include a second conductive material (not shown) overlying the gate conductor 802. This additional conducting material can include a doped semiconductor material, including a doped silicon material, such as doped polysilicon. The gate dielectric can be a dielectric material, such as silicon dioxide. Additionally, the gate dielectric can include a high-k dielectric material, such as hafnium oxide, hafnium silicate, hafnium silicon oxynitride, zirconium silicate, zirconium oxide, and the like.
A set of first spacers 804 can be formed adjacent to and in direct contact with the sidewalls of the gate structure. In this embodiment, this first set of spacers is typically narrow, with a thickness under 15 nm. First spacers 804 can be formed using known techniques of deposition and etching. First spacers 804 can include, for example, silicon nitride.
Raised source/drain regions 808 can be formed adjacent to the first spacers 804. In one embodiment, the extension regions are formed using an epitaxial growth process over the ETSOI layer. In an embodiment, the raised source/drain regions are formed by epitaxial growth of silicon germanium over the ETSOI layer. In other embodiments, the raised source/drain regions are formed by epitaxially grown carbon doped silicon.
In an embodiment, second spacers 806 can be formed adjacent to and in direct contact with first spacers 804, so as to prevent any contact from the raised source/drain regions and the gate structure. The second spacers 806 can be formed by depositing a conformal film and using a highly directional etch. Second spacers 806 can include a dielectric, such as silicon dioxide. In a next step, silicides can be formed over the raised source/drain regions.
Referring now to FIG. 9, high-k liner 902 can be deposited over the device. High-k liner 902 can act to protect the insulating material 502 that is acting as a protective spacer from the formation mis-aligned contacts. Following this, a pre-metal dielectric is additionally deposited over the device. In an embodiment, a high-density plasma oxide is used as the pre-metal dielectric, and it is deposited, for example, by high-density plasma chemical vapor deposition. In another embodiment, spin on glass is deposited over the device as the pre-metal dielectric. In another embodiment, silicon dioxide is deposited over the device. Other dielectric materials can also be used as the pre-metal dielectric.
In an embodiment, the deposited dielectric is patterned and etched to form the holes needed to contact the source/drain regions and gate conductor regions of the device. The contact holes are filled with a metal, for example tungsten, silver, copper, gold, and the like, and then a CMP is performed until flat. In the event of mis-aligned contacts 906, the sidewall of the device covered by the spacers 300 is protected. Due to the presence of first spacers 300, second spacers 502, and in some embodiments the high-k liner 902, the formation of mis-aligned contact holes does not cause the sidewalls to become exposed. Such exposure can lead to shorting between the substrate and the raised source/drain regions when the metal is added to the contact holes. Additionally, epitaxial growth of silicon on the sidewalls which can also lead to shorting between the substrate and the raised source/drain regions is prevented by the presence of the first spacers 300 and second spacers 502. Aligned contacts 904 illustrate correctly aligned contacts with no etching into the STI 208.
Referring now to FIG. 8B, an embodiment with large pads and isolated features is illustrated. Raised source/drain region 810 can be formed over ETSOI layer 204 in the same manner as raised source/drain region 808.
The method as described above can be used in the fabrication of integrated circuit chips. In an embodiment, many field effect transistors are fabricated by this method, separated by at least one shallow trench isolation region, and electrically connected to form an integrated circuit.
The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
While the present invention has been described with reference to what are presently considered to be the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

Claims (11)

What is claimed is:
1. A method of manufacturing a semiconductor device, comprising:
providing a wafer comprising a pad oxide layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein said first semiconductor layer has a thickness of 10 nm or less;
etching a shallow trench isolation (STI) region into said wafer, extending partially into said second semiconductor layer;
forming first spacers on sidewalls of said STI region;
etching an area directly below and between said first spacers, exposing an underside of said first spacers;
forming second spacers covering all exposed portions of said first spacers, wherein said pad oxide layer is removed; and
forming a gate structure over said first semiconductor layer;
wherein said forming said second spacers comprises:
depositing a hydrogen-rich silicon nitride insulating material over said semiconductor device, including spaces below and between said first spacers, and performing an anneal to densify the hydrogen-rich silicon nitride insulating material;
depositing an oxide material over said semiconductor device;
planarizing said semiconductor device, stopping on said hydrogen-rich silicon nitride insulating material;
etching said hydrogen-rich silicon nitride insulating material at and above said pad oxide layer; and
etching to remove said pad oxide layer.
2. The method according to claim 1, wherein said etching said area directly below and between said first spacers comprises:
etching into said second semiconductor layer a space between said first spacers by an isotropic etch; and
etching by an anisotropic etch a space below said first spacers.
3. The method according to claim 2, wherein said isotropic etch comprises a wet etch with potassium hydroxide as an etchant.
4. The method according to claim 2, wherein said anisotropic etch comprises a reactive ion etching process.
5. The method according to claim 1, wherein said first spacers comprise silicon nitride.
6. The method according to claim 1, wherein a width of said STI region is in a range of 30 to 60 nanometers.
7. The method according to claim 1, wherein a width of said STI region is in a range of 40 to 100 micrometers.
8. The method according to claim 7, wherein said depositing said oxide material over said semiconductor device further comprising depositing said oxide material in said STI region.
9. The method according to claim 1, wherein said first and said second semiconductor layers comprise silicon.
10. The method according to claim 1, wherein said forming said gate structure comprises:
depositing at least a dielectric material followed by a first gate conductor material over said first semiconductor layer;
etching said dielectric material and said first gate conductor material to form a gate;
forming third spacers adjacent to and in direct contact with said gate;
forming epitaxially grown raised source/drain regions adjacent to said third spacers and overlying said first semiconductor layer;
depositing fourth spacers adjacent to and in direct contact with said third spacers; and
forming silicides over said epitaxially grown raised source/drain regions.
11. The method according to claim 1, wherein said second spacers completely fill the STI region.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11569353B2 (en) 2021-02-02 2023-01-31 Micron Technology, Inc. Apparatuses including passing word lines comprising a band offset material, and related methods and systems

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10020383B2 (en) * 2015-05-20 2018-07-10 Globalfoundries Inc. Preserving the seed layer on STI edge and improving the epitaxial growth

Citations (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5183771A (en) 1989-01-07 1993-02-02 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing lddfet having double sidewall spacers
US5714413A (en) 1995-12-11 1998-02-03 Intel Corporation Method of making a transistor having a deposited dual-layer spacer structure
US5904541A (en) * 1996-06-27 1999-05-18 Hyundai Electronics Industries Co., Ltd. Method for fabricating a semiconductor device having a shallow trench isolation structure
US5972758A (en) * 1997-12-04 1999-10-26 Intel Corporation Pedestal isolated junction structure and method of manufacture
US6254620B1 (en) 1997-02-07 2001-07-03 Karl Storz Gmbh & Co. Kg Surgical thread cutter
US6294423B1 (en) * 2000-11-21 2001-09-25 Infineon Technologies North America Corp. Method for forming and filling isolation trenches
US20010026996A1 (en) * 1997-02-18 2001-10-04 Norio Ishitsuka Semiconductor device and process for producing the sme
US6313008B1 (en) * 2001-01-25 2001-11-06 Chartered Semiconductor Manufacturing Inc. Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon
US20020039835A1 (en) * 2000-07-25 2002-04-04 International Business Machines Corporation Method of depositing a conformal hydrogen-rich silicon nitride layer onto a patterned structure
US20020070420A1 (en) * 2000-12-09 2002-06-13 Oh Yong-Chul Integrated circuits having adjacent P-type doped regions having shallow trench isolation structures without liner layers therein therebetween and methods of forming same
US6483172B1 (en) * 1998-03-09 2002-11-19 Siemens Aktiengesellschaft Semiconductor device structure with hydrogen-rich layer for facilitating passivation of surface states
US6518641B2 (en) * 2001-05-18 2003-02-11 International Business Machines Corporation Deep slit isolation with controlled void
US6548357B2 (en) 2000-11-15 2003-04-15 International Business Machines Corporation Modified gate processing for optimized definition of array and logic devices on same chip
US6607967B1 (en) * 2000-11-15 2003-08-19 Lsi Logic Corporation Process for forming planarized isolation trench in integrated circuit structure on semiconductor substrate
US6649964B2 (en) * 2000-09-22 2003-11-18 Hynix Semiconductor, Inc. Body-to-substrate contact structure for SOI device and method for fabricating same
US6784076B2 (en) * 2002-04-08 2004-08-31 Micron Technology, Inc. Process for making a silicon-on-insulator ledge by implanting ions from silicon source
US20050136588A1 (en) * 2003-12-23 2005-06-23 Chris Speyer Method of forming isolation regions
US20050139952A1 (en) * 2003-12-30 2005-06-30 Kwan Joo Koh Active cell isolation body of a semiconductor device and method for forming the same
US20050142804A1 (en) * 2003-12-30 2005-06-30 Dongbuanam Semiconductor Inc. Method for fabricating shallow trench isolation structure of semiconductor device
US20050153519A1 (en) * 2004-01-08 2005-07-14 Taiwan Semiconductor Manufacturing Co. Novel shallow trench isolation method for reducing oxide thickness variations at different pattern densities
US6946696B2 (en) * 2002-12-23 2005-09-20 International Business Machines Corporation Self-aligned isolation double-gate FET
US20060220146A1 (en) * 2005-03-31 2006-10-05 Sanyo Electric Co., Ltd. Semiconductor device
US20060223279A1 (en) * 2005-04-01 2006-10-05 Micron Technology, Inc. Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry
US20060223290A1 (en) * 2005-04-01 2006-10-05 International Business Machines Corporation Method of producing highly strained pecvd silicon nitride thin films at low temperature
US7153753B2 (en) * 2003-08-05 2006-12-26 Micron Technology, Inc. Strained Si/SiGe/SOI islands and processes of making same
US20070059897A1 (en) * 2005-09-09 2007-03-15 Armin Tilke Isolation for semiconductor devices
US7230270B2 (en) * 2004-11-24 2007-06-12 Taiwan Semiconductor Manfacturing Company, Ltd. Self-aligned double gate device and method for forming same
US20070141852A1 (en) * 2005-12-20 2007-06-21 Chris Stapelmann Methods of fabricating isolation regions of semiconductor devices and structures thereof
US20070212848A1 (en) * 2006-03-10 2007-09-13 Micron Technology, Inc. Method of making an isolation trench and resulting isolation trench
US20070224775A1 (en) * 2006-03-27 2007-09-27 Nick Lindert Trench isolation structure having an expanded portion thereof
US7442618B2 (en) * 2005-07-16 2008-10-28 Chartered Semiconductor Manufacturing, Ltd Method to engineer etch profiles in Si substrate for advanced semiconductor devices
US20080283935A1 (en) * 2007-05-18 2008-11-20 Texas Instruments Incorporated Trench isolation structure and method of manufacture therefor
US20090160031A1 (en) * 2007-12-24 2009-06-25 Dae Kyeun Kim Semiconductor Device and Method for Fabricating the Same
US7622778B2 (en) * 2005-05-18 2009-11-24 Samsung Electronic Co., Ltd. Semiconductor device having shallow trench isolation structure comprising an upper trench and a lower trench including a void
US20100038745A1 (en) * 2008-08-18 2010-02-18 Promos Technologies Inc. Integrated circuit structure having bottle-shaped isolation
US7700416B1 (en) * 2008-04-25 2010-04-20 Acorn Technologies, Inc. Tensile strained semiconductor on insulator using elastic edge relaxation and a sacrificial stressor layer
US7704835B2 (en) 2006-12-29 2010-04-27 Intel Corporation Method of forming a selective spacer in a semiconductor device
US7705417B2 (en) 2006-08-04 2010-04-27 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating isolation region
US20100213522A1 (en) * 2009-02-23 2010-08-26 International Business Machines Corporation Method for forming a semiconductor structure to remedy box undercut and structure formed thereby
US7799694B2 (en) * 2006-04-11 2010-09-21 Micron Technology, Inc. Methods of forming semiconductor constructions
US20100258869A1 (en) * 2009-04-10 2010-10-14 Hitachi, Ltd. Semiconductor device and manufacturing method thereof
US7818702B2 (en) * 2007-02-28 2010-10-19 International Business Machines Corporation Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates
US20110024840A1 (en) * 2009-07-29 2011-02-03 International Business Machines Corporation Soi transistors having an embedded extension region to improve extension resistance and channel strain characteristics
US7883953B2 (en) * 2008-09-30 2011-02-08 Freescale Semiconductor, Inc. Method for transistor fabrication with optimized performance
US20110037125A1 (en) * 2009-08-17 2011-02-17 International Business Machines Corporation Extremely thin silicon on insulator (etsoi) complementary metal oxide semiconductor (cmos) with in-situ doped source and drain regions formed by a single mask
US7935602B2 (en) * 2005-06-28 2011-05-03 Micron Technology, Inc. Semiconductor processing methods
US20110115021A1 (en) * 2009-11-16 2011-05-19 International Business Machines Corporation Isolation structures for soi devices with ultrathin soi and ultrathin box

Patent Citations (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5183771A (en) 1989-01-07 1993-02-02 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing lddfet having double sidewall spacers
US5714413A (en) 1995-12-11 1998-02-03 Intel Corporation Method of making a transistor having a deposited dual-layer spacer structure
US5904541A (en) * 1996-06-27 1999-05-18 Hyundai Electronics Industries Co., Ltd. Method for fabricating a semiconductor device having a shallow trench isolation structure
US6254620B1 (en) 1997-02-07 2001-07-03 Karl Storz Gmbh & Co. Kg Surgical thread cutter
US20010026996A1 (en) * 1997-02-18 2001-10-04 Norio Ishitsuka Semiconductor device and process for producing the sme
US5972758A (en) * 1997-12-04 1999-10-26 Intel Corporation Pedestal isolated junction structure and method of manufacture
US6483172B1 (en) * 1998-03-09 2002-11-19 Siemens Aktiengesellschaft Semiconductor device structure with hydrogen-rich layer for facilitating passivation of surface states
US20020039835A1 (en) * 2000-07-25 2002-04-04 International Business Machines Corporation Method of depositing a conformal hydrogen-rich silicon nitride layer onto a patterned structure
US6649964B2 (en) * 2000-09-22 2003-11-18 Hynix Semiconductor, Inc. Body-to-substrate contact structure for SOI device and method for fabricating same
US6548357B2 (en) 2000-11-15 2003-04-15 International Business Machines Corporation Modified gate processing for optimized definition of array and logic devices on same chip
US6607967B1 (en) * 2000-11-15 2003-08-19 Lsi Logic Corporation Process for forming planarized isolation trench in integrated circuit structure on semiconductor substrate
US6294423B1 (en) * 2000-11-21 2001-09-25 Infineon Technologies North America Corp. Method for forming and filling isolation trenches
US20020070420A1 (en) * 2000-12-09 2002-06-13 Oh Yong-Chul Integrated circuits having adjacent P-type doped regions having shallow trench isolation structures without liner layers therein therebetween and methods of forming same
US6313008B1 (en) * 2001-01-25 2001-11-06 Chartered Semiconductor Manufacturing Inc. Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon
US6518641B2 (en) * 2001-05-18 2003-02-11 International Business Machines Corporation Deep slit isolation with controlled void
US6784076B2 (en) * 2002-04-08 2004-08-31 Micron Technology, Inc. Process for making a silicon-on-insulator ledge by implanting ions from silicon source
US6946696B2 (en) * 2002-12-23 2005-09-20 International Business Machines Corporation Self-aligned isolation double-gate FET
US7153753B2 (en) * 2003-08-05 2006-12-26 Micron Technology, Inc. Strained Si/SiGe/SOI islands and processes of making same
US20050136588A1 (en) * 2003-12-23 2005-06-23 Chris Speyer Method of forming isolation regions
US20050142804A1 (en) * 2003-12-30 2005-06-30 Dongbuanam Semiconductor Inc. Method for fabricating shallow trench isolation structure of semiconductor device
US20050139952A1 (en) * 2003-12-30 2005-06-30 Kwan Joo Koh Active cell isolation body of a semiconductor device and method for forming the same
US20050153519A1 (en) * 2004-01-08 2005-07-14 Taiwan Semiconductor Manufacturing Co. Novel shallow trench isolation method for reducing oxide thickness variations at different pattern densities
US7230270B2 (en) * 2004-11-24 2007-06-12 Taiwan Semiconductor Manfacturing Company, Ltd. Self-aligned double gate device and method for forming same
US20060220146A1 (en) * 2005-03-31 2006-10-05 Sanyo Electric Co., Ltd. Semiconductor device
US20060223279A1 (en) * 2005-04-01 2006-10-05 Micron Technology, Inc. Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry
US20060223290A1 (en) * 2005-04-01 2006-10-05 International Business Machines Corporation Method of producing highly strained pecvd silicon nitride thin films at low temperature
US7622778B2 (en) * 2005-05-18 2009-11-24 Samsung Electronic Co., Ltd. Semiconductor device having shallow trench isolation structure comprising an upper trench and a lower trench including a void
US7935602B2 (en) * 2005-06-28 2011-05-03 Micron Technology, Inc. Semiconductor processing methods
US7442618B2 (en) * 2005-07-16 2008-10-28 Chartered Semiconductor Manufacturing, Ltd Method to engineer etch profiles in Si substrate for advanced semiconductor devices
US20070059897A1 (en) * 2005-09-09 2007-03-15 Armin Tilke Isolation for semiconductor devices
US20070141852A1 (en) * 2005-12-20 2007-06-21 Chris Stapelmann Methods of fabricating isolation regions of semiconductor devices and structures thereof
US20070212848A1 (en) * 2006-03-10 2007-09-13 Micron Technology, Inc. Method of making an isolation trench and resulting isolation trench
US20070224775A1 (en) * 2006-03-27 2007-09-27 Nick Lindert Trench isolation structure having an expanded portion thereof
US7799694B2 (en) * 2006-04-11 2010-09-21 Micron Technology, Inc. Methods of forming semiconductor constructions
US7705417B2 (en) 2006-08-04 2010-04-27 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating isolation region
US7704835B2 (en) 2006-12-29 2010-04-27 Intel Corporation Method of forming a selective spacer in a semiconductor device
US7818702B2 (en) * 2007-02-28 2010-10-19 International Business Machines Corporation Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates
US20080283935A1 (en) * 2007-05-18 2008-11-20 Texas Instruments Incorporated Trench isolation structure and method of manufacture therefor
US20090160031A1 (en) * 2007-12-24 2009-06-25 Dae Kyeun Kim Semiconductor Device and Method for Fabricating the Same
US7700416B1 (en) * 2008-04-25 2010-04-20 Acorn Technologies, Inc. Tensile strained semiconductor on insulator using elastic edge relaxation and a sacrificial stressor layer
US20100038745A1 (en) * 2008-08-18 2010-02-18 Promos Technologies Inc. Integrated circuit structure having bottle-shaped isolation
US7883953B2 (en) * 2008-09-30 2011-02-08 Freescale Semiconductor, Inc. Method for transistor fabrication with optimized performance
US20100213522A1 (en) * 2009-02-23 2010-08-26 International Business Machines Corporation Method for forming a semiconductor structure to remedy box undercut and structure formed thereby
US20100258869A1 (en) * 2009-04-10 2010-10-14 Hitachi, Ltd. Semiconductor device and manufacturing method thereof
US20110024840A1 (en) * 2009-07-29 2011-02-03 International Business Machines Corporation Soi transistors having an embedded extension region to improve extension resistance and channel strain characteristics
US20110037125A1 (en) * 2009-08-17 2011-02-17 International Business Machines Corporation Extremely thin silicon on insulator (etsoi) complementary metal oxide semiconductor (cmos) with in-situ doped source and drain regions formed by a single mask
US20110115021A1 (en) * 2009-11-16 2011-05-19 International Business Machines Corporation Isolation structures for soi devices with ultrathin soi and ultrathin box

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
E. Chen, "III. Wet and Dry Etching", Apr. 12, 2004, Harvard University, Applied Physics 298r, pp. 1-18. *
R. A. Vega et al., "Low-Standby-Power Bulk MOSFET Design Using High-k Trench Isolation," IEEE Electron Device Letters, Dec. 2009, pp. 1380-1382, vol. 30, Issue: 12.
S. Mayuzumi et al., "High-Performance Metal/High-k n- and p-MOSFETs Top-Cut Dual Stress Liners . . . ," IEEE Transactions on Electron Devices, 2009, pp. 620-626 vol. 56, issue 4.

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11569353B2 (en) 2021-02-02 2023-01-31 Micron Technology, Inc. Apparatuses including passing word lines comprising a band offset material, and related methods and systems

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