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US8826056B2 - Circuit protection system and method - Google Patents

Circuit protection system and method Download PDF

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Publication number
US8826056B2
US8826056B2 US13/285,026 US201113285026A US8826056B2 US 8826056 B2 US8826056 B2 US 8826056B2 US 201113285026 A US201113285026 A US 201113285026A US 8826056 B2 US8826056 B2 US 8826056B2
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Prior art keywords
pch
signal
power chip
control unit
circuit protection
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Expired - Fee Related, expires
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US13/285,026
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US20120311367A1 (en
Inventor
Ying-Bin Fu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
Original Assignee
Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Assigned to HONG FU JIN PRECISION INDUSTRY (SHENZHEN) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD. reassignment HONG FU JIN PRECISION INDUSTRY (SHENZHEN) CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FU, Ying-bin
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision

Definitions

  • the present disclosure relates to circuit protection systems, and particularly to a protection system and a protection method for a circuit utilizing a power chip.
  • the power chip pulls down the potential of a PW_OK signal output to the main chip when the voltage output by the power chip is excessive or insufficient, to protect the main chip and the power chip.
  • the power chip still works during the interval, the power chip could be damaged or destroyed.
  • FIG. 1 is a block diagram of an embodiment of a circuit protection system of the present disclosure.
  • FIG. 2 is a flowchart of an embodiment of a circuit protection method of the present disclosure.
  • an exemplary embodiment of a circuit protection system which is applied to an electronic system, includes a central processing unit (CPU) 70 , a first CPU power chip 10 for powering the CPU 70 .
  • a platform controller hub (PCH) 50 , a second PCH power chip 20 for powering the PCH 50 , a control unit 30 , a basic input output system (BIOS) 40 , and a power supply 60 .
  • the first CPU power chip 10 , the second PCH power chip 20 , the BIOS 40 , and the PCH 50 are all connected to the control unit 30 .
  • the power supply 60 is coupled to the PCH 50 .
  • the CPU 70 , the first CPU power chip 10 , the PCH 50 , the second PCH power chip 20 , and the BIOS 40 are all elements of the electronic system.
  • S 0 is the working state.
  • S 1 is the standby state in which the CPU is disabled while other chips and buses are enabled.
  • S 2 is the power standby state in which the CPU and buses are disabled while other chips are enabled.
  • S 3 is the suspend to RAM state in which the main memory is powered for storing the content, while other devices are not powered.
  • S 4 is the suspend to disk state in which all content of the main memory is saved to hard disk drive.
  • S 5 is the shutdown state in which all devices are disabled.
  • the circuit protection system is ACPI compatible. To correspond to the ACPI specification, the current state of the system has to be stored in the BIOS 40 . Hence, the current state of the circuit protection system can be obtained from the BIOS 40 .
  • control unit 30 is a complex programmable logic device (CPLD).
  • the control unit 30 detects the PW_OK signals output from the power chips, that is, the first CPU power chip 10 and the second PCH power chip 20 , to determine whether the potential of the PW_OK signals output to the main chips, that is, the CPU 70 and the PCH 50 , are low, such as logical 0. If any one of the potential of the PW_OK signals of the power chips is low, the control unit 30 gets the current state of the electronic system through the BIOS 40 .
  • CPLD complex programmable logic device
  • the potential of the PW_OK signal output from the CPU power chip 10 to the CPU 70 , detected by the control unit 30 , is low, and the current state of the electronic system obtained by the control unit 30 through the BIOS 20 is S 1 . Since the CPU 70 should be disabled in state S 1 to correspond to the ACPI specification, the first CPU power chip 10 has to output a PW_OK signal of low potential to the CPU 70 . Hence, the status of the potential of the PW_OK signal of the first CPU power chip 10 is considered to correspond to the predetermined status for the first CPU power chip 10 , defined in the current state of the circuit protection system.
  • the potential of the PW_OK signal output from the second PCH power chip 20 to the PCH 50 is low, and the current state of the electronic system obtained by the control unit 30 through the BIOS 20 is S 1 . Since the PCH 50 should be enabled in state S 1 to correspond to the ACPI specification, the second PCH power chip 20 has to output a PW_OK signal of high potential, such as logical 1, to the PCH 50 . Hence, the status of the potential of the PW_OK signal of the second PCH power chip 20 is not considered to correspond to the predetermined status for the second PCH power chip 20 , defined in the current state of the circuit protection system.
  • the control unit 30 correspondingly outputs an enable signal of low potential to disable the second PCH power chip 20 , and outputs a system PW_OK signal of low potential to the PCH 50 .
  • the PCH 50 outputs a PS_ON signal of high potential to the power supply 60 to shut down the electronic system in response to receiving the enable signal of low potential, to avoid further damage caused by excessive or insufficient voltage.
  • the circuit protection method of the present disclosure is as follows. Depending on the embodiment, certain of the steps described may be removed, others may be added, and the sequence of steps may be altered. It is also to be understood that the description and the claims drawn to a method may include some indication in reference to certain steps. However, the indication used is only to be viewed for identification purposes and not as a suggestion as to an order for the steps.
  • step S 1 the control unit 30 determines whether the potential of the PW_OK signal output from at least one of the power chips 10 and 20 is low. If the potential of the PW_OK signal output by any one of the power chip 10 / 20 is low, step S 2 is implemented; otherwise, step S 1 is repeated.
  • step S 2 the correspondence between the current status of the potential of the PW_OK signal output by the power chip 10 / 20 and the predetermined status of the power chip 10 / 20 defined in the current state of the electronic system is determined.
  • the control unit 30 gets the current state of the electronic system through the BIOS 40 . Since the potential of the PW_OK signal output by the power chip 10 / 20 determined in step S 1 is low, the corresponding main chip is disabled. If the current status of the PW_OK signal corresponds to the predetermined status of the PW_OK signal of the power chip 10 / 20 which defined in the current state of the electronic system, return to step S 1 ; otherwise, step S 3 is implemented.
  • step S 3 the control unit 30 outputs an enable signal to disable the power chip 10 / 20 , and a system PW_OK signal of low potential to the PCH 50 .
  • step S 2 if the current status of the PW_OK signal of the power chip 10 / 20 does not correspond to the predetermined status of the power chip 10 / 20 defined in the current state of the electronic system, there should be problems because the power chip 10 / 20 outputs the PW_OK signal of low potential. For example, the voltage output by the power chip 10 / 20 is excessive or insufficient.
  • control unit 30 outputs an enable signal of low potential to the power chip 10 / 20 and the system PW_OK signal of low potential to the PCH 50 , thereby disabling the power chip 10 / 20 to avoid the damage caused by excessive or insufficient voltage.
  • step S 4 The PCH 50 outputs a PS_ON signal of high potential to the power supply 60 .
  • the PCH 50 outputs the PS_ON signal of high potential to the power supply 60 in response to receive a system PW_OK signal of low potential to shut down the electronic system, to avoid other chips working in the abnormal voltage.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Direct Current Feeding And Distribution (AREA)

Abstract

A circuit protection system for an electronic system includes a platform control hub (PCH), a PCH power chip connected to the PCH, a basic input output system (BIOS), a control unit, and a power supply. The control unit determines the potential of a PW_OK signal from the PCH power chip to get the current state of the electronic system through the BIOS, thereby determining whether the current status of the PW_OK signal corresponds to a predetermined status of the PCH power chip which is defined in the current state of the electronic system. If the current status of the PW_OK signal does not correspond to the predetermined status, the control unit outputs a system PW_OK signal of low potential to disable the PCH power chip, and outputs an enable signal to the PCH which outputs a PS_ON signal of high potential to the power supply to shutdown the electronic system.

Description

This application is related to a pending U.S. patent application, with application Ser. No. 13/217,157, entitled “CIRCUIT PROTECTION SYSTEM AND METHOD”, and filed on Aug. 24, 2011, which is assigned to the same assignee as the present application.
BACKGROUND
1. Technical Field
The present disclosure relates to circuit protection systems, and particularly to a protection system and a protection method for a circuit utilizing a power chip.
2. Description of Related Art
In a circuit utilizing a power chip, the power chip pulls down the potential of a PW_OK signal output to the main chip when the voltage output by the power chip is excessive or insufficient, to protect the main chip and the power chip. However, there is an interval between receiving the low potential PW_OK signal and disabling the power chip. Since the power chip still works during the interval, the power chip could be damaged or destroyed. Thus, there is room for improvement in the art.
BRIEF DESCRIPTION OF THE DRAWINGS
Many aspects of the present disclosure can be better understood with reference to the following drawing(s). The components in the drawing(s) are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawing(s), like reference numerals designate corresponding parts throughout the several views.
FIG. 1 is a block diagram of an embodiment of a circuit protection system of the present disclosure.
FIG. 2 is a flowchart of an embodiment of a circuit protection method of the present disclosure.
 DETAILED DESCRIPTION
Referring to FIG. 1, an exemplary embodiment of a circuit protection system, which is applied to an electronic system, includes a central processing unit (CPU) 70, a first CPU power chip 10 for powering the CPU 70. A platform controller hub (PCH) 50, a second PCH power chip 20 for powering the PCH 50, a control unit 30, a basic input output system (BIOS) 40, and a power supply 60. The first CPU power chip 10, the second PCH power chip 20, the BIOS 40, and the PCH 50 are all connected to the control unit 30. The power supply 60 is coupled to the PCH 50. The CPU 70, the first CPU power chip 10, the PCH 50, the second PCH power chip 20, and the BIOS 40 are all elements of the electronic system.
The advanced configuration and power interface (ACPI) specification defines six states S0-S5 for an ACPI-compliant computer system. S0 is the working state. S1 is the standby state in which the CPU is disabled while other chips and buses are enabled. S2 is the power standby state in which the CPU and buses are disabled while other chips are enabled. S3 is the suspend to RAM state in which the main memory is powered for storing the content, while other devices are not powered. S4 is the suspend to disk state in which all content of the main memory is saved to hard disk drive. S5 is the shutdown state in which all devices are disabled.
The circuit protection system is ACPI compatible. To correspond to the ACPI specification, the current state of the system has to be stored in the BIOS 40. Hence, the current state of the circuit protection system can be obtained from the BIOS 40.
In this embodiment, the control unit 30 is a complex programmable logic device (CPLD). The control unit 30 detects the PW_OK signals output from the power chips, that is, the first CPU power chip 10 and the second PCH power chip 20, to determine whether the potential of the PW_OK signals output to the main chips, that is, the CPU 70 and the PCH 50, are low, such as logical 0. If any one of the potential of the PW_OK signals of the power chips is low, the control unit 30 gets the current state of the electronic system through the BIOS 40. Thereby, determining whether the status of the potential of the PW_OK signal output from the power chips, that is, the first CPU power chip 10 and the second PCH power chip 20, correspond to the predetermined status, which is defined in each of the current states of the electronic system.
In one embodiment, the potential of the PW_OK signal output from the CPU power chip 10 to the CPU 70, detected by the control unit 30, is low, and the current state of the electronic system obtained by the control unit 30 through the BIOS 20 is S1. Since the CPU 70 should be disabled in state S1 to correspond to the ACPI specification, the first CPU power chip 10 has to output a PW_OK signal of low potential to the CPU 70. Hence, the status of the potential of the PW_OK signal of the first CPU power chip 10 is considered to correspond to the predetermined status for the first CPU power chip 10, defined in the current state of the circuit protection system. In another embodiment, the potential of the PW_OK signal output from the second PCH power chip 20 to the PCH 50 is low, and the current state of the electronic system obtained by the control unit 30 through the BIOS 20 is S1. Since the PCH 50 should be enabled in state S1 to correspond to the ACPI specification, the second PCH power chip 20 has to output a PW_OK signal of high potential, such as logical 1, to the PCH 50. Hence, the status of the potential of the PW_OK signal of the second PCH power chip 20 is not considered to correspond to the predetermined status for the second PCH power chip 20, defined in the current state of the circuit protection system. When inconsistencies within the system cause the second PCH power chip 20 to output an incorrect PW_OK signal, for example, the voltage output by the second PCH power chip 20 is excessive or insufficient. The control unit 30 correspondingly outputs an enable signal of low potential to disable the second PCH power chip 20, and outputs a system PW_OK signal of low potential to the PCH 50. The PCH 50 outputs a PS_ON signal of high potential to the power supply 60 to shut down the electronic system in response to receiving the enable signal of low potential, to avoid further damage caused by excessive or insufficient voltage.
Referring to FIG. 2, the circuit protection method of the present disclosure is as follows. Depending on the embodiment, certain of the steps described may be removed, others may be added, and the sequence of steps may be altered. It is also to be understood that the description and the claims drawn to a method may include some indication in reference to certain steps. However, the indication used is only to be viewed for identification purposes and not as a suggestion as to an order for the steps.
In step S1, the control unit 30 determines whether the potential of the PW_OK signal output from at least one of the power chips 10 and 20 is low. If the potential of the PW_OK signal output by any one of the power chip 10/20 is low, step S2 is implemented; otherwise, step S1 is repeated.
In step S2, the correspondence between the current status of the potential of the PW_OK signal output by the power chip 10/20 and the predetermined status of the power chip 10/20 defined in the current state of the electronic system is determined. The control unit 30 gets the current state of the electronic system through the BIOS 40. Since the potential of the PW_OK signal output by the power chip 10/20 determined in step S1 is low, the corresponding main chip is disabled. If the current status of the PW_OK signal corresponds to the predetermined status of the PW_OK signal of the power chip 10/20 which defined in the current state of the electronic system, return to step S1; otherwise, step S3 is implemented.
In step S3, the control unit 30 outputs an enable signal to disable the power chip 10/20, and a system PW_OK signal of low potential to the PCH 50. In step S2, if the current status of the PW_OK signal of the power chip 10/20 does not correspond to the predetermined status of the power chip 10/20 defined in the current state of the electronic system, there should be problems because the power chip 10/20 outputs the PW_OK signal of low potential. For example, the voltage output by the power chip 10/20 is excessive or insufficient. Correspondingly, the control unit 30 outputs an enable signal of low potential to the power chip 10/20 and the system PW_OK signal of low potential to the PCH 50, thereby disabling the power chip 10/20 to avoid the damage caused by excessive or insufficient voltage.
In step S4, The PCH 50 outputs a PS_ON signal of high potential to the power supply 60. The PCH 50 outputs the PS_ON signal of high potential to the power supply 60 in response to receive a system PW_OK signal of low potential to shut down the electronic system, to avoid other chips working in the abnormal voltage.
While the disclosure has been described by way of example and in terms of preferred embodiment, it is to be understood that the disclosure is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims (9)

What is claimed is:
1. A circuit protection system for an electronic system, the circuit protection system comprising:
a control unit;
a platform control hub (PCH) connected to the control unit;
a PCH power chip connected to the control unit and the PCH to power the PCH;
a basic input output system (BIOS) connected to the control unit; and
a power supply connected to the PCH;
wherein the control unit determines the status of the potential of a PW_OK signal output from the PCH power chip, and gets the current state of the electronic system through the BIOS, thereby outputting an enable signal to disable the PCH power chip and outputting a system PW_OK signal to the PCH when the current status of the PW_OK signal of the PCH power chip does not correspond to a predetermined status for the PCH power chip defined in the current state of the electronic system, and the PCH outputs a PS_ON signal to the power supply to shut down the electronic system in response to receiving the system PW_OK signal.
2. The circuit protection system of claim 1, further comprising a main chip and a main power chip connected between the main chip and the control unit to power the main chip, wherein the control unit determines the status of the potential of the PW_OK signal output from the main power chip, and gets the current state of the electronic system through the BIOS, thereby outputting an enable signal to disable the power chip and outputting the system PW_OK signal to the PCH when the current status of the PW_OK signal of the power chip does not correspond to the predetermined status for the power chip defined in the current state of the electronic system, and the PCH outputs the PS_ON signal to the power supply to shut down the electronic system in response to receiving the system PW_OK signal.
3. The circuit protection system of claim 2, wherein the main chip is a central processing unit (CPU), and the power chip is a CPU power chip.
4. The circuit protection system of claim 1, wherein the control unit is a complex programmable logic device (CPLD).
5. The circuit protection system of claim 1, wherein the potential of the system PW_OK signal output by the control unit is low.
6. The circuit protection system of claim 1, wherein the potential of the PS_ON signal output by the PCH is high.
7. The circuit protection system of claim 1, wherein the circuit protection system is advanced configuration and power interface (ACPI) compatible.
8. A circuit protection method for an electronic system, the circuit protection method comprising:
utilizing a control unit to determine whether the potential of a PW_OK signal output from a platform control hub (PCH) power chip to a PCH is low;
determining whether the current status of the potential of the PW_OK signal of the PCH power chip corresponds to a predetermined status defined in each of the current states of the electronic system in response to the PW_OK signal of the PCH power chip being low;
outputting a system PW_OK signal of low potential to the PCH and an enable signal to disable the PCH power chip by the control unit in response to the current status of the potential of the PW_OK signal of the PCH power chip not corresponding to the predetermined status; and
outputting a PS_ON signal of high potential to a power supply to shut down the electronic system by the PCH in response to receiving the system PW_OK signal of low potential.
9. The circuit protection method of claim 8, wherein the control unit is a complex programmable logic device (CPLD).
US13/285,026 2011-05-30 2011-10-31 Circuit protection system and method Expired - Fee Related US8826056B2 (en)

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CN201110141786.5A CN102810840B (en) 2011-05-30 2011-05-30 Voltage protection system
CN201110141786 2011-05-30

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TW201443601A (en) * 2013-05-06 2014-11-16 Fames Technology Co Ltd Power control module of carrier
CN104699215A (en) * 2013-12-04 2015-06-10 鸿富锦精密电子(天津)有限公司 Power supply protection system and power supply protection method
US9626195B2 (en) * 2015-05-11 2017-04-18 Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. Booting system

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US8255988B2 (en) * 2007-03-28 2012-08-28 Microsoft Corporation Direct peripheral communication for restricted mode operation

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KR100603926B1 (en) * 1999-10-25 2006-07-24 삼성전자주식회사 Power supply control circuit and its control method for computer systems with various power management states
CN100504801C (en) * 2004-06-25 2009-06-24 联想(北京)有限公司 Method and device for detecting and diagnosing computer hardware failures

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US8255988B2 (en) * 2007-03-28 2012-08-28 Microsoft Corporation Direct peripheral communication for restricted mode operation

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