US7797581B2 - Device and method for testing motherboard - Google Patents
Device and method for testing motherboard Download PDFInfo
- Publication number
- US7797581B2 US7797581B2 US11/840,226 US84022607A US7797581B2 US 7797581 B2 US7797581 B2 US 7797581B2 US 84022607 A US84022607 A US 84022607A US 7797581 B2 US7797581 B2 US 7797581B2
- Authority
- US
- United States
- Prior art keywords
- testing
- test data
- motherboard
- server
- receiving device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
- G06F11/2733—Test interface between tester and unit under test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31705—Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits
Definitions
- the present invention relates to testing devices and testing methods, more particularly to a testing device and a testing method for testing a motherboard.
- a motherboard which includes a south bridge chip, a north bridge chip and buses and so on, is one of the most important components in a personal computer. Reliability and compatibility of the motherboard is very important.
- a manufacturer of motherboards must test reliability and compatibility of the motherboards before shipment.
- a motherboard is installed in a computer. After an operating system of the computer is loaded, the computer executes some testing programs in order to get testing results. However, if the motherboard has some problems after the computer is started up and prior to loading of the operating system, no test results are obtained. In this situation, the tester cannot clearly know what is wrong with the motherboard.
- a testing device for testing a motherboard which includes a server, a client terminal computer, a debug card, and a receiving device.
- the client terminal computer is connected to the server, for inquiring testing results.
- the debug card is attached to the motherboard, for getting test data.
- the receiving device connected to the debug card transmits the test data to the server via a network.
- a testing method for testing a motherboard includes the following steps: a debug card getting test data from the motherboard; sending the test data to a receiving device, the receiving device transmitting the test data to a server, the server collating and analyzing the test data; and a client terminal computer inquiring test results via the server.
- FIG. 1 is a block diagram of a testing device in accordance with an embodiment of the present invention
- FIG. 2 is another block diagram of the testing device shown in FIG. 1 , with more detail regarding a server and the addition of a client terminal computer;
- FIG. 3 is a flow chart of a testing method in accordance with an embodiment of the present invention.
- a testing device in accordance with a preferred embodiment of the present invention for testing a motherboard 10 includes a debug card 11 , a hard disk 12 , a receiving device 20 , a server 30 , and a scanner 50 .
- the debug card 11 is attached to the motherboard 10 and is connected to the receiving device 20 via, for example, a serial port.
- the hard disk 12 is coupled to the motherboard 10 .
- the receiving device 20 for example, an Nport, is connected to the scanner 50 via, for example, a PS/2 interface, and is connected to the server 30 via a network.
- BIOS Basic Input Output System
- POST power-on self tests
- the BIOS chip sends testing codes to the debug card 11 from the 80H address or other addresses.
- the debug card 11 also receives special testing codes that the programs in the Master Boot Record (MBR) of the hard disk 12 send. These special testing codes indicate a step in the test process. For example, when the MBR sends special testing code A055BB, it indicates that POST is over.
- the testing codes from the BIOS chip and the current special testing code from the MBR together compose test data. The composed test data are then transmitted to the receiving device 20 .
- the scanner 50 is provided to scan motherboard sequence numbers and operator identifying codes and so on.
- the receiving device 20 sends the testing codes from the BIOS chip, special current testing code from the MBR, and motherboard sequence numbers and so on from the scanner 50 , to the server 30 via the network.
- the server 30 includes a communication module 31 , a database 32 , and a user interface module 33 .
- the communication module 31 receives the testing information sent from the receiving device 20 and transmits the testing information to the database 32 .
- the database 32 stores the testing information.
- the user interface module 33 is an interface for receiving commands from web users and inquiring of the database 32 .
- the user interface module 33 also has other functions, for example, account management, setting administrator and guest accounts, and making statistic report forms and so on.
- a client terminal computer 60 communicates with the server 30 via the user interface module 33 .
- the testing method for testing the motherboard 10 includes the following steps:
- Step 1 When the computer is switched on, the BIOS chip runs POST, and then the BIOS chip sends testing codes to the debug card 11 from 80H address or other addresses.
- the debug card 11 also gets special testing codes sent by the MBR of the hard disk 12 . These special testing codes indicate a step in the test process.
- Step 2 The debug card 11 sends test data for a just completed step in the test process, the test data include the testing codes from the BIOS, and the special testing codes to the receiving device 20 via the serial port.
- the scanner 50 scans motherboard sequence numbers and so on. Then the receiving device 20 sends the testing codes, the special testing codes, and information from scanner 50 to the server 30 via the network.
- Step 3 The receiving device 20 sends the testing codes, the special testing codes, and the information from the scanner 50 to the communication module 31 .
- the communication module 31 collates the received data and sends the data to the database 32 of the server 30 for storing.
- Step 4 The client terminal computer 60 sends commands to the server 30 .
- the user interface module 33 of the server 30 sends inquiries to the database 32 .
- the database 32 returns answers to the queries to the user interface module 33 and then users can see the answers on a web site accessed by the client terminal computer 60 .
- the testing device can automatically collect test information before the operating system is loaded. If the motherboard 10 has some problems after the computer is started up and prior to loading of the operating system, testers can still get the testing information. Thus, testers could know why the motherboard 10 was wrong before the operating system is loaded.
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Debugging And Monitoring (AREA)
Abstract
Description
Claims (9)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2007102008224A CN101324860B (en) | 2007-06-14 | 2007-06-14 | Mainboard test system and test method |
CN200710200822.4 | 2007-06-14 | ||
CN200710200822 | 2007-06-14 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20080313503A1 US20080313503A1 (en) | 2008-12-18 |
US7797581B2 true US7797581B2 (en) | 2010-09-14 |
Family
ID=40133481
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/840,226 Expired - Fee Related US7797581B2 (en) | 2007-06-14 | 2007-08-17 | Device and method for testing motherboard |
Country Status (2)
Country | Link |
---|---|
US (1) | US7797581B2 (en) |
CN (1) | CN101324860B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130238942A1 (en) * | 2012-03-12 | 2013-09-12 | Hon Hai Precision Industry Co., Ltd. | Port test device for motherboards |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102455961A (en) * | 2010-10-29 | 2012-05-16 | 鸿富锦精密工业(深圳)有限公司 | System and method for managing and controlling mainboard testing process |
CN102478623B (en) * | 2010-11-22 | 2013-10-16 | 英业达股份有限公司 | Method for testing unit to be tested |
US9037911B2 (en) * | 2010-12-09 | 2015-05-19 | Advanced Micro Devices, Inc. | Debug state machines and methods of their operation |
CN102855166A (en) * | 2011-06-29 | 2013-01-02 | 鸿富锦精密工业(深圳)有限公司 | Mainboard testing system and method |
US20140053036A1 (en) * | 2012-08-15 | 2014-02-20 | Scott P. Nixon | Debugging multiple exclusive sequences using dsm context switches |
CN104133749A (en) * | 2014-07-23 | 2014-11-05 | 浪潮电子信息产业股份有限公司 | Verification method for HDD detecting failure and HDD out-of-order defect of server |
CN109144801A (en) * | 2018-08-27 | 2019-01-04 | 郑州云海信息技术有限公司 | It is a kind of to be directed to the test method of MOC card, device and equipment in server |
CN111341377A (en) * | 2018-12-19 | 2020-06-26 | 佛山市顺德区顺达电脑厂有限公司 | Test device capable of obtaining memory operation information and test method thereof |
TWI700580B (en) * | 2019-01-23 | 2020-08-01 | 神達電腦股份有限公司 | Automatic test system and automatic test method |
CN111143150A (en) * | 2019-12-27 | 2020-05-12 | 深圳市越疆科技有限公司 | Method and system for testing PCBA (printed circuit board assembly), testing equipment and micro-control unit |
CN111537862B (en) * | 2020-04-21 | 2023-03-31 | 青岛矽昌通信技术有限公司 | PCBA test method and system |
CN114490746B (en) * | 2021-12-23 | 2024-01-23 | 苏州浪潮智能科技有限公司 | Equipment testing method and device, equipment to be tested and storage medium |
CN118502553A (en) * | 2024-06-18 | 2024-08-16 | 百信信息技术有限公司 | Server main board structure and testing method |
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US6336195B1 (en) * | 1999-04-14 | 2002-01-01 | Compal Electronics, Inc. | Method for debugging keyboard basic input/output system (KB-BIOS) in a development notebook computing system |
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CN1241118C (en) * | 2002-09-20 | 2006-02-08 | 联想(北京)有限公司 | System and method for realizing automatic on/off test of computer |
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CN100412804C (en) * | 2005-06-03 | 2008-08-20 | 鸿富锦精密工业(深圳)有限公司 | Method and system for recognizing error codes of failure diagnosis card for main board |
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2007
- 2007-06-14 CN CN2007102008224A patent/CN101324860B/en not_active Expired - Fee Related
- 2007-08-17 US US11/840,226 patent/US7797581B2/en not_active Expired - Fee Related
Patent Citations (13)
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US6487610B2 (en) * | 1998-10-23 | 2002-11-26 | Intel Corporation | Direct processor access via an external multi-purpose interface |
US6263373B1 (en) * | 1998-12-04 | 2001-07-17 | International Business Machines Corporation | Data processing system and method for remotely controlling execution of a processor utilizing a test access port |
US6336195B1 (en) * | 1999-04-14 | 2002-01-01 | Compal Electronics, Inc. | Method for debugging keyboard basic input/output system (KB-BIOS) in a development notebook computing system |
US6892248B2 (en) * | 2001-02-21 | 2005-05-10 | International Business Machines Corporation | Method and apparatus for configuring a port on a legacy-free device for general I/O purposes or debugging purposes |
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US20060080078A1 (en) * | 2004-10-08 | 2006-04-13 | Jing-Rung Wang | Adaptive device for memory simulator |
US7634760B1 (en) * | 2005-05-23 | 2009-12-15 | Netapp, Inc. | System and method for remote execution of a debugging utility using a remote management module |
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US20070016827A1 (en) * | 2005-07-18 | 2007-01-18 | Dell Products L.P. | Systems and methods for providing remotely accessible in-system emulation and/or debugging |
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US20080133961A1 (en) * | 2006-12-01 | 2008-06-05 | Hon Hai Precision Industry Co., Ltd. | Debug card |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130238942A1 (en) * | 2012-03-12 | 2013-09-12 | Hon Hai Precision Industry Co., Ltd. | Port test device for motherboards |
Also Published As
Publication number | Publication date |
---|---|
CN101324860B (en) | 2013-08-28 |
CN101324860A (en) | 2008-12-17 |
US20080313503A1 (en) | 2008-12-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: HONG FU JIN PRECISION INDUSTRY (SHENZHEN) CO., LTD Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ZHU, GUANG-YU;CHAN, HOI;WANG, BO-TAO;AND OTHERS;REEL/FRAME:019707/0834;SIGNING DATES FROM 20070719 TO 20070725 Owner name: HON HAI PRECISION INDUSTRY CO., LTD., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ZHU, GUANG-YU;CHAN, HOI;WANG, BO-TAO;AND OTHERS;REEL/FRAME:019707/0834;SIGNING DATES FROM 20070719 TO 20070725 Owner name: HONG FU JIN PRECISION INDUSTRY (SHENZHEN) CO., LTD Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ZHU, GUANG-YU;CHAN, HOI;WANG, BO-TAO;AND OTHERS;SIGNING DATES FROM 20070719 TO 20070725;REEL/FRAME:019707/0834 Owner name: HON HAI PRECISION INDUSTRY CO., LTD., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ZHU, GUANG-YU;CHAN, HOI;WANG, BO-TAO;AND OTHERS;SIGNING DATES FROM 20070719 TO 20070725;REEL/FRAME:019707/0834 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
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FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.) |
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LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
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STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
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FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20180914 |