[go: up one dir, main page]

US7427796B2 - Semiconductor device and method of manufacturing a semiconductor device - Google Patents

Semiconductor device and method of manufacturing a semiconductor device Download PDF

Info

Publication number
US7427796B2
US7427796B2 US11/053,600 US5360005A US7427796B2 US 7427796 B2 US7427796 B2 US 7427796B2 US 5360005 A US5360005 A US 5360005A US 7427796 B2 US7427796 B2 US 7427796B2
Authority
US
United States
Prior art keywords
layer
silicide
gate electrode
semiconductor device
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related, expires
Application number
US11/053,600
Other versions
US20060063362A1 (en
Inventor
Akira Hokazono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HOKAZONO, AKIRA
Publication of US20060063362A1 publication Critical patent/US20060063362A1/en
Application granted granted Critical
Publication of US7427796B2 publication Critical patent/US7427796B2/en
Expired - Fee Related legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H10D30/0213—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation providing different silicide thicknesses on gate electrodes and on source regions or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H10D84/0137—Manufacturing their gate conductors the gate conductors being silicided
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0147—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • the present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
  • a silicide layer lower in specific resistance than polysilicon is often formed on the gate electrode.
  • the gate electrode and a source/drain diffusion layer are first formed on a semiconductor substrate; a metal layer is next deposited on the semiconductor substrate; and the semiconductor substrate is annealed.
  • thickness of the silicide layer usually depends on the thickness of the metal layer.
  • the gate electrode in the full silicide region is entirely silicided whereas the gate electrode in the non-full silicide region is partly silicided only in the top portion thereof.
  • the conventional technique locally made the full silicide MOSFET and the non-full silicide MOSFET in different regions on a common semiconductor substrate.
  • the silicide layer is formed to spread over the source and drain layers of the MOSFETs, the silicide layer on the source and drain layer of the full silicide MOSFET becomes thicker than that of the non-full silicide MOSFET. This may invite junction leakage.
  • a semiconductor device having transistors that include silicides different in thickness in their gate electrodes in a common substrate and can prevent junction leakage in their source and the drain.
  • a semiconductor device comprises a first transistor including: a first source layer and a first drain layer both formed in a surface of a semiconductor substrate; a first silicide layer formed on the first source layer and the first drain layer; a first gate electrode formed on a first gate insulating film, which is formed on the surface of the semiconductor substrate and has a second silicide layer; and a silicon nitride film formed on sidewalls of the first gate electrode;
  • a second transistor including: a second source layer and a second drain layer both formed in the surface of the semiconductor substrate; a third silicide layer formed on the second source layer and the second drain layer and equal in thickness to the first silicide layer; a second gate electrode formed on a second gate insulating film, which is formed on the surface of the semiconductor substrate and has a fourth silicide layer thinner in thickness than the second silicide layer.
  • a method of manufacturing a semiconductor device comprises forming a gate insulating film on a semiconductor substrate; forming a plurality of gate electrodes on the gate insulating film; forming a silicon nitride film on sidewalls of a first of the gate electrodes; forming a silicon oxide film on sidewalls of a second of the gate electrodes, the second gate electrode having no silicon nitride film on sidewalls thereof; depositing a metal layer on the plurality of gate electrodes and the semiconductor substrate; and siliciding at least the tops of the gate electrodes by annealing the semiconductor substrate.
  • FIG. 1A and FIG. 1B are cross-sectional views of transistors according to the first embodiment of the invention.
  • FIG. 2A is a graph showing the sheet resistance of the second silicide layer 20 a relative to the gate length Lg of the first transistor 101 ;
  • FIG. 2B is a graph showing the sheet resistance of the fourth silicide layer 20 b relative to the gate length Lg of the second transistor 102 ;
  • FIG. 3 is a graph showing the relation between the thickness of the silicon oxide layer 7 a and the resistance of the silicide film 20 a;
  • FIGS. 4A and 4B are cross-sectional views of the semiconductor device which show its manufacturing process according to the first embodiment of the invention.
  • FIGS. 5A and 5B are cross-sectional views showing the manufacturing process following FIGS. 4A and 4B ;
  • FIGS. 6A and 6B are cross-sectional views showing the manufacturing process following FIGS. 5A and 5B ;
  • FIGS. 7A and 7B are cross-sectional views showing the manufacturing process following FIGS. 6A and 6B ;
  • FIGS. 8A and 8B are cross-sectional views showing the manufacturing process following FIGS. 7A and 7B ;
  • FIGS. 9A and 9B are cross-sectional views showing the manufacturing process following FIGS. 8A and 8B ;
  • FIGS. 10A and 10B are cross-sectional views showing the manufacturing process following FIGS. 9A and 9B ;
  • FIGS. 11A and 11B are cross-sectional views showing the manufacturing process following FIGS. 10A and 10B ;
  • FIGS. 12A and 12B are cross-sectional views showing the manufacturing process following FIGS. 11A and 11B ;
  • FIGS. 13A and 13B are cross-sectional views showing the manufacturing process following FIGS. 12A and 12B ;
  • FIG. 14A and FIG. 14B are cross-sectional views of transistors according to the second embodiment of the invention.
  • FIGS. 15A and 15B are cross-sectional views of the semiconductor device which show its manufacturing process according to the second embodiment of the invention.
  • FIGS. 16A and 16B are cross-sectional views showing the manufacturing process following FIGS. 15A and 15B ;
  • FIG. 17 is a block diagram of a digital/analog mixed circuit including full silicide MOSFETs and non-full silicide MOSFETs on a common substrate.
  • the full silicide does not always means that the gate electrode is silicided by 100%, but contemplates that a part thereof may be doped polysilicon. For example, even when the silicide layer in a gate electrode reaches a gate insulating film, a part of the interface between the gate electrode and the gate insulating film may be non-silicided.
  • FIG. 1A is a cross-sectional view of a first transistor 101 in a full silicide region of a semiconductor device according to the first embodiment of the invention.
  • FIG. 1B is a cross-sectional view of a second transistor 102 in a non-full silicide region of the semiconductor device according to the first embodiment of the invention.
  • the first transistor 101 and the second transistor 102 are formed on a common semiconductor chip.
  • the first transistor 101 includes a first source layer 13 a , a first drain layer 23 a , a first silicide layer 14 a , a second silicide layer 20 a , a first gate electrode 6 a , a silicon oxide film 7 a , a silicon nitride film 9 a and a silicon oxide film 12 a .
  • the second transistor 102 includes a second source layer 13 b , a second drain layer 23 b , a third silicide layer 14 b , a fourth silicide layer 20 b , a second gate electrode 6 b , a silicon oxide film 7 b and a silicon oxide film 12 b.
  • the first source layer 13 a and the first drain layer 23 a are formed in a well diffusion layer 3 a formed on the surface of a p-type or n-type silicon substrate 10 .
  • the first source layer 13 a and the first drain layer 23 a may be either of p-type layers or of n-type layers.
  • an extension layer 8 a is formed near a channel region 4 a between the first source layer 13 a and the first drain layer 23 a .
  • the extension layer 8 a is of the same conduction type as that of the first source layer 13 a and the first drain layer 23 a.
  • the first silicide layer 14 a is formed on the first source layer 13 a and the first drain layer 23 a .
  • the first silicide layer 14 a may be made of nickel silicide, for example, and its thickness is D 1 . Considering that the depth of the first source layer 13 a and the first drain layer 23 a is equal to or less than 80 nm, the thickness D 1 is preset equal to or less than 30 nm to prevent the junction leak.
  • a gate insulating film 5 a is formed on the surface of the channel region 4 a .
  • the gate electrode 6 a is formed on the gate insulating film 5 a and thereby isolated from the channel region 4 a .
  • the gate electrode 6 a may be made of nickel silicide, for example.
  • the gate electrode 6 a is preferably silicided entirely. At least the thickness D 2 of the second silicide layer 20 a is thicker than the thickness D 3 of the second silicide layer 20 b in the second transistor 102 . Therefore, the first transistor 101 is lower in gate resistance than the second transistor 102 . As a result, the first transistor 101 is enhanced in switching speed.
  • the first transistor 101 is used in an analog circuit region required to be low in gate resistance, logic circuit region required to be high in switching speed, or SRAM region.
  • the silicon oxide film 7 a is formed on the sidewall of the gate electrode 6 a .
  • the silicon nitride film 9 a is formed on the sidewall of the gate electrode 6 a to lie adjacent to the silicon oxide film 7 a .
  • the silicon oxide film 12 a is formed on the sidewall of the gate electrode 6 a to cover the silicon nitride film 9 a.
  • the silicon nitride film 9 a formed on the sidewall of the gate electrode 6 a promotes silicidation of the gate electrode 6 a . Conditions of full silicidation of the gate electrode 6 a will be explained later.
  • the second source layer 13 b and the second drain layer 23 b are formed in a well diffusion layer 3 b formed on the surface of the silicon substrate 10 .
  • the second source layer 13 b and the second drain layer 23 b may be either p-type layers or n-type layers.
  • An extension layer 8 b is formed near a channel region 4 b .
  • the extension layer 8 b is of the same conduction type as that of the second source layer 13 b and the second drain layer 23 b.
  • the third silicide layer 14 b is formed on the second source layer 13 b and the second drain layer 23 b .
  • the third silicide layer 14 b may be made of nickel silicide, for example. Thickness of the third silicide layer 14 b is D 1 equally to the thickness of the first silicide layer 14 a.
  • a gate insulating film 5 b is formed on the surface of the channel region 4 b .
  • the gate electrode 6 b is formed on the gate insulating film 5 b and thereby isolated from the channel region 4 b .
  • An upper portion of the gate electrode 6 b , the fourth silicide layer 20 b is formed.
  • the fourth silicide layer 20 b may be made of nickel silicide, for example.
  • the lower part of the gate electrode 6 b below the fourth silicide layer 20 b is made of doped polysilicon.
  • the thickness D 3 of the fourth silicide layer 20 b is thinner than the thickness D 2 of the second silicide layer 20 b Since the fourth silicide layer 20 b does not reach the gate the gate insulating film 5 b , relatively high reliability of the gate insulating film 5 b can be maintained.
  • the second transistor 102 is used in a DRAM required to be highly reliable, or in a device directly incorporating an existing circuit region.
  • the silicon oxide film 7 b is formed on the sidewall of the gate electrode 6 b . Furthermore, the silicon oxide film 12 b is formed on the sidewall of the gate electrode 6 a to cover the silicon oxide film 7 b . Since the second transistor 102 does includes no silicon nitride film on the sidewall of the gate electrode 6 b , the upper part alone of the gate electrode 6 b is silicided.
  • FIG. 2A is a graph showing the sheet resistance of the second silicide layer 20 a relative to the gate length Lg of the first transistor 101 .
  • FIG. 2B is a graph showing the sheet resistance of the fourth silicide layer 20 b relative to the gate length Lg of the second transistor 102 .
  • the second silicide layer 20 a and the fourth silicide layer 20 b are approximately equal in sheet resistance.
  • the sheet resistance of the second silicide layer 20 a begins to lower. This is because, in case the gate length Lg of the gate electrode 6 a is short, the silicon nitride film 9 a on the sidewall of the gate electrode 6 a promotes silicidation of the gate electrode 6 a and the thickness of the second silicide layer 20 a increases accordingly.
  • this is called “reverse narrow line effect”.
  • thickness of the silicide films 20 a and 20 b depends upon a thickness of a metal layer deposited upon the gate electrodes 6 a and 6 b in order to form the silicide films 20 a and 20 b .
  • the gate length Lg decreases to or below 50 nm, silicidation from the sidewall portion of the gate electrode 6 a becomes salient. Therefore, even when the sputtering thickness of the metal layer (for example, thickness of a nickel layer) is constant, the silicon nitride film 9 a formed on the sidewall of the gate electrode 6 a may change the thickness of the silicide film 20 a .
  • the silicon nitride film does not exist on the gate electrode 6 b . Therefore, the reverse narrow line effect does not occur in the second transistor 102 as shown in FIG. 2B .
  • the gate electrode 6 a is entirely silicided (full silicidation).
  • the gate length Lg of the gate electrode 6 a is preferably equal to or less than 50 nm to form the second silicide layer 20 a thicker than the fourth silicide layer 20 b . Further, for full silicidation of the gate electrode 6 a , the gate length of the gate electrode 6 a is preferably equal to or less than 20 nm.
  • FIG. 3 is a graph showing the relation between the thickness of the silicon oxide layer 7 a and the resistance of the silicide film 20 a .
  • the gate length Lg is 20 nm.
  • Thickness of the silicon oxide film 7 a is the thickness formed on the sidewall of the gate electrode 6 a and the thickness of near the interface between the gate electrode 6 a and the gate insulating film 5 a.
  • the silicon oxide film 7 a intervenes.
  • the silicon oxide film 7 a is formed to prevent concentration of the electric field to the end portion of the gate insulating film 5 a , i.e. to enhance the reliability of the fist transistor 101 .
  • the silicon oxide film 7 a is excessively thick, distance between the gate electrode 6 a and the silicon nitride film 9 a increases, and the reverse narrow line effect does not take place.
  • the thickness of the silicon oxide film 7 a is larger than 28 nm, resistance of the silicide film 20 a is relatively high. This means that the reverse narrow line effect has not occurred. As the thickness of the silicon oxide film 7 a decreases to or below 28 nm, the reverse narrow line effect occurs, and the resistance of the silicide film 20 a lowers. When the thickness of the silicon oxide film 7 a decreases to or below 10 nm approximately, resistance of the silicide film 20 a stabilizes in a low level. This means that the gate electrode 6 a has been fully silicided.
  • the thickness of the silicon oxide film 7 a is preferably equal to or smaller than 20 nm to bring about the reverse narrow line effect. Furthermore, to fully silicide the gate electrode 6 a , thickness of the silicon oxide film 7 a is preferably equal to or less than 10 nm approximately.
  • the thickness of the silicon nitride film more than 8 nm is required.
  • the first embodiment need not deposit a thick metal layer on the transistor in the full silicide region, it has silicide layers equal in thickness on the source and drain layers in both full silicide and non-full silicide regions. Therefore, the junction leak in the source and drain layers can be prevented. Furthermore, the first embodiment has silicide layers different in thickness on the gate electrodes in the full silicide region and the non-full silicide region. Therefore, it can form both the full silicide MOSFET enhanced in switching speed and the non-full silicide MOSFET having high reliability on the common substrate.
  • the first embodiment need not deposit metal layers on the full silicide region and the non-full silicide region in different manufacturing steps unlike the conventional technique, and needs no step of removing a mask, which is sequent to deposition of a metal layer. Therefore, the first embodiment can make the manufacturing process easier and can enhance the performance of the transistors.
  • FIGS. 4A through 13B are cross-sectional views of the semiconductor device according to the first embodiment of the invention, which show a flow of its manufacturing process.
  • FIGS. 4A , 5 A, 6 A, 7 A, 8 A, 9 A, 10 A, 11 A, 12 A and 13 A are cross-sectional views of the full silicide region.
  • FIGS. 4B , 5 B, 6 B, 7 B, 8 B, 9 B, 10 B, 11 B, 12 B and 13 B are cross-sectional views of the non-full silicide region.
  • a 200 ⁇ 350 nm thick Shallow Trench Isolation is first formed in a p-type or n-type silicon substrate 10 by a device-isolating technique. Thereafter, a silicon oxide film (not shown), equal to or thinner than 20 nm, is formed on the surface of the silicon substrate 10 .
  • STI Shallow Trench Isolation
  • impurities and activating RTA follow.
  • phosphorus is implanted by ion implantation under the condition of concentration 3.0*13 cm ⁇ 2 and energy 500 keV.
  • boron is implanted by ion implantation under the condition of concentration 1.5*13 cm ⁇ 2 and energy 10 keV.
  • boron is injected by impurity implantation under the condition of concentration 2.0*13 cm ⁇ 2 and energy 260 keV.
  • arsenic is injected by ion injection under the condition of concentration 1.0*13 cm ⁇ 2 and energy 80 keV. Thereafter, the previously formed silicon oxide film (not shown) is removed.
  • gate insulating films 5 a and 5 b are formed by LPCVD (Low Pressure Chemical Vapor Deposition).
  • LPCVD Low Pressure Chemical Vapor Deposition
  • polysilicon or polysilicon germanium is deposited to a thickness of 50 ⁇ 200 nm, followed by photolithography, X ray lithography or electron beam lithography for patterning of 10 ⁇ 150 nm gate length.
  • polysilicon or polysilicon germanium is partly removed by RIE (Reactive Ion Etching). Through these steps, the gate electrodes 6 a and 6 b having a gate length Lg equal to or less than 50 nm are obtained.
  • the gate insulating films 5 a and 5 b may be any of silicon oxide films (SiO 2 ), silicon oxide nitride films (SiON), silicon nitride films (SiN) and high dielectric films (such as Ta 2 O 3 ).
  • silicon oxide films are formed on sidewalls of the gate electrodes 6 a and 6 b by thermal oxidation. Thereafter, a silicon oxide film is deposited by LPCVD. Further through an etch-back process by RIE, silicon oxide films 7 a and 7 b of a thickness equal to or less than 10 nm are obtained. The silicon oxide films 7 a and 7 b are used as offset spacers upon forming the extension layers 8 a and 8 b.
  • the extension layers 8 a and 8 b are formed.
  • arsenic is implanted by ion implantation under the condition of concentration from 5.0*10 14 cm ⁇ 2 to 1.5*10 15 cm ⁇ 2 and energy 1 ⁇ 5 keV.
  • BF 2 is injected by ion injection under the condition of concentration from 5.0*10 14 cm ⁇ 2 to 1.5*10 15 cm ⁇ 2 and energy 1 ⁇ 3 keV.
  • the extension layers 8 a and 8 b are formed in self-alignment via the silicon oxide films 7 a and 7 b as offset spacers.
  • a silicon nitride film 30 is next deposited.
  • the silicon nitride film 30 is processed by anisotropic etching by RIE to retain silicon nitride films 9 a and 9 b on sidewalls of the gate electrodes 6 a and 6 b.
  • a TEOS film 40 is next deposited, and photo resist 11 is coated. Subsequently, the photo resist 11 is removed only from the non-full silicide region while retaining it in the full silicide region for patterning.
  • the TEOS film 40 in the non-full silicide region is removed by etching, and the resist is removed thereafter.
  • the silicon nitride film 9 b in the non-full silicide region is removed by etching.
  • etching of the silicon nitride film 9 b is attained by exposing the silicon nitride film 9 b to hot phosphoric acid solution heated to 160° C.
  • the TEOS film 40 is next removed by dilute fluoric acid.
  • the silicon nitride film 9 a is retained on the sidewall of the gate electrode 6 a in the full silicide region whereas the silicon nitride film 9 b is removed from the sidewall of the gate electrode 6 b in the non-full silicide region.
  • silicon oxide films 12 a and 12 b are next formed additionally on sidewalls of the gate electrodes 6 a and 6 b .
  • the silicon oxide films 12 a and 12 b may have a double-layered structure. In the full silicide region, the silicon oxide films 12 a and 12 b cover the silicon nitride film 9 a.
  • the silicon oxide films 12 a and 12 b may be a single-layered TEOS layer. Further, the silicon oxide films 12 a and 12 b may be a double-layered structure. For example, the silicon oxide films 12 a and 12 b may have TEOS as liner films and have silicon nitride films outside the liner films. Alternatively, the silicon oxide films 12 a and 12 b may have a triple-layered structure. For example, the silicon oxide films 12 a and 12 b may have TEOS as liner films, silicon nitride films outside the liner films, and silicon oxide films outside the silicon nitride films. Alternatively, the silicon oxide films 12 a and 12 b may have a structure including four or more layers. Thus, the silicon oxide films 12 a and 12 b may be any desired films including silicon oxide films as their base layers.
  • the first source layers 13 a , 23 a and the second drain layers 13 b , 23 b are next formed. These source and drain layers 13 a , 23 a , 13 b and 23 b are next activated by RTA.
  • a nickel layer is formed uniformly on the surface of the silicon substrate 10 .
  • RTA 400 ⁇ 500° C. for silicidation is carried out.
  • surfaces of the source and drain layers 13 a , 23 a , 13 b , 23 b and surfaces of the gate electrodes 6 a , 6 b are silicided.
  • the substrate is exposed to a mixed solution of sulfuric acid and hydrogen peroxide solution to remove nickel not having reacted.
  • a step of depositing a titanium nitride (TiN) film may be added after the sputtering of the nickel layer.
  • a two-step annealing process may be carried out, which first carries out low temperature RTA of 250 ⁇ 400° C., next exposes the substrate to the mixed solution of sulfuric acid and hydrogen peroxide solution, and thereafter again carries out RTA of 400 ⁇ 500° C. to lower the sheet resistance.
  • the first to fourth silicide layers 14 a , 14 b , 20 a and 20 b are obtained.
  • the second silicide layer 20 a in the gate electrode 6 a became thick because of the reverse narrow line effect.
  • the first transistor 101 becomes a full silicide MOSFET.
  • the 1 ⁇ 10 nm thick silicon oxide film 7 a intervenes between the gate electrode 6 a and the silicon nitride film 9 a , it is thin as shown in FIG. 3 and does not function to prevent the reverse narrow line effect.
  • the fourth silicide layer 20 b in the gate electrode 6 b is deposited relatively thin.
  • the second transistor 102 becomes a non-full silicide MOSFET.
  • silicon Before the step of silicidation, silicon may be epitaxially grown on the source and drain layers 13 a , 23 a , 13 b and 23 b .
  • silicon germanium may be epitaxially grown on the source and drain layers 13 a , 23 a , 13 b and 23 b.
  • a protection film (not shown) is deposited to protect the first and second silicide layers 14 a , 14 b .
  • an inter-layer film (not shown) is deposited on the protection film.
  • the protection film protects the first and second silicide layers 14 a , 14 b , and prevents junction leak that otherwise occurs due to excavation of the substrate by RIE for the source and drain layers 13 a , 23 a , 13 b and 23 b . Therefore, the protection film is made of a material having higher selectivity than the inter-layer film.
  • Ti titanium
  • TiN titanium nitride
  • W tungsten
  • the manufacturing method according to the instant embodiment can easily manufacture a semiconductor device having silicide layers equal in thickness on the source and drain layers in both the full silicide region and the non-full silicide region and having silicide layers equal in thickness on the gate electrodes in both the full silicide region and the non-full silicide region on a common substrate.
  • a TEOS film is deposited. After that, the TEOS film is removed only from the non-full silicide region by photolithography and RIE or wet etching. Then, under the existence of the TEOS film retained in the full silicide region as a mask, the silicon nitride film 30 is entirely removed from the non-full silicide region by etching using hot phosphoric acid solution heated to 160° C.
  • the non-full silicide region is covered by photo resist, the TEOS film is removed by treatment using fluoric acid, and the silicon nitride film 30 in the full silicide region is locally removed by anisotropic etching. As a result, the configuration shown in FIGS. 11A and 11B can be obtained.
  • FIG. 14A is a cross-sectional view of the first transistor 101 in the full silicide region of a semiconductor device according to the second embodiment of the invention.
  • FIG. 14B is a cross-sectional view of the second transistor 102 in the non-full silicide region of the semiconductor device according to the second embodiment.
  • the second embodiment is different from the first embodiment in the use of a silicon nitride film 15 a as an offset spacer.
  • the first embodiment includes the silicon oxide film 7 a as the offset spacer, and includes the silicon nitride film 9 a to cover the silicon oxide film 7 a .
  • the offset spacer itself serves as the silicon nitride film 15 a , the silicon oxide film 7 a need not be formed.
  • the silicon nitride film 15 a may be formed on the sidewall of the gate electrode 6 a in direct contact therewith, or via a natural oxide film (not shown) that is usually formed on the surface of the gate electrode 6 a.
  • the silicon nitride film 15 a is formed only on the gate electrode 6 a in the full silicide region. Therefore, the second silicide layer 20 a is formed thicker than the fourth silicide layer 20 b . As a result, the second embodiment assures the same effects as those of the first embodiment.
  • FIGS. 15A through 16B are cross-sectional views of the semiconductor device according to the second embodiment, which show a flow of its manufacturing method.
  • FIGS. 15A and 16A are cross-sectional views of the full silicide region.
  • FIGS. 15B and 16B are cross-sectional views of the non-full silicide region.
  • the gate electrodes 6 a and 6 b are formed by the method shown in FIGS. 4A and 4B .
  • the silicon nitride films 15 a and 15 b are next formed on sidewalls of the gate electrodes 6 a ad 6 b .
  • the silicon nitride films 15 a and 15 b function as offset spacers when the extension layers 8 a and 8 b are formed.
  • the TEOS film 40 is deposited on the silicon substrate 10 . There follow photolithography and RIE or wet etching to retain the TEOS film 40 in the full silicide region and expose the non-full silicide region.
  • the silicon nitride film 15 b is exposed to hot phosphoric acid solution heated to 160° C. to remove it. Further, the TEOS film 40 is removed also from the full silicide region. As such, as shown in FIGS. 16A and 16B , the silicon nitride can be formed on the sidewall of the gate electrode 6 a in the full silicide region.
  • the semiconductor device shown in FIGS. 14A ad 14 B can be obtained.
  • the manufacturing method of the semiconductor device according to the second embodiment assures the same effects as those of the manufacturing method of the semiconductor device according to the first embodiment.
  • the manufacturing method of the semiconductor device according to the second embodiment can be modified as well similarly to the first embodiment. That is, after the material of the silicon nitride films 15 a and 15 b are deposited, a TEOS film is deposited. Thereafter, the TEOS film is removed only from the non-full silicide region by photolithography and RIE or wet etching. Under the existence of the TEOS film retained in the full silicide region as a mask, the silicon nitride film is entirely removed from the non-full silicide region by etching using hot phosphoric acid solution heated to 160° C.
  • the non-full silicide region is covered with photo resist, the TEOS film is removed by treatment using fluoric acid, and the silicon nitride film in the full silicide region is partly removed by anisotropic etching by RIE. As such, the configuration shown in FIGS. 15A and 15B can be obtained.
  • FIG. 17 is a block diagram of a digital/analog mixed circuit including full silicide MOSFETs and non-full silicide MOSFETs on a common substrate.
  • full silicide MOSFETs are formed in the analog circuit region required to be low in gate resistance, logic circuit region, and SRAM region required to be high in switching speed.
  • non-full silicide MOSFETs are formed in the DRAM region requiring a highly reliable gate insulating film, or in a region directly incorporating an existing circuit.
  • the first and second embodiments heretofore explained have been directed to semiconductor devices including transistors of full silicide or non-full silicide gate electrodes on a common substrate.
  • transistors of full silicide or non-full silicide gate electrodes on a common substrate.
  • transistors having silicide layers simply different in thickness on a common substrate according to the teachings of the present invention, even without siliciding the entirety of the gate electrodes.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor device according to an embodiment of the present invention comprises a first transistor including: a first source layer and a first drain layer both formed in one surface of a semiconductor substrate; a first silicide layer formed on the first source layer and the first drain layer; a first gate electrode formed on a first gate insulating film formed on the surface of the semiconductor substrate and having a second silicide layer; and a silicon nitride film formed on the sidewall of the first gate electrode; a second transistor including: a second source layer and a second drain layer both formed in the surface of the semiconductor substrate; a third silicide layer formed on the second source layer and the second drain layer and equal in thickness to the first silicide layer; a second gate electrode formed on a second gate insulating film formed on the surface of the semiconductor substrate and having a fourth silicide layer thinner in thickness than the second silicide layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2004-273849, filed on Sep. 21, 2004, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
2. Background Art
To enhance the switching speed of semiconductor devices, a silicide layer lower in specific resistance than polysilicon is often formed on the gate electrode. To form the silicide layer On the gate electrode, the gate electrode and a source/drain diffusion layer are first formed on a semiconductor substrate; a metal layer is next deposited on the semiconductor substrate; and the semiconductor substrate is annealed. In this process, thickness of the silicide layer usually depends on the thickness of the metal layer.
There is a recent proposal to form on a common semiconductor substrate both a MOSFET in which the gate electrode is entirely silicided (hereafter called a full silicide MOSFET) and a MOSFET in which the upper part of the gate electrode is locally silicided (hereafter called a non-full silicide MOSFET). Heretofore, a process using photolithography has been used to locally retain a silicon oxide film or other mask material in a desired region such that a relatively thick metal layer deposits in the region for the full silicide MOSFET (hereafter called a full silicide region) while a relatively thin metal layer deposits in the region for the non-full silicide MOSFET (hereafter called a non-full silicide region). In this process, the gate electrode in the full silicide region is entirely silicided whereas the gate electrode in the non-full silicide region is partly silicided only in the top portion thereof. In this manner, the conventional technique locally made the full silicide MOSFET and the non-full silicide MOSFET in different regions on a common semiconductor substrate.
However, removal of the mask material after deposition of the metal layers invites the problem of undesirable etching of sidewall protection films of the gate electrodes and the silicide layer.
Furthermore, since the silicide layer is formed to spread over the source and drain layers of the MOSFETs, the silicide layer on the source and drain layer of the full silicide MOSFET becomes thicker than that of the non-full silicide MOSFET. This may invite junction leakage.
It might be possible to use a process of forming a silicide by exposing the gate electrodes alone. This process, however, cannot form a silicide on the source and drain layer (see Kedzierski et al., “Issues in NiSi-gated FDSOI device integration”, IEDM Tech. Dig., 2003, pp. 441-444).
To overcome these problems, here is provided a semiconductor device having transistors that include silicides different in thickness in their gate electrodes in a common substrate and can prevent junction leakage in their source and the drain.
SUMMARY OF THE INVENTION
A semiconductor device according to an embodiment of the present invention comprises a first transistor including: a first source layer and a first drain layer both formed in a surface of a semiconductor substrate; a first silicide layer formed on the first source layer and the first drain layer; a first gate electrode formed on a first gate insulating film, which is formed on the surface of the semiconductor substrate and has a second silicide layer; and a silicon nitride film formed on sidewalls of the first gate electrode;
a second transistor including: a second source layer and a second drain layer both formed in the surface of the semiconductor substrate; a third silicide layer formed on the second source layer and the second drain layer and equal in thickness to the first silicide layer; a second gate electrode formed on a second gate insulating film, which is formed on the surface of the semiconductor substrate and has a fourth silicide layer thinner in thickness than the second silicide layer.
A method of manufacturing a semiconductor device according to an embodiment of the present invention, comprises forming a gate insulating film on a semiconductor substrate; forming a plurality of gate electrodes on the gate insulating film; forming a silicon nitride film on sidewalls of a first of the gate electrodes; forming a silicon oxide film on sidewalls of a second of the gate electrodes, the second gate electrode having no silicon nitride film on sidewalls thereof; depositing a metal layer on the plurality of gate electrodes and the semiconductor substrate; and siliciding at least the tops of the gate electrodes by annealing the semiconductor substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A and FIG. 1B are cross-sectional views of transistors according to the first embodiment of the invention;
FIG. 2A is a graph showing the sheet resistance of the second silicide layer 20 a relative to the gate length Lg of the first transistor 101;
FIG. 2B is a graph showing the sheet resistance of the fourth silicide layer 20 b relative to the gate length Lg of the second transistor 102;
FIG. 3 is a graph showing the relation between the thickness of the silicon oxide layer 7 a and the resistance of the silicide film 20 a;
FIGS. 4A and 4B are cross-sectional views of the semiconductor device which show its manufacturing process according to the first embodiment of the invention;
FIGS. 5A and 5B are cross-sectional views showing the manufacturing process following FIGS. 4A and 4B;
FIGS. 6A and 6B are cross-sectional views showing the manufacturing process following FIGS. 5A and 5B;
FIGS. 7A and 7B are cross-sectional views showing the manufacturing process following FIGS. 6A and 6B;
FIGS. 8A and 8B are cross-sectional views showing the manufacturing process following FIGS. 7A and 7B;
FIGS. 9A and 9B are cross-sectional views showing the manufacturing process following FIGS. 8A and 8B;
FIGS. 10A and 10B are cross-sectional views showing the manufacturing process following FIGS. 9A and 9B;
FIGS. 11A and 11B are cross-sectional views showing the manufacturing process following FIGS. 10A and 10B;
FIGS. 12A and 12B are cross-sectional views showing the manufacturing process following FIGS. 11A and 11B;
FIGS. 13A and 13B are cross-sectional views showing the manufacturing process following FIGS. 12A and 12B;
FIG. 14A and FIG. 14B are cross-sectional views of transistors according to the second embodiment of the invention;
FIGS. 15A and 15B are cross-sectional views of the semiconductor device which show its manufacturing process according to the second embodiment of the invention;
FIGS. 16A and 16B are cross-sectional views showing the manufacturing process following FIGS. 15A and 15B; and
FIG. 17 is a block diagram of a digital/analog mixed circuit including full silicide MOSFETs and non-full silicide MOSFETs on a common substrate.
 DETAILED DESCRIPTION OF THE INVENTION
Some embodiments of the present invention will now be explained below with reference to the drawings. The embodiments, however, should not be construed to limit the invention in any ways and modes. In the embodiments explained below, the full silicide does not always means that the gate electrode is silicided by 100%, but contemplates that a part thereof may be doped polysilicon. For example, even when the silicide layer in a gate electrode reaches a gate insulating film, a part of the interface between the gate electrode and the gate insulating film may be non-silicided.
First Embodiment
FIG. 1A is a cross-sectional view of a first transistor 101 in a full silicide region of a semiconductor device according to the first embodiment of the invention. FIG. 1B is a cross-sectional view of a second transistor 102 in a non-full silicide region of the semiconductor device according to the first embodiment of the invention. The first transistor 101 and the second transistor 102 are formed on a common semiconductor chip.
The first transistor 101 includes a first source layer 13 a, a first drain layer 23 a, a first silicide layer 14 a, a second silicide layer 20 a, a first gate electrode 6 a, a silicon oxide film 7 a, a silicon nitride film 9 a and a silicon oxide film 12 a. The second transistor 102 includes a second source layer 13 b, a second drain layer 23 b, a third silicide layer 14 b, a fourth silicide layer 20 b, a second gate electrode 6 b, a silicon oxide film 7 b and a silicon oxide film 12 b.
In the first transistor 101, the first source layer 13 a and the first drain layer 23 a are formed in a well diffusion layer 3 a formed on the surface of a p-type or n-type silicon substrate 10. The first source layer 13 a and the first drain layer 23 a may be either of p-type layers or of n-type layers. To prevent a short-channel effect, an extension layer 8 a is formed near a channel region 4 a between the first source layer 13 a and the first drain layer 23 a. The extension layer 8 a is of the same conduction type as that of the first source layer 13 a and the first drain layer 23 a.
The first silicide layer 14 a is formed on the first source layer 13 a and the first drain layer 23 a. The first silicide layer 14 a may be made of nickel silicide, for example, and its thickness is D1. Considering that the depth of the first source layer 13 a and the first drain layer 23 a is equal to or less than 80 nm, the thickness D1 is preset equal to or less than 30 nm to prevent the junction leak.
A gate insulating film 5 a is formed on the surface of the channel region 4 a. The gate electrode 6 a is formed on the gate insulating film 5 a and thereby isolated from the channel region 4 a. The gate electrode 6 a may be made of nickel silicide, for example. The gate electrode 6 a is preferably silicided entirely. At least the thickness D2 of the second silicide layer 20 a is thicker than the thickness D3 of the second silicide layer 20 b in the second transistor 102. Therefore, the first transistor 101 is lower in gate resistance than the second transistor 102. As a result, the first transistor 101 is enhanced in switching speed. Typically, the first transistor 101 is used in an analog circuit region required to be low in gate resistance, logic circuit region required to be high in switching speed, or SRAM region.
The silicon oxide film 7 a is formed on the sidewall of the gate electrode 6 a. The silicon nitride film 9 a is formed on the sidewall of the gate electrode 6 a to lie adjacent to the silicon oxide film 7 a. The silicon oxide film 12 a is formed on the sidewall of the gate electrode 6a to cover the silicon nitride film 9 a.
The silicon nitride film 9 a formed on the sidewall of the gate electrode 6 a promotes silicidation of the gate electrode 6 a. Conditions of full silicidation of the gate electrode 6 a will be explained later.
In the second transistor 102, the second source layer 13 b and the second drain layer 23 b are formed in a well diffusion layer 3 b formed on the surface of the silicon substrate 10. The second source layer 13 b and the second drain layer 23 b may be either p-type layers or n-type layers. An extension layer 8 b is formed near a channel region 4 b. The extension layer 8 b is of the same conduction type as that of the second source layer 13 b and the second drain layer 23 b.
The third silicide layer 14 b is formed on the second source layer 13 b and the second drain layer 23 b. The third silicide layer 14 b may be made of nickel silicide, for example. Thickness of the third silicide layer 14 b is D1 equally to the thickness of the first silicide layer 14 a.
A gate insulating film 5 b is formed on the surface of the channel region 4 b. The gate electrode 6 b is formed on the gate insulating film 5 b and thereby isolated from the channel region 4 b. An upper portion of the gate electrode 6 b, the fourth silicide layer 20 b is formed. The fourth silicide layer 20 b may be made of nickel silicide, for example. The lower part of the gate electrode 6 b below the fourth silicide layer 20 b is made of doped polysilicon. As already explained, the thickness D3 of the fourth silicide layer 20 b is thinner than the thickness D2 of the second silicide layer 20 b Since the fourth silicide layer 20 b does not reach the gate the gate insulating film 5 b, relatively high reliability of the gate insulating film 5 b can be maintained. Typically, the second transistor 102 is used in a DRAM required to be highly reliable, or in a device directly incorporating an existing circuit region.
The silicon oxide film 7 b is formed on the sidewall of the gate electrode 6 b. Furthermore, the silicon oxide film 12 b is formed on the sidewall of the gate electrode 6 a to cover the silicon oxide film 7 b. Since the second transistor 102 does includes no silicon nitride film on the sidewall of the gate electrode 6 b, the upper part alone of the gate electrode 6 b is silicided.
FIG. 2A is a graph showing the sheet resistance of the second silicide layer 20 a relative to the gate length Lg of the first transistor 101. FIG. 2B is a graph showing the sheet resistance of the fourth silicide layer 20 b relative to the gate length Lg of the second transistor 102.
In case the gate length Lg is larger than 50 nm, the second silicide layer 20 a and the fourth silicide layer 20 b are approximately equal in sheet resistance. When the gate length Lg decreases to or below 50 nm as shown in FIG. 2A, the sheet resistance of the second silicide layer 20 a begins to lower. This is because, in case the gate length Lg of the gate electrode 6 a is short, the silicon nitride film 9 a on the sidewall of the gate electrode 6 a promotes silicidation of the gate electrode 6 a and the thickness of the second silicide layer 20 a increases accordingly. Hereafter, this is called “reverse narrow line effect”.
In case the gate length Lg is longer than 50 nm, thickness of the silicide films 20 a and 20 b depends upon a thickness of a metal layer deposited upon the gate electrodes 6 a and 6 b in order to form the silicide films 20 a and 20 b. However, as the gate length Lg decreases to or below 50 nm, silicidation from the sidewall portion of the gate electrode 6 a becomes salient. Therefore, even when the sputtering thickness of the metal layer (for example, thickness of a nickel layer) is constant, the silicon nitride film 9 a formed on the sidewall of the gate electrode 6 a may change the thickness of the silicide film 20 a. Note that the silicon nitride film does not exist on the gate electrode 6 b. Therefore, the reverse narrow line effect does not occur in the second transistor 102 as shown in FIG. 2B.
As the gate length Lg decreases to or below 20 nm, the gate electrode 6 a is entirely silicided (full silicidation).
From the above discussion, it is apparent the gate length Lg of the gate electrode 6a is preferably equal to or less than 50 nm to form the second silicide layer 20 a thicker than the fourth silicide layer 20 b. Further, for full silicidation of the gate electrode 6 a, the gate length of the gate electrode 6 a is preferably equal to or less than 20 nm.
FIG. 3 is a graph showing the relation between the thickness of the silicon oxide layer 7 a and the resistance of the silicide film 20 a. Here, the gate length Lg is 20 nm. Thickness of the silicon oxide film 7 a is the thickness formed on the sidewall of the gate electrode 6 a and the thickness of near the interface between the gate electrode 6 a and the gate insulating film 5 a.
Between the gate electrode 6 a and the silicon nitride film 9 a, the silicon oxide film 7 a intervenes. The silicon oxide film 7 a is formed to prevent concentration of the electric field to the end portion of the gate insulating film 5 a, i.e. to enhance the reliability of the fist transistor 101. However, if the silicon oxide film 7 a is excessively thick, distance between the gate electrode 6 a and the silicon nitride film 9 a increases, and the reverse narrow line effect does not take place.
As shown in FIG. 3, in case the thickness of the silicon oxide film 7 a is larger than 28 nm, resistance of the silicide film 20 a is relatively high. This means that the reverse narrow line effect has not occurred. As the thickness of the silicon oxide film 7 a decreases to or below 28 nm, the reverse narrow line effect occurs, and the resistance of the silicide film 20 a lowers. When the thickness of the silicon oxide film 7 a decreases to or below 10 nm approximately, resistance of the silicide film 20 a stabilizes in a low level. This means that the gate electrode 6 a has been fully silicided.
From the above discussion, it is apparent that the thickness of the silicon oxide film 7 a is preferably equal to or smaller than 20 nm to bring about the reverse narrow line effect. Furthermore, to fully silicide the gate electrode 6 a, thickness of the silicon oxide film 7 a is preferably equal to or less than 10 nm approximately.
When the silicon nitride film 9 a becomes less than 8 nm, the impact of the silicon nitride film on the reverse narrow line effect becomes small. Therefore, the thickness of the silicon nitride film more than 8 nm is required.
Since the first embodiment need not deposit a thick metal layer on the transistor in the full silicide region, it has silicide layers equal in thickness on the source and drain layers in both full silicide and non-full silicide regions. Therefore, the junction leak in the source and drain layers can be prevented. Furthermore, the first embodiment has silicide layers different in thickness on the gate electrodes in the full silicide region and the non-full silicide region. Therefore, it can form both the full silicide MOSFET enhanced in switching speed and the non-full silicide MOSFET having high reliability on the common substrate.
In addition, since the thickness of the silicide layer of the gate electrode does not depend on the thickness of a metal layer deposited, the first embodiment need not deposit metal layers on the full silicide region and the non-full silicide region in different manufacturing steps unlike the conventional technique, and needs no step of removing a mask, which is sequent to deposition of a metal layer. Therefore, the first embodiment can make the manufacturing process easier and can enhance the performance of the transistors.
FIGS. 4A through 13B are cross-sectional views of the semiconductor device according to the first embodiment of the invention, which show a flow of its manufacturing process. FIGS. 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A and 13A are cross-sectional views of the full silicide region. FIGS. 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B and 13B are cross-sectional views of the non-full silicide region.
As shown in FIGS. 4A and 4B, a 200˜350 nm thick Shallow Trench Isolation (STI) is first formed in a p-type or n-type silicon substrate 10 by a device-isolating technique. Thereafter, a silicon oxide film (not shown), equal to or thinner than 20 nm, is formed on the surface of the silicon substrate 10.
After that, to form the well regions 3 a, 3 b and the channel regions 4 a, 4 b, injection of impurities and activating RTA (Rapid Thermal Annealing) follow. Typically, for impurity injection into n-type wells, phosphorus is implanted by ion implantation under the condition of concentration 3.0*13 cm−2 and energy 500 keV. For impurity implantation into n-type channel regions, boron is implanted by ion implantation under the condition of concentration 1.5*13 cm−2 and energy 10 keV. For impurity implantation in p-type wells, boron is injected by impurity implantation under the condition of concentration 2.0*13 cm−2 and energy 260 keV. For impurity implantation into p-type channel regions, arsenic is injected by ion injection under the condition of concentration 1.0*13 cm−2 and energy 80 keV. Thereafter, the previously formed silicon oxide film (not shown) is removed.
After that, 0.5 nm˜6 nm thick gate insulating films 5 a and 5 b are formed by LPCVD (Low Pressure Chemical Vapor Deposition). On the gate insulating films 5 a and 5 b, polysilicon or polysilicon germanium is deposited to a thickness of 50˜200 nm, followed by photolithography, X ray lithography or electron beam lithography for patterning of 10˜150 nm gate length. In addition, polysilicon or polysilicon germanium is partly removed by RIE (Reactive Ion Etching). Through these steps, the gate electrodes 6 a and 6 b having a gate length Lg equal to or less than 50 nm are obtained. The gate insulating films 5 a and 5 b may be any of silicon oxide films (SiO2), silicon oxide nitride films (SiON), silicon nitride films (SiN) and high dielectric films (such as Ta2O3).
As shown in FIGS. 5A and 5B, 1˜6 nm thick silicon oxide films are formed on sidewalls of the gate electrodes 6 a and 6 b by thermal oxidation. Thereafter, a silicon oxide film is deposited by LPCVD. Further through an etch-back process by RIE, silicon oxide films 7 a and 7 b of a thickness equal to or less than 10 nm are obtained. The silicon oxide films 7 a and 7 b are used as offset spacers upon forming the extension layers 8 a and 8 b.
After that, the extension layers 8 a and 8 b are formed. Typically, for impurity implantation into the n-type extension layer, arsenic is implanted by ion implantation under the condition of concentration from 5.0*1014 cm−2 to 1.5*1015 cm−2 and energy 1˜5 keV. For impurity injection into the p-type extension layer, BF2 is injected by ion injection under the condition of concentration from 5.0*1014 cm−2 to 1.5*1015 cm−2 and energy 1˜3 keV. The extension layers 8 a and 8 b are formed in self-alignment via the silicon oxide films 7 a and 7 b as offset spacers.
As shown in FIGS. 6A and 6B, a silicon nitride film 30 is next deposited. Subsequently, as shown in FIGS. 7A and 7B, the silicon nitride film 30 is processed by anisotropic etching by RIE to retain silicon nitride films 9 a and 9 b on sidewalls of the gate electrodes 6 a and 6 b.
As shown in FIGS. 8A and 8B, a TEOS film 40 is next deposited, and photo resist 11 is coated. Subsequently, the photo resist 11 is removed only from the non-full silicide region while retaining it in the full silicide region for patterning.
As shown in FIGS. 9A and 9B, the TEOS film 40 in the non-full silicide region is removed by etching, and the resist is removed thereafter.
As shown in FIGS. 10A and 10B, by using the TEOS film 40 covering the full silicide region as a mask, the silicon nitride film 9 b in the non-full silicide region is removed by etching. Typically, etching of the silicon nitride film 9 b is attained by exposing the silicon nitride film 9 b to hot phosphoric acid solution heated to 160° C.
As shown in FIGS. 11A and 11B, the TEOS film 40 is next removed by dilute fluoric acid. As such, the silicon nitride film 9 a is retained on the sidewall of the gate electrode 6 a in the full silicide region whereas the silicon nitride film 9 b is removed from the sidewall of the gate electrode 6 b in the non-full silicide region.
As shown in FIGS. 12A and 12B, silicon oxide films 12 a and 12 b are next formed additionally on sidewalls of the gate electrodes 6 a and 6 b. The silicon oxide films 12 a and 12 b may have a double-layered structure. In the full silicide region, the silicon oxide films 12 a and 12 b cover the silicon nitride film 9 a.
The silicon oxide films 12 a and 12 b may be a single-layered TEOS layer. Further, the silicon oxide films 12 a and 12 b may be a double-layered structure. For example, the silicon oxide films 12 a and 12 b may have TEOS as liner films and have silicon nitride films outside the liner films. Alternatively, the silicon oxide films 12 a and 12 b may have a triple-layered structure. For example, the silicon oxide films 12 a and 12 b may have TEOS as liner films, silicon nitride films outside the liner films, and silicon oxide films outside the silicon nitride films. Alternatively, the silicon oxide films 12 a and 12 b may have a structure including four or more layers. Thus, the silicon oxide films 12 a and 12 b may be any desired films including silicon oxide films as their base layers.
As shown in FIGS. 13A and 13B, the first source layers 13 a, 23 a and the second drain layers 13 b, 23 b are next formed. These source and drain layers 13 a, 23 a, 13 b and 23 b are next activated by RTA.
In the next step, natural oxide films are removed by treatment using hydrofluoric acid, and a nickel layer is formed uniformly on the surface of the silicon substrate 10. Thereafter, RTA of 400˜500° C. for silicidation is carried out. As a result, surfaces of the source and drain layers 13 a, 23 a, 13 b, 23 b and surfaces of the gate electrodes 6 a, 6 b are silicided. Subsequently, the substrate is exposed to a mixed solution of sulfuric acid and hydrogen peroxide solution to remove nickel not having reacted. A step of depositing a titanium nitride (TiN) film may be added after the sputtering of the nickel layer. Alternatively, a two-step annealing process may be carried out, which first carries out low temperature RTA of 250˜400° C., next exposes the substrate to the mixed solution of sulfuric acid and hydrogen peroxide solution, and thereafter again carries out RTA of 400˜500° C. to lower the sheet resistance.
As a result of this silicidation, the first to fourth silicide layers 14 a, 14 b, 20 a and 20 b are obtained. In this process, in the full silicide region, since the silicon nitride film 9 a exists on the sidewall of the gate electrode 6 a, the second silicide layer 20 a in the gate electrode 6a became thick because of the reverse narrow line effect. When the second silicide layer 20 a reaches the gate insulating film 5 a, the first transistor 101 becomes a full silicide MOSFET. Although the 1˜10 nm thick silicon oxide film 7 a intervenes between the gate electrode 6 a and the silicon nitride film 9 a, it is thin as shown in FIG. 3 and does not function to prevent the reverse narrow line effect.
On the other hand, in the non-full silicide region, there is no silicon nitride film near the gate electrode 6 b. Therefore, the fourth silicide layer 20 b in the gate electrode 6 b is deposited relatively thin. As a result, the second transistor 102 becomes a non-full silicide MOSFET.
Before the step of silicidation, silicon may be epitaxially grown on the source and drain layers 13 a, 23 a, 13 b and 23 b. Alternatively, silicon germanium may be epitaxially grown on the source and drain layers 13 a, 23 a, 13 b and 23 b.
After that, a protection film (not shown) is deposited to protect the first and second silicide layers 14 a, 14 b. Furthermore, an inter-layer film (not shown) is deposited on the protection film. When contact holes are formed, the inter-layer film is partly removed by RIE. In this process, the protection film protects the first and second silicide layers 14 a, 14 b, and prevents junction leak that otherwise occurs due to excavation of the substrate by RIE for the source and drain layers 13 a, 23 a, 13 b and 23 b. Therefore, the protection film is made of a material having higher selectivity than the inter-layer film.
After contact holes are formed, titanium (Ti) or titanium nitride (TiN) is deposited as a barrier metal, and tungsten (W) is deposited further. Finally, metal wiring is formed, and the semiconductor device is completed.
The manufacturing method according to the instant embodiment can easily manufacture a semiconductor device having silicide layers equal in thickness on the source and drain layers in both the full silicide region and the non-full silicide region and having silicide layers equal in thickness on the gate electrodes in both the full silicide region and the non-full silicide region on a common substrate.
A modified method of manufacturing the semiconductor substrate according to the embodiment is next explained below. After the steps shown in FIGS. 4A through 6B, a TEOS film is deposited. After that, the TEOS film is removed only from the non-full silicide region by photolithography and RIE or wet etching. Then, under the existence of the TEOS film retained in the full silicide region as a mask, the silicon nitride film 30 is entirely removed from the non-full silicide region by etching using hot phosphoric acid solution heated to 160° C. Then, the non-full silicide region is covered by photo resist, the TEOS film is removed by treatment using fluoric acid, and the silicon nitride film 30 in the full silicide region is locally removed by anisotropic etching. As a result, the configuration shown in FIGS. 11A and 11B can be obtained.
Second Embodiment
FIG. 14A is a cross-sectional view of the first transistor 101 in the full silicide region of a semiconductor device according to the second embodiment of the invention. FIG. 14B is a cross-sectional view of the second transistor 102 in the non-full silicide region of the semiconductor device according to the second embodiment.
The second embodiment is different from the first embodiment in the use of a silicon nitride film 15 a as an offset spacer. As already explained, the first embodiment includes the silicon oxide film 7 a as the offset spacer, and includes the silicon nitride film 9 a to cover the silicon oxide film 7 a. In the second embodiment, however, since the offset spacer itself serves as the silicon nitride film 15 a, the silicon oxide film 7 a need not be formed.
The silicon nitride film 15 a may be formed on the sidewall of the gate electrode 6 a in direct contact therewith, or via a natural oxide film (not shown) that is usually formed on the surface of the gate electrode 6 a.
In the second embodiment, the silicon nitride film 15 a is formed only on the gate electrode 6 a in the full silicide region. Therefore, the second silicide layer 20 a is formed thicker than the fourth silicide layer 20 b. As a result, the second embodiment assures the same effects as those of the first embodiment.
FIGS. 15A through 16B are cross-sectional views of the semiconductor device according to the second embodiment, which show a flow of its manufacturing method. FIGS. 15A and 16A are cross-sectional views of the full silicide region. FIGS. 15B and 16B are cross-sectional views of the non-full silicide region.
The gate electrodes 6 a and 6 b are formed by the method shown in FIGS. 4A and 4B. As shown in FIGS. 15A and 15B, the silicon nitride films 15 a and 15 b are next formed on sidewalls of the gate electrodes 6 a ad 6 b. The silicon nitride films 15 a and 15 b function as offset spacers when the extension layers 8 a and 8 b are formed. After the extension layers 8 a and 8 b are formed, the TEOS film 40 is deposited on the silicon substrate 10. There follow photolithography and RIE or wet etching to retain the TEOS film 40 in the full silicide region and expose the non-full silicide region. Subsequently, the silicon nitride film 15 b is exposed to hot phosphoric acid solution heated to 160° C. to remove it. Further, the TEOS film 40 is removed also from the full silicide region. As such, as shown in FIGS. 16A and 16B, the silicon nitride can be formed on the sidewall of the gate electrode 6 a in the full silicide region.
After that, similarly to the manufacturing method according to the first embodiment, by forming the silicon oxide films 12 a and 12 b and through the step of silicidation, the semiconductor device shown in FIGS. 14A ad 14B can be obtained.
The manufacturing method of the semiconductor device according to the second embodiment assures the same effects as those of the manufacturing method of the semiconductor device according to the first embodiment.
The manufacturing method of the semiconductor device according to the second embodiment can be modified as well similarly to the first embodiment. That is, after the material of the silicon nitride films 15 a and 15 b are deposited, a TEOS film is deposited. Thereafter, the TEOS film is removed only from the non-full silicide region by photolithography and RIE or wet etching. Under the existence of the TEOS film retained in the full silicide region as a mask, the silicon nitride film is entirely removed from the non-full silicide region by etching using hot phosphoric acid solution heated to 160° C. Thereafter, the non-full silicide region is covered with photo resist, the TEOS film is removed by treatment using fluoric acid, and the silicon nitride film in the full silicide region is partly removed by anisotropic etching by RIE. As such, the configuration shown in FIGS. 15A and 15B can be obtained.
FIG. 17 is a block diagram of a digital/analog mixed circuit including full silicide MOSFETs and non-full silicide MOSFETs on a common substrate. In the analog circuit region required to be low in gate resistance, logic circuit region, and SRAM region required to be high in switching speed, full silicide MOSFETs are formed. In contrast, in the DRAM region requiring a highly reliable gate insulating film, or in a region directly incorporating an existing circuit, non-full silicide MOSFETs are formed.
The first and second embodiments heretofore explained have been directed to semiconductor devices including transistors of full silicide or non-full silicide gate electrodes on a common substrate. However, it will be apparent to the skilled person in the art that it is possible to form transistors having silicide layers simply different in thickness on a common substrate according to the teachings of the present invention, even without siliciding the entirety of the gate electrodes.

Claims (11)

1. A semiconductor device, comprising:
a first transistor including: a first source layer and a first drain layer both formed in a surface of a semiconductor substrate; a first silicide layer formed on the first source layer and the first drain layer; a first gate electrode formed on a first gate insulating film, which is formed on the surface of the semiconductor substrate and has a second silicide layer; and a silicon nitride film formed on sidewalls of the first gate electrode;
a second transistor including: a second source layer and a second drain layer both formed in the surface of the semiconductor substrate; a third silicide layer formed on the second source layer and the second drain layer and equal in thickness to the first silicide layer; a second gate electrode formed on second gate insulating film, which is formed on the surface of the semiconductor substrate and has a fourth silicide layer thinner in thickness than the second silicide layer,
wherein the second silicide layer reaches to the first gate insulating film and is made of a same material as the fourth silicide layer.
2. The semiconductor device according to claim 1, wherein
a gate length of the first gate electrode is equal to or less than 50 nm.
3. The semiconductor device according to claim 1, wherein
a gate length of the first gate electrode is equal to or less than 20 nm.
4. The semiconductor device according to claim 1, wherein
each of the thicknesses of the first silicide layer and the third silicide layer is equal to or less than 30 nm.
5. The semiconductor device according to claim 1, wherein
the first transistor further includes: a thin-film silicon oxide layer intervening between the first gate electrode and the silicon nitride layer provided on sidewalls of the first gate electrode.
6. The semiconductor device according to claim 5, wherein a maximum thickness of the silicon nitride layer is equal to or more than 8 nm.
7. The semiconductor device according to claim 5, wherein
a maximum thickness of the thin-film silicon oxide layer is equal to or less than 28 nm.
8. The semiconductor device according to claim 5, wherein
a maximum thickness of the thin-film silicon oxide layer is equal to or less than 10 nm.
9. The semiconductor device according to claim 1, wherein
the first to fourth silicide layers are made of a nickel silicide.
10. The semiconductor device according to claim 1 further comprising:
a silicon oxide layer provided on the silicon nitride layer of the first transistor.
11. The semiconductor device according to claim 1 further comprising:
a silicon oxide layer provided on sidewalls of the second gate electrode.
US11/053,600 2004-09-21 2005-02-09 Semiconductor device and method of manufacturing a semiconductor device Expired - Fee Related US7427796B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004273849A JP4791722B2 (en) 2004-09-21 2004-09-21 Manufacturing method of semiconductor device
JP2004-273849 2004-09-21

Publications (2)

Publication Number Publication Date
US20060063362A1 US20060063362A1 (en) 2006-03-23
US7427796B2 true US7427796B2 (en) 2008-09-23

Family

ID=36074611

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/053,600 Expired - Fee Related US7427796B2 (en) 2004-09-21 2005-02-09 Semiconductor device and method of manufacturing a semiconductor device

Country Status (3)

Country Link
US (1) US7427796B2 (en)
JP (1) JP4791722B2 (en)
CN (1) CN100418224C (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070131930A1 (en) * 2005-12-13 2007-06-14 Kazuhiko Aida Semiconductor device and method for fabricating the same
US20140353729A1 (en) * 2013-05-29 2014-12-04 United Microelectronics Corp. Semiconductor structure and method for forming the same

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5023425B2 (en) * 2004-09-28 2012-09-12 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof
CN103021951B (en) * 2011-09-27 2014-09-24 中芯国际集成电路制造(上海)有限公司 Flash memory and manufacturing method thereof as well as formation method of grids in different thicknesses

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7112483B2 (en) * 2003-08-29 2006-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming a device having multiple silicide types

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11261020A (en) * 1998-03-11 1999-09-24 Nec Corp Semiconductor device and manufacturing method thereof
KR100327347B1 (en) * 2000-07-22 2002-03-06 Samsung Electronics Co Ltd Metal oxide semiconductor field effect transistor having reduced resistance between source and drain and fabricating method thereof
JP2003168740A (en) * 2001-09-18 2003-06-13 Sanyo Electric Co Ltd Semiconductor device and method of manufacturing semiconductor device
US6498067B1 (en) * 2002-05-02 2002-12-24 Taiwan Semiconductor Manufacturing Company Integrated approach for controlling top dielectric loss during spacer etching
EP1411146B1 (en) * 2002-10-17 2010-06-09 Samsung Electronics Co., Ltd. Method of forming cobalt silicide film and method of manufacturing semiconductor device having cobalt silicide film
JP4457688B2 (en) * 2004-02-12 2010-04-28 ソニー株式会社 Semiconductor device
US7122472B2 (en) * 2004-12-02 2006-10-17 International Business Machines Corporation Method for forming self-aligned dual fully silicided gates in CMOS devices

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7112483B2 (en) * 2003-08-29 2006-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming a device having multiple silicide types

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
J. Kedzierski et al., "Issues in NiSi-gated FDSOI Device Integration", IEDM Tech. Digest, 2003, pp. 441-444.

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070131930A1 (en) * 2005-12-13 2007-06-14 Kazuhiko Aida Semiconductor device and method for fabricating the same
US7495299B2 (en) * 2005-12-13 2009-02-24 Panasonic Corporation Semiconductor device
US20140353729A1 (en) * 2013-05-29 2014-12-04 United Microelectronics Corp. Semiconductor structure and method for forming the same

Also Published As

Publication number Publication date
JP4791722B2 (en) 2011-10-12
CN1753183A (en) 2006-03-29
US20060063362A1 (en) 2006-03-23
CN100418224C (en) 2008-09-10
JP2006093233A (en) 2006-04-06

Similar Documents

Publication Publication Date Title
US20030211684A1 (en) Gate stack for high performance sub-micron CMOS devices
JPH11354651A (en) CMOS self-aligned strap-like interconnect and method
JP2001148472A (en) Semiconductor device and manufacturing method thereof
US6140192A (en) Method for fabricating semiconductor device
US7141467B2 (en) Semiconductor device having metal silicide films formed on source and drain regions and method for manufacturing the same
US8004050B2 (en) Semiconductor device comprising gate electrode having arsenic and phosphorous
JP2002539638A (en) Method of manufacturing MIS field-effect transistor
US6667204B2 (en) Semiconductor device and method of forming the same
US6025241A (en) Method of fabricating semiconductor devices with self-aligned silicide
JPH08213610A (en) Field effect type semiconductor device and method of manufacturing the same
US6221760B1 (en) Semiconductor device having a silicide structure
JP2001320045A (en) Method of manufacturing MIS type semiconductor device
US6153457A (en) Method of fabricating self-align-contact
US7427796B2 (en) Semiconductor device and method of manufacturing a semiconductor device
US20050212040A1 (en) Semiconductor device having gate sidewall structure in silicide process and producing method of the semiconductor device
JP3190858B2 (en) Semiconductor device and method of manufacturing the same
US20060134874A1 (en) Manufacture method of MOS semiconductor device having extension and pocket
JP3301994B2 (en) Method for manufacturing semiconductor device
US7521767B2 (en) MOS transistor in a semiconductor device
JP2842842B2 (en) MOS type semiconductor device and method of manufacturing the same
US6221725B1 (en) Method of fabricating silicide layer on gate electrode
JP2007305889A (en) Semiconductor device and its manufacturing method
JP4065803B2 (en) Manufacturing method of semiconductor device
US6197672B1 (en) Method for forming polycide dual gate
JPH08250603A (en) Semiconductor device and manufacture thereof

Legal Events

Date Code Title Description
AS Assignment

Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HOKAZONO, AKIRA;REEL/FRAME:016543/0762

Effective date: 20050413

FPAY Fee payment

Year of fee payment: 4

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20160923