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US7323361B2 - Packaging system for semiconductor devices - Google Patents

Packaging system for semiconductor devices Download PDF

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Publication number
US7323361B2
US7323361B2 US10/397,436 US39743603A US7323361B2 US 7323361 B2 US7323361 B2 US 7323361B2 US 39743603 A US39743603 A US 39743603A US 7323361 B2 US7323361 B2 US 7323361B2
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Prior art keywords
die
lead frame
chip
drain
semiconductor device
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US10/397,436
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US20030214019A1 (en
Inventor
David Chong
Hun Kwang Lee
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Semiconductor Components Industries LLC
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Fairchild Semiconductor Corp
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Publication date
Application filed by Fairchild Semiconductor Corp filed Critical Fairchild Semiconductor Corp
Priority to US10/397,436 priority Critical patent/US7323361B2/en
Priority to PCT/US2003/009692 priority patent/WO2003083908A2/en
Priority to CNB038109328A priority patent/CN100466209C/en
Priority to TW092107101A priority patent/TWI283048B/en
Priority to JP2003581236A priority patent/JP4485210B2/en
Priority to DE10392461T priority patent/DE10392461T5/en
Priority to AU2003226134A priority patent/AU2003226134A1/en
Publication of US20030214019A1 publication Critical patent/US20030214019A1/en
Priority to US11/844,914 priority patent/US7579680B2/en
Assigned to FAIRCHILD SEMICONDUCTOR CORPORATION reassignment FAIRCHILD SEMICONDUCTOR CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHONG, DAVID, LEE, HUN KWANG
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Publication of US7323361B2 publication Critical patent/US7323361B2/en
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Assigned to DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT reassignment DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, FAIRCHILD SEMICONDUCTOR CORPORATION reassignment SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 040075, FRAME 0644 Assignors: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Assigned to FAIRCHILD SEMICONDUCTOR CORPORATION, SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC reassignment FAIRCHILD SEMICONDUCTOR CORPORATION RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Assignors: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for individual devices of subclass H10D
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Definitions

  • the invention generally relates to methods for fabricating integrated circuits (ICs) and semiconductor devices and the resulting structures. More particularly, the invention relates generally to the packaging used for IC and semiconductor devices. More specifically, the invention relates to a packaged integrated circuit having a low drain/source resistance, smaller footprint, low profile, excellent packaging inductance, excellent thermal performance, and a simplified manufacturing process.
  • IC also called semiconductor
  • Semiconductor processing builds hundreds of individual IC (also called semiconductor) chips on a wafer. These individual chips are then tested, assembled, and packaged for their various uses.
  • the packaging step can be an important step in terms of costs and reliability.
  • the individual IC chip must be connected properly to leads (leading to external circuitry) and packaged in a way that is convenient for use in a larger circuit or electrical system.
  • the wafers containing the numerous IC chips Prior to packaging, the wafers containing the numerous IC chips are thinned from the side of the wafer away from the chips. The wafers are then mounted to an adhesive tape and cut into individual chips, typically using a dicing saw. The chips are then mounted onto a metal lead frame or on a metallized region of an insulating substrate. In this process, a thin layer of a metal (such as Au, optionally combined with Ge or other elements to improve the metal contact) is placed between the bottom of the chip and the metal lead frame/insulated substrate. Heat (and optionally a slight pressure) can then be applied to form an alloyed bond holding the chip firmly to the substrate.
  • a metal such as Au, optionally combined with Ge or other elements to improve the metal contact
  • the chips are then wire bonded to the lead frame.
  • This wire bonding is typically performed by attaching interconnecting wires from various contact pads on the IC chip to corresponding posts on the lead frame.
  • the time used to bond wires individually to each pad on the chip can be overcome by several methods that utilize simultaneous bonding, i.e., the flip-chip approach.
  • relatively thick metal bumps are deposited on the contact pad before the chips are separated from the wafer.
  • a matching metallization pattern is also provided on the substrate. After separation from the wafer, each chip is turned upside down and the bumps are properly aligned with the metallization pattern on the substrate. Then, ultrasonic bonding or solder alloying aids the attachment of each bump to its corresponding metallization pattern on the substrate.
  • the resulting device is then packaged in any suitable medium that can protect it from the environment of its intended use. In most cases, this means that the device is isolated from moisture, contaminants, and corrosion.
  • the packaging used for such protection can be either hermetic-ceramic or plastic. In a plastic package, the chip is encapsulated with resin materials, typically epoxy-based resins.
  • FIGS. 5 and 6 depict an IC chip with a typical plastic package having a source 201 , gate 202 , and drain 203 .
  • the chip/die 206 is attached to the central support 207 of the lead frame.
  • the frame made of etched or stamped thin metal (e.g., Fe—Ni or Cu alloys), includes external leads 205 and the interconnections provided by the bond wires 204 are typically fine gold wires.
  • the encapsulation 208 is often accomplished by a molding process that uses an epoxy resin to cover the chip and form the outer shape of the package at the same time.
  • the external portions of the lead frame can be shaped as a gull wing lead or a j-lead (as depicted in FIG. 6 ).
  • Such prior art devices suffer from several problems. Namely, such devices have a relatively high drain-source resistance (R DS(on) ), a large footprint, a high profile, a poor package inductance, an inefficient thermal performance, and often require complex manufacturing processes.
  • R DS(on) drain-source resistance
  • the invention provides a package system for integrated circuit (IC) chips and a method for making such a package system.
  • the method uses a solder-ball flip-chip method for connecting the IC chips onto a lead frame that has pre-formed gull-wing leads only on the source/gate side of the chip.
  • a boschman molding technique is used for the encapsulation process, leaving exposed land and die bottoms for a direct connection to a circuit board.
  • the resulting packaged IC chip has the source and gate of the chip directly connected to the lead frame by solder balls.
  • the drain of the chip is directly mounted to the circuit board without the need for leads from the drain side of the chip.
  • FIGS. 1 , 2 A- 2 C, 3 A- 3 B, and 5 - 6 The following description of the invention can be understood in light of FIGS. 1 , 2 A- 2 C, 3 A- 3 B, and 5 - 6 , in which:
  • FIG. 1 illustrates a IC chip used in one aspect of the invention
  • FIGS. 2A , B, & C illustrate a partial method of packaging an IC chip in one aspect of the invention
  • FIGS. 3A and B illustrate a packaged IC chip in one aspect of the invention.
  • FIGS. 5 and 6 illustrate conventional packaged IC chips.
  • FIGS. 1 , 2 A- 2 C, 3 A- 3 B, and 5 - 6 illustrate specific aspects of the invention and are a part of the specification. Together with the following description, the Figures demonstrate and explain the principles of the invention.
  • the packaged IC chip of the invention has several features. First, it has the source of the IC chip directly connected to the lead frame by solder balls. Second, the bottoms of the leads and the IC chip are not completely encapsulated. Third, the drain of the IC is directly mounted to the circuit board without the need for leads from the drain side of the IC.
  • any method that forms such a packaged IC chip can be used in the invention.
  • the method described below is used to form such a packaged IC chip.
  • the various IC chips are first manufactured on a wafer, cut from the wafer, and then tested.
  • the individual chips are then bonded to a die as conventionally known in the art (and the combined chip and die will be referred hereafter to as die 10 ).
  • die 10 the combined chip and die will be referred hereafter to as die 10 ).
  • the IC chip is manufactured with a lined array of I/O points 11 for the internal circuitry of the chip to communicate with the external circuitry of the electronic device in which the packaged chip is used. This array can be made using any known process in the art when manufacturing the IC chip.
  • the chip is also manufactured to contain a plurality of metallization pads 20 , typically made of aluminum (Al).
  • the pads 20 are formed respectively over the I/O points 11 by any known process in the art.
  • These metallization pads 20 can serve as test pads, bump pads, or both.
  • the die 10 are connected to the lead frame by any flip-chip technique known in the art, including the process illustrated in 2 B and 2 C.
  • a bumping process is first performed to form a solder bump 40 on each metallization pad 20 over the semiconductor die 10 .
  • the solder bump 40 can be made of any solderable metal known in the art and process of forming the solder bumps 40 can be carried out as known in the art.
  • the resulting bumping structure is formed over the semiconductor die 10 as shown in FIG. 2B .
  • this bumping structure is used to bond the semiconductor die 10 to a substrate, which is in one aspect of the invention a lead frame 30 .
  • the lead frame supports the die, serves as a fundamental part of the I/O interconnection system, and also provides a thermally conductive path for dissipating the majority of the heat generated by the die.
  • This bonding process is carried out by aligning the die 10 with bumps 40 over the desired location of the lead frame 30 and then pressing the die 10 and lead frame 30 together under heat so that the bump 40 (which is already attached to die 10 ) becomes attached to lead frame 30 .
  • the lead frame 30 is manufactured either by stamping or by masked etching.
  • the lead frame features an interconnected metallized pattern that is made up of the following: a centrally located support to which the die containing chip 10 is attached and a network of leads 35 extending therefrom.
  • Metal strips (not shown) that act as dam bars are located between the leads at points that will eventually be just outside the edge of the completed package assembly. During the encapsulation process, these dam bars help prevent encapsulant from seeping out of the mold and flowing onto the leads where it could later adversely affect lead trim and form operations. Additional bars (not shown) can be located between the lead tips to provide protection of the leads from mechanical damage during processing and handling.
  • the lead frame is manufactured with a gull wing configuration as known in the art.
  • FIG. 2C After performing the “flip-chip” technique, the resulting structure is illustrated in FIG. 2C .
  • this structure is then encapsulated.
  • This encapsulation can be carried out by any known encapsulation process that obtains the structure depicted in FIGS. 3A and 3B .
  • Examples of such encapsulation processes include premolding, postmolding, or boschman molding processes.
  • premolding a plastic base is first molded; the die is then placed on it and is connected to the desired I/O configuration. Finally, a separate plastic lid (or top) is joined to the base.
  • postmolding the leadframe with an attached die is loaded into a multicavity molding fixture and is encapsulated in molding compound using a single molding process.
  • a boschman molding technique is used during the encapsulation process.
  • a film is attached on the “reverse” face (or side 37 ) of the die 10 before the encapsulation procedure. This reverse face is that side of the die 10 containing the drain and the corresponding side of the leads of the lead frame.
  • the film is attached to the dies by lining the bottom of the mold with a sheet of the film.
  • the structure is then place in a mold and the encapsulant material is transferred into the mold.
  • a laminating tool is placed over the dambar or leadframe surface to laminate the leadframe onto the film.
  • the mold is closed and encapsulant material cured to create the encapsulant 45 .
  • the molded structure is removed and the film then peeled off after the encapsulation to obtain the structure depicted in FIGS. 3A and 3B . Using this process, the resulting structure can be manufactured without any remaining adhesive residue.
  • This damage to the packaged chip can be cosmetic (i.e. marring of the substrate surface) and/or functional (e.g. fracturing of the substrate; destruction of the electrically conductive traces on the substrate surface; tearing away of the solder mask on the substrate surface to undesirably expose, for instance, copper; and/or weakening or breaking of the seal between the encapsulant and the substrate surface).
  • cosmetic i.e. marring of the substrate surface
  • functional e.g. fracturing of the substrate; destruction of the electrically conductive traces on the substrate surface; tearing away of the solder mask on the substrate surface to undesirably expose, for instance, copper; and/or weakening or breaking of the seal between the encapsulant and the substrate surface.
  • the packaged chip of the invention obtained is depicted in FIGS. 3A and 3B .
  • the packaged IC chip 5 contains exposed land and die bottom surfaces 22 . These surfaces are used for connecting (or mounting) the packaged IC chip directly to the circuit board of an electronic device or system in which the packaged IC chip 5 is used.
  • any method of mounting the packaged IC chip to a circuit board of an electronic apparatus that provides a direct connection between the exposed portions of packaged chip and the circuit board can be used in the invention.
  • the packaged chip of the invention provides several advantages over other known packaged chips in the art.
  • the packaged chips of the invention have a relatively low drain/source resistance.
  • the source and gate are connected directly to the leadframe by solder balls.
  • the drain and the leads of the leadframe are mounted directly onto the circuit board without an intervening encapsulant, a short electrical resistive path is created.
  • the second advantage is that the packaged chips of the invention have a smaller footprint and lower profile.
  • the leads are eliminated on the drain side of the package.
  • the gate and source are directly connected to the frame, thereby allowing the leads to be located closer to the edge of die.
  • the packaged chips have no encapsulation on the bottom of the molded package (i.e., exposing the die).
  • the third advantage is that the packaged chips of the invention have an improved package inductance. This advantage exists because of two features of the packaged chips. First, the use of gold wire has been eliminated. Second, the gate and source pins are directly connected to the leadframe.
  • the fourth advantage is that the packaged chips of the invention have a more efficient thermal performance.
  • the drain of the packaged chip is mounted directly from the die back to the circuit board without any encapsulation. Thus, heat generated by the chip during its operation is quickly dissipated into the circuit board.
  • the final advantage is that the packaged chips of the invention have a simpler manufacturing process for the following reasons.
  • a flip chip technique is used in place of the tedious and time consuming wire bonding.
  • Second, it is map molded with a sheet lining on the bottom mold that is laminated to the bottom side of the package with exposed die back, resulting in little to no mold bleed.
  • the IC chip can be sawn and/or diced to the desired package size because of the subsequent processing used.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A package system for integrated circuit (IC) chips and a method for making such a package system. The method uses a solder-ball flip-chip method for connecting the IC chips onto a lead frame that has pre-formed gull-wing leads only on the source/gate side of the chip. A boschman molding technique is used for the encapsulation process, leaving exposed land and die bottoms for a direct connection to a circuit board. The resulting packaged IC chip has the source of the chip directly connected to the lead frame by solder balls. As well, the drain and gate of the chip are directly mounted to the circuit board without the need for leads from the drain side of the chip.

Description

REFERENCE TO RELATED APPLICATIONS
This application claims priority from U.S. provisional patent application No. 60/368,587, filed Mar. 29, 2002 the entire disclosure of which is incorporated herein by reference.
FIELD OF THE INVENTION
The invention generally relates to methods for fabricating integrated circuits (ICs) and semiconductor devices and the resulting structures. More particularly, the invention relates generally to the packaging used for IC and semiconductor devices. More specifically, the invention relates to a packaged integrated circuit having a low drain/source resistance, smaller footprint, low profile, excellent packaging inductance, excellent thermal performance, and a simplified manufacturing process.
BACKGROUND OF THE INVENTION
Semiconductor processing builds hundreds of individual IC (also called semiconductor) chips on a wafer. These individual chips are then tested, assembled, and packaged for their various uses. The packaging step can be an important step in terms of costs and reliability. The individual IC chip must be connected properly to leads (leading to external circuitry) and packaged in a way that is convenient for use in a larger circuit or electrical system.
Prior to packaging, the wafers containing the numerous IC chips are thinned from the side of the wafer away from the chips. The wafers are then mounted to an adhesive tape and cut into individual chips, typically using a dicing saw. The chips are then mounted onto a metal lead frame or on a metallized region of an insulating substrate. In this process, a thin layer of a metal (such as Au, optionally combined with Ge or other elements to improve the metal contact) is placed between the bottom of the chip and the metal lead frame/insulated substrate. Heat (and optionally a slight pressure) can then be applied to form an alloyed bond holding the chip firmly to the substrate.
Once the chips are mounted by this process, the chips are then wire bonded to the lead frame. This wire bonding is typically performed by attaching interconnecting wires from various contact pads on the IC chip to corresponding posts on the lead frame. The time used to bond wires individually to each pad on the chip can be overcome by several methods that utilize simultaneous bonding, i.e., the flip-chip approach. In this approach, relatively thick metal bumps are deposited on the contact pad before the chips are separated from the wafer. A matching metallization pattern is also provided on the substrate. After separation from the wafer, each chip is turned upside down and the bumps are properly aligned with the metallization pattern on the substrate. Then, ultrasonic bonding or solder alloying aids the attachment of each bump to its corresponding metallization pattern on the substrate.
The resulting device is then packaged in any suitable medium that can protect it from the environment of its intended use. In most cases, this means that the device is isolated from moisture, contaminants, and corrosion. The packaging used for such protection can be either hermetic-ceramic or plastic. In a plastic package, the chip is encapsulated with resin materials, typically epoxy-based resins.
FIGS. 5 and 6 depict an IC chip with a typical plastic package having a source 201, gate 202, and drain 203. The chip/die 206 is attached to the central support 207 of the lead frame. The frame, made of etched or stamped thin metal (e.g., Fe—Ni or Cu alloys), includes external leads 205 and the interconnections provided by the bond wires 204 are typically fine gold wires. The encapsulation 208 is often accomplished by a molding process that uses an epoxy resin to cover the chip and form the outer shape of the package at the same time. The external portions of the lead frame can be shaped as a gull wing lead or a j-lead (as depicted in FIG. 6).
Such prior art devices however, suffer from several problems. Namely, such devices have a relatively high drain-source resistance (RDS(on)), a large footprint, a high profile, a poor package inductance, an inefficient thermal performance, and often require complex manufacturing processes.
SUMMARY OF THE INVENTION
The invention provides a package system for integrated circuit (IC) chips and a method for making such a package system. The method uses a solder-ball flip-chip method for connecting the IC chips onto a lead frame that has pre-formed gull-wing leads only on the source/gate side of the chip. A boschman molding technique is used for the encapsulation process, leaving exposed land and die bottoms for a direct connection to a circuit board. The resulting packaged IC chip has the source and gate of the chip directly connected to the lead frame by solder balls. As well, the drain of the chip is directly mounted to the circuit board without the need for leads from the drain side of the chip.
BRIEF DESCRIPTION OF THE DRAWINGS
The following description of the invention can be understood in light of FIGS. 1, 2A-2C, 3A-3B, and 5-6, in which:
FIG. 1 illustrates a IC chip used in one aspect of the invention;
FIGS. 2A, B, & C illustrate a partial method of packaging an IC chip in one aspect of the invention;
FIGS. 3A and B illustrate a packaged IC chip in one aspect of the invention.
FIGS. 5 and 6 illustrate conventional packaged IC chips.
FIGS. 1, 2A-2C, 3A-3B, and 5-6 illustrate specific aspects of the invention and are a part of the specification. Together with the following description, the Figures demonstrate and explain the principles of the invention.
 DETAILED DESCRIPTION OF THE INVENTION
The following description provides specific details in order to provide a thorough understanding of the invention. The skilled artisan, however, would understand that the invention can be practiced without employing these specific details. Indeed, the invention can be practiced by modifying the illustrated method and resulting product and can be used in conjunction with apparatus and techniques conventionally used in the industry. Indeed, as described briefly below, the invention can be adapted for packaging systems for electronics devices other than just ICs.
The packaged IC chip of the invention has several features. First, it has the source of the IC chip directly connected to the lead frame by solder balls. Second, the bottoms of the leads and the IC chip are not completely encapsulated. Third, the drain of the IC is directly mounted to the circuit board without the need for leads from the drain side of the IC.
Any method that forms such a packaged IC chip can be used in the invention. In one aspect of the invention, the method described below is used to form such a packaged IC chip. To begin, the various IC chips are first manufactured on a wafer, cut from the wafer, and then tested. The individual chips are then bonded to a die as conventionally known in the art (and the combined chip and die will be referred hereafter to as die 10). During the manufacturing process, and as shown in FIG. 1, the IC chip is manufactured with a lined array of I/O points 11 for the internal circuitry of the chip to communicate with the external circuitry of the electronic device in which the packaged chip is used. This array can be made using any known process in the art when manufacturing the IC chip.
The chip is also manufactured to contain a plurality of metallization pads 20, typically made of aluminum (Al). The pads 20 are formed respectively over the I/O points 11 by any known process in the art. These metallization pads 20 can serve as test pads, bump pads, or both.
Next, the die 10 are connected to the lead frame by any flip-chip technique known in the art, including the process illustrated in 2B and 2C. As detailed in FIG. 2B, a bumping process is first performed to form a solder bump 40 on each metallization pad 20 over the semiconductor die 10. The solder bump 40 can be made of any solderable metal known in the art and process of forming the solder bumps 40 can be carried out as known in the art.
The resulting bumping structure is formed over the semiconductor die 10 as shown in FIG. 2B. Then, this bumping structure is used to bond the semiconductor die 10 to a substrate, which is in one aspect of the invention a lead frame 30. The lead frame supports the die, serves as a fundamental part of the I/O interconnection system, and also provides a thermally conductive path for dissipating the majority of the heat generated by the die. This bonding process is carried out by aligning the die 10 with bumps 40 over the desired location of the lead frame 30 and then pressing the die 10 and lead frame 30 together under heat so that the bump 40 (which is already attached to die 10) becomes attached to lead frame 30.
Before the bonding process, the lead frame 30 is manufactured either by stamping or by masked etching. The lead frame features an interconnected metallized pattern that is made up of the following: a centrally located support to which the die containing chip 10 is attached and a network of leads 35 extending therefrom. Metal strips (not shown) that act as dam bars are located between the leads at points that will eventually be just outside the edge of the completed package assembly. During the encapsulation process, these dam bars help prevent encapsulant from seeping out of the mold and flowing onto the leads where it could later adversely affect lead trim and form operations. Additional bars (not shown) can be located between the lead tips to provide protection of the leads from mechanical damage during processing and handling. The lead frame is manufactured with a gull wing configuration as known in the art.
After performing the “flip-chip” technique, the resulting structure is illustrated in FIG. 2C. Next, this structure is then encapsulated. This encapsulation can be carried out by any known encapsulation process that obtains the structure depicted in FIGS. 3A and 3B. Examples of such encapsulation processes include premolding, postmolding, or boschman molding processes. In premolding, a plastic base is first molded; the die is then placed on it and is connected to the desired I/O configuration. Finally, a separate plastic lid (or top) is joined to the base. In postmolding, the leadframe with an attached die is loaded into a multicavity molding fixture and is encapsulated in molding compound using a single molding process.
In one aspect of the invention, a boschman molding technique is used during the encapsulation process. In this technique, a film is attached on the “reverse” face (or side 37) of the die 10 before the encapsulation procedure. This reverse face is that side of the die 10 containing the drain and the corresponding side of the leads of the lead frame. The film is attached to the dies by lining the bottom of the mold with a sheet of the film. The structure is then place in a mold and the encapsulant material is transferred into the mold. A laminating tool is placed over the dambar or leadframe surface to laminate the leadframe onto the film. The mold is closed and encapsulant material cured to create the encapsulant 45. The molded structure is removed and the film then peeled off after the encapsulation to obtain the structure depicted in FIGS. 3A and 3B. Using this process, the resulting structure can be manufactured without any remaining adhesive residue.
In manufacturing similar devices by molding operations, it is well recognized that certain disadvantages occurred. During the encapsulation and subsequent removal of excess material, the encapsulant enclosed both the die and die bonds, as well as extended along the surface of the die-mounting substrate. The excess encapsulant, sometimes called mold bleed (i.e., encapsulant other than that necessary to enclose the die and die bonds), must then be removed by a subsequent process.
One method for removing this mold bleed was the simple mechanical act of peeling. When the excess encapsulant was peeled away from the substrate surface, however, some of the mold bleed adhered to the substrate surface, twisting the substrate and tearing/rupturing the substrate surface. This damage to the packaged chip can be cosmetic (i.e. marring of the substrate surface) and/or functional (e.g. fracturing of the substrate; destruction of the electrically conductive traces on the substrate surface; tearing away of the solder mask on the substrate surface to undesirably expose, for instance, copper; and/or weakening or breaking of the seal between the encapsulant and the substrate surface). By using the molding technique described above, however, this molding bleed—and the damage from its removal—can be avoided.
After being encapsulated, the packaged chip of the invention obtained is depicted in FIGS. 3A and 3B. As illustrated, the packaged IC chip 5 contains exposed land and die bottom surfaces 22. These surfaces are used for connecting (or mounting) the packaged IC chip directly to the circuit board of an electronic device or system in which the packaged IC chip 5 is used.
Any method of mounting the packaged IC chip to a circuit board of an electronic apparatus that provides a direct connection between the exposed portions of packaged chip and the circuit board can be used in the invention.
The packaged chip of the invention provides several advantages over other known packaged chips in the art. First, the packaged chips of the invention have a relatively low drain/source resistance. In the packaged chips, the source and gate are connected directly to the leadframe by solder balls. And since the drain and the leads of the leadframe are mounted directly onto the circuit board without an intervening encapsulant, a short electrical resistive path is created.
The second advantage is that the packaged chips of the invention have a smaller footprint and lower profile. In the packaged chips, the leads are eliminated on the drain side of the package. As well, the gate and source are directly connected to the frame, thereby allowing the leads to be located closer to the edge of die. Further, the packaged chips have no encapsulation on the bottom of the molded package (i.e., exposing the die).
The third advantage is that the packaged chips of the invention have an improved package inductance. This advantage exists because of two features of the packaged chips. First, the use of gold wire has been eliminated. Second, the gate and source pins are directly connected to the leadframe.
The fourth advantage is that the packaged chips of the invention have a more efficient thermal performance. The drain of the packaged chip is mounted directly from the die back to the circuit board without any encapsulation. Thus, heat generated by the chip during its operation is quickly dissipated into the circuit board.
The final advantage is that the packaged chips of the invention have a simpler manufacturing process for the following reasons. First, a flip chip technique is used in place of the tedious and time consuming wire bonding. Second, it is map molded with a sheet lining on the bottom mold that is laminated to the bottom side of the package with exposed die back, resulting in little to no mold bleed. Finally, the IC chip can be sawn and/or diced to the desired package size because of the subsequent processing used.
Having described the preferred embodiments of the invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.

Claims (20)

1. A method for making a semiconductor device, comprising:
providing a semiconductor die;
attaching a lead frame to the semiconductor die without using a bond wire; and
substantially encapsulating the die and the lead frame except for a part of the bottoms of the die and the lead frame so that any exposed lead frame surface is substantially coplanar with the encapsulation,
wherein the part of the die that is attached to the lead frame comprises a source and a gate for the semiconductor device.
2. The method of claim 1, including attaching the die to the lead frame via solder balls.
3. The method of claim 1, wherein the device contains no leads connected to the drain of the die on the drain side of the die.
4. A method for making a semiconductor device, comprising:
providing a semiconductor die;
attaching a lead frame to the semiconductor die without using a bond wire; and
substantially encapsulating the die and the lead frame except for a part of the bottoms of the die and the lead frame so that any exposed lead frame surface is substantially coplanar with the encapsulation,
wherein the device contains no leads connected to the drain of the die on the drain side of the die.
5. The method of claim 4, including attaching the die to the lead frame via solder balls.
6. The method of claim 4, wherein the part of the die that is attached to the lead frame comprises a source and a gate for the semiconductor device.
7. A method for making a semiconductor device, comprising:
providing a semiconductor die having a source and a drain;
attaching a lead frame to the semiconductor die without using a bond wire, the frame containing no leads connected to the drain of the die on the drain side of the die; and
substantially encapsulating the die and the lead frame except for a part of the bottoms of the die and the lead frame so that any exposed lead frame surface is substantially coplanar with the encapsulation.
8. The method of claim 7, including attaching the die to the lead frame via solder balls.
9. The method of claim 7, wherein the part of the die that is attached to the lead frame comprises a source and a gate for the semiconductor device.
10. The method of claim 7, wherein the encapsulation is performed by a boschman molding technique.
11. A method for packaging a semiconductor device, comprising:
providing a semiconductor die that is attached to a lead frame without using a bond wire; and
substantially encapsulating the die and the lead frame by a boschman molding technique, without encapsulating a part of the bottoms of the die and the lead frame, wherein any exposed lead frame surface is substantially coplanar with the encapsulation.
12. The method of claim 11, including attaching the die to the lead frame via solder balls.
13. The method of claim 12, wherein the part of the die that is attached to the lead frame comprises a source and a gate for the semiconductor device.
14. The method of claim 11, wherein the device contains no leads connected to the drain of the die on the drain side of the die.
15. A method for packaging a semiconductor device, comprising:
providing a semiconductor die having a source and a drain, the die attached to a lead frame without using a bond wire and containing no leads connected to the drain of the die on the drain side of the die; and
substantially encapsulating the die and the lead frame by a boschman molding technique, without encapsulating a part of the bottoms of the die and the lead frame, wherein any exposed lead frame surface is substantially coplanar with the encapsulation.
16. The method of claim 15, including attaching the die to the lead frame via solder balls.
17. The method of claim 15, wherein the part of the die that is attached to the lead frame comprises a source and a gate for the semiconductor device.
18. A method for making an electronic apparatus containing a packaged semiconductor device, the method comprising:
providing a packaged semiconductor device containing a die with a source and a drain and a lead frame without using a bond wire and containing no leads connected to the drain of the die on the drain side of the die, wherein the die and the lead frame are substantially encapsulated except for a part of the bottoms of the die and the lead frame, and any exposed lead frame surface is substantially coplanar with the encapsulation; and
attaching the packaged semiconductor device to a part of the electronic apparatus using the non-encapsulated parts of device.
19. The method of claim 18, including attaching the die to the lead frame via solder balls.
20. The method of claim 18, wherein the part of the die that is attached to the lead frame comprises a source and a gate for the semiconductor device.
US10/397,436 2002-03-29 2003-03-25 Packaging system for semiconductor devices Expired - Lifetime US7323361B2 (en)

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US10/397,436 US7323361B2 (en) 2002-03-29 2003-03-25 Packaging system for semiconductor devices
CNB038109328A CN100466209C (en) 2002-03-29 2003-03-28 Packaging system for semiconductor devices
TW092107101A TWI283048B (en) 2002-03-29 2003-03-28 New package system for discrete devices
JP2003581236A JP4485210B2 (en) 2002-03-29 2003-03-28 Semiconductor device, electronic device, method for manufacturing semiconductor device, and method for manufacturing electronic device
DE10392461T DE10392461T5 (en) 2002-03-29 2003-03-28 Packaging system for semiconductor devices
AU2003226134A AU2003226134A1 (en) 2002-03-29 2003-03-28 Packaging system for semiconductor devices
PCT/US2003/009692 WO2003083908A2 (en) 2002-03-29 2003-03-28 Packaging system for semiconductor devices
US11/844,914 US7579680B2 (en) 2002-03-29 2007-08-24 Packaging system for semiconductor devices

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9536800B2 (en) 2013-12-07 2017-01-03 Fairchild Semiconductor Corporation Packaged semiconductor devices and methods of manufacturing

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7323361B2 (en) * 2002-03-29 2008-01-29 Fairchild Semiconductor Corporation Packaging system for semiconductor devices
US7408245B2 (en) * 2006-12-22 2008-08-05 Powertech Technology Inc. IC package encapsulating a chip under asymmetric single-side leads
CN114975130A (en) * 2022-05-31 2022-08-30 浙江禾芯集成电路有限公司 Packaging method of packaging structure of vertical MOSFET chip

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4653993A (en) * 1982-08-19 1987-03-31 Boschman Kleinpenning Beheer B.V. Apparatus for encapsulating electronic components in plastic material
US5202849A (en) * 1989-10-20 1993-04-13 Fujitsu Limited Dynamic semiconductor memory device
US5844315A (en) 1996-03-26 1998-12-01 Motorola Corporation Low-profile microelectronic package
US5925934A (en) * 1995-10-28 1999-07-20 Institute Of Microelectronics Low cost and highly reliable chip-sized package
US6077724A (en) 1998-09-05 2000-06-20 First International Computer Inc. Multi-chips semiconductor package and fabrication method
US6337510B1 (en) * 2000-11-17 2002-01-08 Walsin Advanced Electronics Ltd Stackable QFN semiconductor package
US20030025183A1 (en) * 2001-08-01 2003-02-06 Fairchild Semiconductor Corporation Packaged semiconductor device and method of manufacture using shaped die
WO2003083908A2 (en) 2002-03-29 2003-10-09 Fairchild Semiconductor, Inc. Packaging system for semiconductor devices
US6717260B2 (en) * 2001-01-22 2004-04-06 International Rectifier Corporation Clip-type lead frame for source mounted die

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3138159B2 (en) * 1994-11-22 2001-02-26 シャープ株式会社 Semiconductor device, semiconductor device package, and semiconductor device replacement method
US5530284A (en) * 1995-03-06 1996-06-25 Motorola, Inc. Semiconductor leadframe structure compatible with differing bond wire materials
US5894108A (en) 1997-02-11 1999-04-13 National Semiconductor Corporation Plastic package with exposed die
US5925384A (en) * 1997-04-25 1999-07-20 Micron Technology, Inc. Manual pellet loader for Boschman automolds
KR100246366B1 (en) * 1997-12-04 2000-03-15 김영환 Area array type semiconductor package and fabrication method of the same
US6249041B1 (en) * 1998-06-02 2001-06-19 Siliconix Incorporated IC chip package with directly connected leads
KR100293815B1 (en) * 1998-06-30 2001-07-12 박종섭 Stacked Package
JP4260263B2 (en) * 1999-01-28 2009-04-30 株式会社ルネサステクノロジ Semiconductor device
JP3871486B2 (en) * 1999-02-17 2007-01-24 株式会社ルネサステクノロジ Semiconductor device
JP4408475B2 (en) * 1999-02-23 2010-02-03 三洋電機株式会社 Semiconductor devices that do not use bonding wires
US6265761B1 (en) * 1999-05-07 2001-07-24 Maxim Integrated Products, Inc. Semiconductor devices with improved lead frame structures
US6307755B1 (en) * 1999-05-27 2001-10-23 Richard K. Williams Surface mount semiconductor package, die-leadframe combination and leadframe therefor and method of mounting leadframes to surfaces of semiconductor die
JP4077118B2 (en) * 1999-06-25 2008-04-16 富士通株式会社 Semiconductor device manufacturing method and semiconductor device manufacturing mold
US6448110B1 (en) * 1999-08-25 2002-09-10 Vanguard International Semiconductor Corporation Method for fabricating a dual-chip package and package formed
JP3215686B2 (en) * 1999-08-25 2001-10-09 株式会社日立製作所 Semiconductor device and manufacturing method thereof
US6198163B1 (en) * 1999-10-18 2001-03-06 Amkor Technology, Inc. Thin leadframe-type semiconductor package having heat sink with recess and exposed surface
US6744124B1 (en) * 1999-12-10 2004-06-01 Siliconix Incorporated Semiconductor die package including cup-shaped leadframe
US6528880B1 (en) * 2001-06-25 2003-03-04 Lovoltech Inc. Semiconductor package for power JFET having copper plate for source and ribbon contact for gate
JP3868777B2 (en) * 2001-09-11 2007-01-17 株式会社東芝 Semiconductor device

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4653993A (en) * 1982-08-19 1987-03-31 Boschman Kleinpenning Beheer B.V. Apparatus for encapsulating electronic components in plastic material
US5202849A (en) * 1989-10-20 1993-04-13 Fujitsu Limited Dynamic semiconductor memory device
US5925934A (en) * 1995-10-28 1999-07-20 Institute Of Microelectronics Low cost and highly reliable chip-sized package
US5844315A (en) 1996-03-26 1998-12-01 Motorola Corporation Low-profile microelectronic package
US6077724A (en) 1998-09-05 2000-06-20 First International Computer Inc. Multi-chips semiconductor package and fabrication method
US6337510B1 (en) * 2000-11-17 2002-01-08 Walsin Advanced Electronics Ltd Stackable QFN semiconductor package
US6717260B2 (en) * 2001-01-22 2004-04-06 International Rectifier Corporation Clip-type lead frame for source mounted die
US20030025183A1 (en) * 2001-08-01 2003-02-06 Fairchild Semiconductor Corporation Packaged semiconductor device and method of manufacture using shaped die
WO2003083908A2 (en) 2002-03-29 2003-10-09 Fairchild Semiconductor, Inc. Packaging system for semiconductor devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9536800B2 (en) 2013-12-07 2017-01-03 Fairchild Semiconductor Corporation Packaged semiconductor devices and methods of manufacturing

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DE10392461T5 (en) 2005-09-29
TW200401413A (en) 2004-01-16
US20030214019A1 (en) 2003-11-20
CN1653604A (en) 2005-08-10
WO2003083908A2 (en) 2003-10-09
US7579680B2 (en) 2009-08-25
AU2003226134A8 (en) 2003-10-13
JP2005522028A (en) 2005-07-21
JP4485210B2 (en) 2010-06-16
CN100466209C (en) 2009-03-04
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WO2003083908A3 (en) 2004-03-25
AU2003226134A1 (en) 2003-10-13

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