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US6700160B1 - Double-diffused MOS (DMOS) power transistor with a channel compensating implant - Google Patents

Double-diffused MOS (DMOS) power transistor with a channel compensating implant Download PDF

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Publication number
US6700160B1
US6700160B1 US09/690,263 US69026300A US6700160B1 US 6700160 B1 US6700160 B1 US 6700160B1 US 69026300 A US69026300 A US 69026300A US 6700160 B1 US6700160 B1 US 6700160B1
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well
type
semiconductor
channel region
substrate
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US09/690,263
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Steven L. Merchant
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Texas Instruments Inc
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Texas Instruments Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 

Definitions

  • the present invention relates generally to semiconductor devices, and more particularly to a double-diffused MOS (DMOS) power transistor.
  • DMOS double-diffused MOS
  • V T threshold voltage
  • a low threshold voltage is attractive for ease of gate drive and low source-to-drain on-state resistance, necessitating a body region 14 with a low surface concentration and/or short channel.
  • These attributes imply high body sheet resistance which makes the parasitic NPN bipolar transistor, shown at 16 with the p-body 12 as base, susceptible to easy turn-on.
  • Activation of the parasitic bipolar transistor results in restricting the transistor safe operating area (SOA) of the power transistor 10 , and renders the power transistor unusable for simultaneous high current/high voltage application, when, for example, switching off an inductive load.
  • SOA transistor safe operating area
  • the present invention achieves technical advantages as a double-diffused MOS (DMOS) power transistor having a channel compensating implant.
  • a shallow n-type channel compensating implant (NCCI) is employed to decouple the p-body surface concentration and pinched body sheet resistance.
  • NCCI shallow n-type channel compensating implant
  • the doping of the NCCI overcompensates the lighter doped portion of the graded p-body, making it n-type. This results in partial compensation of the heavy doped p-body near the transistor n+source, achieving a shorter, more lightly doped channel with the same heavy doped p-body beneath the n+transistor source.
  • the power transistor of the present invention gives a more favorable trade-off between threshold voltage/on-state resistance and safe operating area.
  • the NCCI allows a larger fraction of the transistor bias voltage to be supported on the thin gate oxide proximate the transistor gate.
  • the present invention achieves further technical advantages as it can be fabricated using a self-aligned technique with a channel length that is insensitive to lithography techniques.
  • FIG. 1 is a side sectional view of a conventional DMOS power transistor formed with a single p-body implant and having a parasitic NPN bipolar transistor resulting in a restricted safe operating area (SOA);
  • SOA restricted safe operating area
  • FIG. 2 is a side sectional view of an improved DMOS power transistor according to the present invention including a shallow n-type channel compensating implant (NCCI); and
  • FIG. 3 is a numerical simulation showing the improved off-state breakdown voltage using the NCCI in the DMOS power transistor of FIG. 2 .
  • a shallow n-type channel compensating (NCCI) implant 24 is employed, as shown in FIG. 2 .
  • the doping of the NCCI 24 is such that it overcompensates the lighter doped portion of the graded p-body, making it n-type.
  • the heavy doped upper portion of the p-body 12 near the n+source is partially compensated. The result is a shorter, more lightly doped channel 22 while retaining the same heavy p-body doping beneath the n+transistor source.
  • SOA safe operating area
  • the heavy doped p-body well 12 may have a doping of 1 ⁇ 10 17 to 5 ⁇ 10 18 /cm 3 and a depth of 0.7 to 2 um, a depth of 0.7 to 2 um, with the n+source well 26 having a doping of 0.1 to 0.5 um, and the n-well 28 having a doping of 8 ⁇ 10 15 to 2 ⁇ 10 17 /cm 3 .
  • the NCCI 24 may preferably have a doping of 1 ⁇ 10 17 to 1 ⁇ 10 18 /cm 3 , a depth of 0.1 to 0.6 um, and a width of 0.5 to 5 um, with the NCCI 24 overlapping and overcompensating the upper shallow portion of the heavy doped p-body 12 as shown This example would have a pinched body resistance in the body region 12 of 1 to 5 kohm/sq.
  • the transistor gate terminal is shown at 30 and may be formed of polysilicon. During the semiconductor fabrication process, the NCCI 24 is diffused after the FOX step, but before the deposition and etching of the polysilicon gate 30 .
  • NCCI 24 also improves the off-state breakdown voltage BV DSS .
  • the NCCI implant 24 allows a larger fraction of the gate bias voltage V T to be supported on gate 30 on the thin gate oxide 32 .
  • the region of maximum impact ionization shifts from the silicon/oxide surface to the body/well junction, which may be an advantage for robustness.
  • the present invention has an advantage over the use of a conventional very deep p-type diffusion because it can be fabricated using a self-aligned technique so the channel length is insensitive to lithography.
  • the conventional deep p-type diffusion must be offset from the p-body to avoid raising the surface (channel) concentration, and it is difficult to accurately put the deep p-type diffusion where it is needed (under the n+source) without influencing the surface concentration.
  • Retrograde profiles require expensive MeV ion implanters.

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

An improved DMOS power transistor (20) with a single p-body implant (12) and including an n-type channel compensating implant (NCCI) (24). The improved DMOS power transistor (20) provides a more favorable trade-off between threshold voltage (VT) and on-state resistance, while increasing the safe operating area (SOA). The NCCI (24) also improves the off-state breakdown voltage, and allows a larger fraction of the gate bias voltage to be supported on the thin gate oxide (32). The present invention can be fabricated using self-aligned fabrication techniques so that the channel length (22) is insensitive to lithography equipment.

Description

FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices, and more particularly to a double-diffused MOS (DMOS) power transistor.
BACKGROUND OF THE INVENTION
In a conventional DMOS power transistor 10 formed with a single p-body implant 12, as shown in FIG. 1, a trade-off exists between the threshold voltage (VT) and the pinched-body sheet resistance. A low threshold voltage is attractive for ease of gate drive and low source-to-drain on-state resistance, necessitating a body region 14 with a low surface concentration and/or short channel. These attributes imply high body sheet resistance which makes the parasitic NPN bipolar transistor, shown at 16 with the p-body 12 as base, susceptible to easy turn-on. Activation of the parasitic bipolar transistor results in restricting the transistor safe operating area (SOA) of the power transistor 10, and renders the power transistor unusable for simultaneous high current/high voltage application, when, for example, switching off an inductive load.
Other known ways of dealing with this trade-off are to use of a very deep p-type diffusion in addition to the p-body diffusion, and to use high energy MeV ion implantation to form a retrograde body.
SUMMARY OF THE INVENTION
The present invention achieves technical advantages as a double-diffused MOS (DMOS) power transistor having a channel compensating implant. A shallow n-type channel compensating implant (NCCI) is employed to decouple the p-body surface concentration and pinched body sheet resistance. The doping of the NCCI overcompensates the lighter doped portion of the graded p-body, making it n-type. This results in partial compensation of the heavy doped p-body near the transistor n+source, achieving a shorter, more lightly doped channel with the same heavy doped p-body beneath the n+transistor source. The power transistor of the present invention gives a more favorable trade-off between threshold voltage/on-state resistance and safe operating area. The NCCI allows a larger fraction of the transistor bias voltage to be supported on the thin gate oxide proximate the transistor gate. The present invention achieves further technical advantages as it can be fabricated using a self-aligned technique with a channel length that is insensitive to lithography techniques.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a side sectional view of a conventional DMOS power transistor formed with a single p-body implant and having a parasitic NPN bipolar transistor resulting in a restricted safe operating area (SOA);
FIG. 2 is a side sectional view of an improved DMOS power transistor according to the present invention including a shallow n-type channel compensating implant (NCCI); and
FIG. 3 is a numerical simulation showing the improved off-state breakdown voltage using the NCCI in the DMOS power transistor of FIG. 2.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring now to FIG. 2, there is shown at 20 an improved power transistor suited for both high current/high voltage applications. In order to decouple the p-body surface concentration of the p-body well 12 and pinched body sheet resistance of channel region 22, a shallow n-type channel compensating (NCCI) implant 24 is employed, as shown in FIG. 2. The doping of the NCCI 24 is such that it overcompensates the lighter doped portion of the graded p-body, making it n-type. The heavy doped upper portion of the p-body 12 near the n+source is partially compensated. The result is a shorter, more lightly doped channel 22 while retaining the same heavy p-body doping beneath the n+transistor source. This gives the power transistor 20 a more favorable trade-off between threshold voltage VT/on-state resistance and safe operating area (SOA).
In one preferred embodiment, as shown in FIG. 2, the heavy doped p-body well 12 may have a doping of 1×1017 to 5×1018/cm3 and a depth of 0.7 to 2 um, a depth of 0.7 to 2 um, with the n+source well 26 having a doping of 0.1 to 0.5 um, and the n-well 28 having a doping of 8×1015 to 2×1017/cm3. The NCCI 24 may preferably have a doping of 1×1017 to 1×1018/cm3, a depth of 0.1 to 0.6 um, and a width of 0.5 to 5 um, with the NCCI 24 overlapping and overcompensating the upper shallow portion of the heavy doped p-body 12 as shown This example would have a pinched body resistance in the body region 12 of 1 to 5 kohm/sq. The transistor gate terminal is shown at 30 and may be formed of polysilicon. During the semiconductor fabrication process, the NCCI 24 is diffused after the FOX step, but before the deposition and etching of the polysilicon gate 30.
Numerical simulation, displayed in FIG. 3, shows that the NCCI 24 also improves the off-state breakdown voltage BVDSS. The NCCI implant 24 allows a larger fraction of the gate bias voltage VT to be supported on gate 30 on the thin gate oxide 32. For a high NCCI dose, the region of maximum impact ionization shifts from the silicon/oxide surface to the body/well junction, which may be an advantage for robustness.
The present invention has an advantage over the use of a conventional very deep p-type diffusion because it can be fabricated using a self-aligned technique so the channel length is insensitive to lithography. In contrast, the conventional deep p-type diffusion must be offset from the p-body to avoid raising the surface (channel) concentration, and it is difficult to accurately put the deep p-type diffusion where it is needed (under the n+source) without influencing the surface concentration. Retrograde profiles require expensive MeV ion implanters.
Though the invention has been described with respect to a specific preferred embodiment, many variations and modifications will become apparent to those skilled in the art upon reading the present application. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications. For instance an NMOS transistor is shown and described in detail, but the principle of using a channel compensating implant could be employed in a PMOS transistor if desired using a p-type implant (PCCI).

Claims (16)

I claim:
1. A semiconductor MOS transistor, comprising:
a substrate of a first type;
a first well defined on said substrate, said first well being of a second type;
a second well defined in said first well, said second well being of said first type;
a third well defined in said second well, said third well being of said second type, a surface portion of said second well located between said first well and said third well forming a channel region of said semiconductor MOS transistor;
a second well defined in said first well, said second well being of said first type;
a third well defined in said second well, said third well being of said second type, a surface portion of said second well located between said first well and said third well forming a channel region of said semiconductor MOS transistor;
a channel compensating implant (CCI) defined in said first well and in a portion of said channel region of said second well to decouple said channel region from said second well;
a thin gate oxide formed over the channel region of said second well, said channel compensating implant being adjacent to said thin ate oxide; and
a gate terminal defined over said thin gate oxide.
2. The semiconductor as specified in claim 1 wherein said substrate is p-substrate, said first well is n-type, said second well is p-type, and said third well is n-type.
3. The semiconductor as specified in claim 2 wherein said CCI is n-type and forms a n-type channel compensating implant (NCCI).
4. The semiconductor as specified in claim 3 wherein said p-type second well has a doping of at least 1×1017/cm3.
5. The semiconductor as specified in claim 4 wherein said NCCI has a doping of no more than 1×1018/cm3.
6. A semiconductor MOS transistor, comprising:
a substrate of a first type;
a first well defined on said substrate, said first well being of a second type;
a second well defined in said first well, said second well being of said first type;
a third well defined in said second well, said third well being of said second type, a surface portion of said second well located between said first well and said third well forming a channel region of said semiconductor MOS transistor;
a second well defined in said first well, said second well being of said first type;
a third well defined in said second well, said third well being of said second type, a surface portion of said second well located between said first well and said third well forming a channel region of said semiconductor MOS transistor;
a channel compensating implant (CCI) defined in said first well and in a portion of said channel region of said second well to decouple said channel region from said second well;
a thin gate oxide formed over the channel region of said second well; and
a gate terminal defined over said thin gate oxide,
wherein said CCI compensates upper portion of said second well.
7. The semiconductor as specified in claim 6 wherein said substrate is n-substrate, said first well is p-type, said second well is n-type, said third well is p-type, and said CCI is p-type forming an PCCI.
8. The semiconductor as specified in claim 6 wherein said substrate is p-substrate, said first well is n-type, said second well is p-type, and said third well is n-type.
9. The semiconductor as specified in claim 8 wherein said CCI is n-type and forms a n-type channel compensating implant (NCCI).
10. The semiconductor as specified in claim 9 wherein said p-type second well has a doping of at least 1×1017/cm3.
11. The semiconductor as specified in claim 10 wherein said NCCI has a doping of no more than 1×1018/cm3.
12. The semiconductor as specified in claim 11 further comprising a fourth well defined in said first well, wherein said NCCI comprises a portion of a channel between said third well and said fourth well having a pinched body sheet resistance of no more than 5 kohm/sq.
13. The semiconductor as specified in claim 12 wherein said third well forms a source terminal, and said fourth well forms a drain terminal.
14. A semiconductor MOS transistor, comprising:
a substrate of a first type;
a first well defined on said substrate, said first well being of a second type;
a second well defined in said first well, said second well being of said first type;
a third well defined in said second well, said third well being of said second type, a surface portion of said second well located between said first well and said third well forming a channel region of said semiconductor MOS transistor;
a second well defined in said first well, said second well being of said first type;
a third well defined in said second well, said third well being of said second type, a surface portion of said second well located between said first well and said third well forming a channel region of said semiconductor MOS transistor;
a channel compensating implant (CCI) defined in said first well and in a portion of said channel region of said second well to decouple said channel region from said second well;
a thin gate oxide formed over the channel region of said second well; and
a gate terminal defined over said thin gate oxide,
wherein said substrate is n-substrate, said first well is p-type, said second well is n-type, said third well is p-type, and said CCI is p-type forming an PCCI.
15. A semiconductor MOS transistor, comprising:
a substrate of a first type;
a first well defined on said substrate, said first well being of a second type;
a second well defined in said first well, said second well being of said first type;
a third well defined in said second well, said third well being of said second type, a surface portion of said second well located between said first well and said third well forming a channel region of said semiconductor MOS transistor;
a second well defined in said first well, said second well being of said first type;
a third well defined in said second well, said third well being of said second type, a surface portion of said second well located between said first well and said third well forming a channel region of said semiconductor MOS transistor;
a channel compensating implant (CCI) defined in said first well and in a portion of said channel region of said second well to decouple said channel region from said second well;
a thin gate oxide formed over the channel region of said second well; and
a gate terminal defined over said thin ate oxide,
wherein said substrate is p-substrate, said first well is n-type, said second well is p-type, and said third well is n-type,
wherein said CCI is n-type and forms a n-type channel compensating implant (NCCI),
further comprising a fourth well defined in said first well, wherein said NCCI comprises a portion of a channel between said third well and said fourth well having a pinched body sheet resistance of no more than 5 kohm/sq.
16. The semiconductor as specified in claim 15 wherein said third well forms a source terminal, and said fourth well forms a drain terminal.
US09/690,263 2000-10-17 2000-10-17 Double-diffused MOS (DMOS) power transistor with a channel compensating implant Expired - Lifetime US6700160B1 (en)

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US20110147838A1 (en) * 2009-12-17 2011-06-23 Infineon Technologies Ag Tunnel Field Effect Transistors
JP2012156388A (en) * 2011-01-27 2012-08-16 Fujitsu Semiconductor Ltd Mos transistor, and method of manufacturing semiconductor integrated circuit device
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US8900954B2 (en) 2011-11-04 2014-12-02 International Business Machines Corporation Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening
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USRE41764E1 (en) 1999-06-11 2010-09-28 Thomas Skotnicki Semiconductor device with compensated threshold voltage and method for making same
JP2009239096A (en) * 2008-03-27 2009-10-15 Renesas Technology Corp Semiconductor device
US10374068B2 (en) 2009-12-17 2019-08-06 Infineon Technologies Ag Tunnel field effect transistors
US20110147838A1 (en) * 2009-12-17 2011-06-23 Infineon Technologies Ag Tunnel Field Effect Transistors
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DE112010005265B4 (en) * 2010-02-15 2020-09-10 Texas Instruments Incorporated Method of making a depletion mode DMOS transistor
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US9159825B2 (en) 2010-10-12 2015-10-13 Silanna Semiconductor U.S.A., Inc. Double-sided vertical semiconductor device with thinned substrate
US8928068B2 (en) 2010-10-12 2015-01-06 Silanna Semiconductor U.S.A., Inc. Vertical semiconductor device with thinned substrate
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US8981472B2 (en) 2011-01-27 2015-03-17 Fujitsu Semiconductor Limited MOS transistor and fabrication method of semiconductor integrated circuit device
JP2012156388A (en) * 2011-01-27 2012-08-16 Fujitsu Semiconductor Ltd Mos transistor, and method of manufacturing semiconductor integrated circuit device
CN102646706A (en) * 2011-02-17 2012-08-22 立锜科技股份有限公司 High voltage component and manufacturing method thereof
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US8900954B2 (en) 2011-11-04 2014-12-02 International Business Machines Corporation Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening
US9478615B2 (en) 2011-11-04 2016-10-25 Globalfoundries Inc. Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening
US9324861B2 (en) 2012-08-30 2016-04-26 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device
US20140091369A1 (en) * 2012-09-28 2014-04-03 United Microelectronics Corp. High voltage metal-oxide-semiconductor transistor device
US9196717B2 (en) * 2012-09-28 2015-11-24 United Microelectronics Corp. High voltage metal-oxide-semiconductor transistor device
US20140091389A1 (en) * 2012-09-28 2014-04-03 United Microelectronics Corp. High voltage metal-oxide-semiconductor transistor device
US8829611B2 (en) * 2012-09-28 2014-09-09 United Microelectronics Corp. High voltage metal-oxide-semiconductor transistor device
US9331098B2 (en) 2013-03-27 2016-05-03 Qualcomm Switch Corp. Semiconductor-on-insulator integrated circuit with reduced off-state capacitance
US10211167B2 (en) 2013-03-27 2019-02-19 Qualcomm Incorporated Methods of making integrated circuit assembly with faraday cage and including a conductive ring
US9530796B2 (en) 2013-03-27 2016-12-27 Qualcomm Incorporated Semiconductor-on-insulator integrated circuit with interconnect below the insulator
US9478507B2 (en) 2013-03-27 2016-10-25 Qualcomm Incorporated Integrated circuit assembly with faraday cage
US9466536B2 (en) 2013-03-27 2016-10-11 Qualcomm Incorporated Semiconductor-on-insulator integrated circuit with back side gate

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