US6509226B1 - Process for protecting array top oxide - Google Patents
Process for protecting array top oxide Download PDFInfo
- Publication number
- US6509226B1 US6509226B1 US09/670,741 US67074100A US6509226B1 US 6509226 B1 US6509226 B1 US 6509226B1 US 67074100 A US67074100 A US 67074100A US 6509226 B1 US6509226 B1 US 6509226B1
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- United States
- Prior art keywords
- polysilicon
- layer
- top oxide
- oxide
- nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- 238000000034 method Methods 0.000 title claims abstract description 13
- 150000004767 nitrides Chemical class 0.000 claims abstract description 41
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 41
- 229920005591 polysilicon Polymers 0.000 claims abstract description 40
- 238000002955 isolation Methods 0.000 claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- 239000010703 silicon Substances 0.000 claims abstract description 17
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000004020 conductor Substances 0.000 claims abstract description 9
- 238000003491 array Methods 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 abstract description 11
- 238000007254 oxidation reaction Methods 0.000 abstract description 11
- 230000008021 deposition Effects 0.000 abstract description 6
- 239000007943 implant Substances 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
Definitions
- the present invention generally relates to integrated circuit (IC) memory devices and, more particularly, to a process for protecting the array top oxide in vertical metal oxide semiconductor field effect transistor (MOSFET) dynamic random access memory (DRAM) arrays.
- IC integrated circuit
- MOSFET vertical metal oxide semiconductor field effect transistor
- DRAM dynamic random access memory
- ES etch stop
- nitride liner removal of the ES (etch stop) nitride liner from the array results in thinning of the underlying top oxide which is intended to provide insulation between the silicon substrate and the word lines to be formed subsequently. Thinning of the top oxide results in a higher than desired incidence of word line to substrate shorts and/or leakage. Furthermore, thinning of the top oxide may result in the formation of divots in the array gate conductor (GC) polycrystalline silicon (polysilicon) in the top portion of the deep trench, due to gate stack overetch. Divots in the array GC polysilicon which are deeper than the bit line diffusion (XA) junction result in non-functional array MOSFETs due to gate underlap.
- GC array gate conductor
- XA bit line diffusion
- processing of a DRAM device containing vertical MOSFET arrays proceeds in a normal fashion through planarization of the array gate conductor (GC) polysilicon of the vertical MOSFET to the top surface of the top oxide which provides array top insulation. Then a thin polysilicon or amorphous silicon layer is deposited (new layer) over the planarized surface and the normal second pad nitride (active area (AA) pad nitride) and tetraethyl orthosilicate (TEOS) stack is deposited.
- the AA mask is used to open the pad layer to the silicon surface, and standard shallow trench isolation (STI) etching is used to form isolation trenches.
- STI shallow trench isolation
- the isolation trenches are filled with high density plasma (HDP) oxide and then planarized to the top surface of the AA pad nitride (the TEOS layer overlying t he second pad nitride having been polished off).
- HDP high density plasma
- the AA pad nitride is stripped, with the thin silicon layer serving as an etch stop protecting the underlying TTO.
- the standard etch support (ES) nitride liner is then deposited, and the process continues with the patterning of the ES mask which opens the support areas.
- the ES nitride, thin polysilicon layer and TTO are etched from the exposed areas.
- a sacrificial oxidation is applied along with well implants, support gate oxidation and support gate polysilicon deposition.
- the support gate polysilicon is opened in t he array.
- the ES nitride is removed selective to the underlying silicon layer, protecting the TTO.
- the gate stack is deposited and patterned and the process continues to completion.
- FIG. 1 is a cross-sectional view showing a thin layer of polysilicon or amorphous silicon deposited following array gate CMP to the top surface of the top oxide and following formation of the isolation trenches (ITs);
- FIG. 2 is a cross-sectional view showing the AA pad nitride stripped and the standard ES nitride layer deposited;
- FIG. 3 is a cross-sectional view showing the patterning of the ES mask followed by the ES nitride, thin polysilicon layer and TTO is etched from the exposed areas;
- FIG. 4 is a cross-sectional view showing the results of sacrificial oxidation, well implants, support gate oxidation and first layer of polysilicon deposition which serves as a portion of the gate conductor for the support MOSFETs;
- FIG. 5 is a cross-sectional view showing the opening the first layer polysilicon using the EA mask and removal of the ES nitride selective to the underlying silicon layer.
- FIG. 1 there is shown a cross-sectional view of a section of a DRAM containing vertical MOSFET arrays formed in a silicon substrate 10 .
- the substrate 10 has an n-buried plate 11 through which two trenches 12 and 13 have been formed from the top surface of the substrate.
- a collar oxide 14 is formed within each of the trenches to just below the n-buried plate 11 , and then the trenches are filled with polysilicon 15 which acts as the conductor for the storage node.
- a storage node insulator Prior to deposition of polysilicon 15 , a storage node insulator is formed.
- a top oxide 16 deposited on the surface of the substrate 10 extends into the trenches 12 and 13 to cover the tops of the polysilicon 15 .
- polysilicon 17 which serves as the gate conductors (GC) for the DRAM cell.
- GC gate conductors
- the processing of the DRAM proceeds in a normal fashion through planarization, by chemical-mechanical polish (CMP), of the array GC polysilicon 17 of vertical MOSFETs to the top surface of the top oxide 16 , which provides array top insulation. Then a thin polysilicon or amorphous silicon layer 18 is deposited over the planarized surface.
- This new layer of polysilicon or amorphous silicon layer 18 is a new layer in the process and serves as an etch stop (for overlying nitride layers) and a buffer layer, protecting the underlying top oxide 16 from damage and erosion due to subsequent processing.
- the normal second pad nitride 19 (AA pad nitride) and TEOS stack is deposited.
- the AA mask is used to open the pad layer to the silicon surface and standard STI (shallow trench isolation) etching is used to form isolation trenches (IT) 20 .
- An AA oxidation is performed, the isolation trenches 20 are filled with HDP oxide and then planarized to the top surface of the AA pad nitride.
- the AA pad nitride is stripped, with the thin silicon layer serving as an etch stop which protects the underlying TTO 16 .
- the standard ES nitride liner 21 is deposited.
- the process continues with the patterning of the ES mask 22 which opens the support areas.
- the ES nitride 21 , thin polysilicon layer 18 and top oxide 16 are etched from the exposed areas, in the supports, as shown in FIG. 3 .
- the process continues with sacrificial oxidation, well implants, support gate oxidation and the first layer polysilicon 23 deposition, as shown in FIG. 4 .
- This first layer of polysilicon serves as a portion of the gate conductor for the support MOSFETs.
- the EA mask 24 the first layer polysilicon 23 is opened in the array.
- ES nitride is removed selective to the underlying thin silicon layer, protecting the TTO, as shown in FIG. 5 .
- the EA resist is stripped.
- the gate stack is deposited and patterned, and the standard process continues to completion.
- An additional embodiment would deposit the thin silicon barrier layer following IT planarization instead of following array GC planarization.
- This alternative embodiment has the additional advantage of protecting the STI from recess during subsequent removal of the ES nitride liner layer.
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
Abstract
Processing of a DRAM device containing vertical MOSFET arrays proceeds through planarization of the array gate conductor (GC) polysilicon of the vertical MOSFET to the top surface of the top oxide. A thin polysilicon layer is deposited over the planarized surface and an active area (M) pad nitride and tetraethyl orthosilicate (TEOS) stack is deposited. The M mask is used to open the pad layer to the silicon surface, and shallow trench isolation (STI) etching is used to form isolation trenches. An AA oxidation is performed, the isolation trenches are filled with high density plasma (HDP) oxide and planarized to the top surface of the AA pad nitride. Following isolation trench (IT) planarization, the AA pad nitride is stripped, with the thin silicon layer serving as an etch stop protecting the underlying top oxide. The etch support (ES) nitride liner is deposited, and the ES mask is patterned to open the support areas. The ES nitride, thin polysilicon layer and top oxide are etched from the exposed areas. A sacrificial oxidation is applied along with well implants, support gate oxidation and support gate polysilicon deposition. Using the etch array (EA) mask, the support gate polysilicon is opened in the array. The ES nitride is removed selective to the underlying silicon layer, protecting the top oxide. The gate stack is deposited and patterned and the process continues to completion.
Description
The present invention generally relates to integrated circuit (IC) memory devices and, more particularly, to a process for protecting the array top oxide in vertical metal oxide semiconductor field effect transistor (MOSFET) dynamic random access memory (DRAM) arrays.
In the present process for memory cell fabrication in vertical MOSFET DRAM arrays, removal of the ES (etch stop) nitride liner from the array results in thinning of the underlying top oxide which is intended to provide insulation between the silicon substrate and the word lines to be formed subsequently. Thinning of the top oxide results in a higher than desired incidence of word line to substrate shorts and/or leakage. Furthermore, thinning of the top oxide may result in the formation of divots in the array gate conductor (GC) polycrystalline silicon (polysilicon) in the top portion of the deep trench, due to gate stack overetch. Divots in the array GC polysilicon which are deeper than the bit line diffusion (XA) junction result in non-functional array MOSFETs due to gate underlap.
It is therefore an object of the present invention to provide a protective etch stop layer under the etch supports (ES) nitride liner.
According to the invention, processing of a DRAM device containing vertical MOSFET arrays proceeds in a normal fashion through planarization of the array gate conductor (GC) polysilicon of the vertical MOSFET to the top surface of the top oxide which provides array top insulation. Then a thin polysilicon or amorphous silicon layer is deposited (new layer) over the planarized surface and the normal second pad nitride (active area (AA) pad nitride) and tetraethyl orthosilicate (TEOS) stack is deposited. The AA mask is used to open the pad layer to the silicon surface, and standard shallow trench isolation (STI) etching is used to form isolation trenches. An AA oxidation is perfomed, the isolation trenches are filled with high density plasma (HDP) oxide and then planarized to the top surface of the AA pad nitride (the TEOS layer overlying t he second pad nitride having been polished off). Following isolation trench (IT) planarization, the AA pad nitride is stripped, with the thin silicon layer serving as an etch stop protecting the underlying TTO. The standard etch support (ES) nitride liner is then deposited, and the process continues with the patterning of the ES mask which opens the support areas. The ES nitride, thin polysilicon layer and TTO are etched from the exposed areas. Next, a sacrificial oxidation is applied along with well implants, support gate oxidation and support gate polysilicon deposition. Then, using the etch array (EA) mask, the support gate polysilicon is opened in t he array. The ES nitride is removed selective to the underlying silicon layer, protecting the TTO. The gate stack is deposited and patterned and the process continues to completion.
The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:
FIG. 1 is a cross-sectional view showing a thin layer of polysilicon or amorphous silicon deposited following array gate CMP to the top surface of the top oxide and following formation of the isolation trenches (ITs);
FIG. 2 is a cross-sectional view showing the AA pad nitride stripped and the standard ES nitride layer deposited;
FIG. 3 is a cross-sectional view showing the patterning of the ES mask followed by the ES nitride, thin polysilicon layer and TTO is etched from the exposed areas;
FIG. 4 is a cross-sectional view showing the results of sacrificial oxidation, well implants, support gate oxidation and first layer of polysilicon deposition which serves as a portion of the gate conductor for the support MOSFETs; and
FIG. 5 is a cross-sectional view showing the opening the first layer polysilicon using the EA mask and removal of the ES nitride selective to the underlying silicon layer.
Referring now to the drawings, and more particularly to FIG. 1, there is shown a cross-sectional view of a section of a DRAM containing vertical MOSFET arrays formed in a silicon substrate 10. The substrate 10 has an n-buried plate 11 through which two trenches 12 and 13 have been formed from the top surface of the substrate. A collar oxide 14 is formed within each of the trenches to just below the n-buried plate 11, and then the trenches are filled with polysilicon 15 which acts as the conductor for the storage node. Prior to deposition of polysilicon 15, a storage node insulator is formed. A top oxide 16 deposited on the surface of the substrate 10 extends into the trenches 12 and 13 to cover the tops of the polysilicon 15. Above the top oxide 16 on the surface of the substrate and in the trenches is deposited polysilicon 17 which serves as the gate conductors (GC) for the DRAM cell. Prior to deposition of polysilicon 17, a gate oxide is formed. The top oxide 16 within the trenches 12 and 13 thus serves as an insulating layer between the GC and the storage node polysilicon.
The processing of the DRAM proceeds in a normal fashion through planarization, by chemical-mechanical polish (CMP), of the array GC polysilicon 17 of vertical MOSFETs to the top surface of the top oxide 16, which provides array top insulation. Then a thin polysilicon or amorphous silicon layer 18 is deposited over the planarized surface. This new layer of polysilicon or amorphous silicon layer 18 is a new layer in the process and serves as an etch stop (for overlying nitride layers) and a buffer layer, protecting the underlying top oxide 16 from damage and erosion due to subsequent processing. The normal second pad nitride 19 (AA pad nitride) and TEOS stack is deposited. The AA mask is used to open the pad layer to the silicon surface and standard STI (shallow trench isolation) etching is used to form isolation trenches (IT) 20. An AA oxidation is performed, the isolation trenches 20 are filled with HDP oxide and then planarized to the top surface of the AA pad nitride.
Referring next to FIG. 2, following STI planarization, the AA pad nitride is stripped, with the thin silicon layer serving as an etch stop which protects the underlying TTO 16. Then the standard ES nitride liner 21 is deposited. The process continues with the patterning of the ES mask 22 which opens the support areas. The ES nitride 21, thin polysilicon layer 18 and top oxide 16 are etched from the exposed areas, in the supports, as shown in FIG. 3.
The process continues with sacrificial oxidation, well implants, support gate oxidation and the first layer polysilicon 23 deposition, as shown in FIG. 4. This first layer of polysilicon serves as a portion of the gate conductor for the support MOSFETs. Then, using the EA mask 24, the first layer polysilicon 23 is opened in the array. ES nitride is removed selective to the underlying thin silicon layer, protecting the TTO, as shown in FIG. 5. The EA resist is stripped. The gate stack is deposited and patterned, and the standard process continues to completion.
An additional embodiment would deposit the thin silicon barrier layer following IT planarization instead of following array GC planarization. This alternative embodiment has the additional advantage of protecting the STI from recess during subsequent removal of the ES nitride liner layer.
While the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.
Claims (3)
1. In a process for protecting an array top oxide layer in the manufacture of vertical metal oxide semiconductor field effect transistor (MOSFET) dynamic random access memory (DRAM) arrays in a silicon substrate, the improvement comprising the step of depositing a thin polysilicon or amorphous silicon layer over the top oxide layer which serves as an etch stop and protects the underlying top oxide layer from etch damage, and planarizing an array gate conductor (GC) polysilicon of the vertical MOSFET to the top surface of the top oxide prior to the depositing the thin polysilicon or amorphous silicon layer over the top oxide layer.
2. The process of claim 1 , further comprising the steps of:
depositing an active area (AA) pad nitride and tetraethyl orthosilicate (TEOS) stack over the thin polysilicon or amorphous silicon layer;
opening the AA pad nitride to the silicon surface of the substrate;
etching shallow trench isolation (STI) to form isolation trenches;
filling the isolation trenches with high density plasma (HDP) oxide; and
planarizing to the top surface of the AA pad nitride and stripping the AA pad nitride, with the thin polysilicon or amorphous silicon layer serving as an etch stop protecting the underlying top oxide thereby avoiding thinning of the top oxide and preventing word line to substrate shorts and/or leakage.
3. A process for protecting an array top oxide in the manufacture of vertical metal oxide semiconductor field effect transistor (MOSFET) dynamic access memory (DRAM) arrays in a silicon substrate, comprising the steps of:
planarizing an array gate conductor (GC) polysilicon of the vertical MOSFET to a top surface of the top oxide;
depositing a thin polysilicon layer over the planarized surface;
depositing an active area (AA) pad nitride mask and tetraethyl orthosilicate (TEOS) stack;
using the AA pad nitride mask to open a pad layer to the silicon surface of the substrate;
performing shallow trench isolation (STI) etching to form isolation trenches;
filling the isolation trenches with high density plasma (HDP) oxide and planarizing to a top surface of the AA pad nitride mask;
stripping the AA pad nitride mask, with the thin polysilicon layer serving as an etch stop protecting the underlying top oxide;
depositing an etch support (ES) nitride liner, patterning an ES mask to open support areas, and etching the ES nitride liner, thin polysilicon layer and top oxide from exposed areas; and
using an etch array (EA) mask, opening the support gate polysilicon in the array, and removing the ES nitride liner selective to the underlying polysilicon layer, protecting the top oxide.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/670,741 US6509226B1 (en) | 2000-09-27 | 2000-09-27 | Process for protecting array top oxide |
| PCT/US2001/026644 WO2002031878A2 (en) | 2000-09-27 | 2001-08-24 | Trench capacitor dram process with protected top oxide during sti etch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/670,741 US6509226B1 (en) | 2000-09-27 | 2000-09-27 | Process for protecting array top oxide |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US6509226B1 true US6509226B1 (en) | 2003-01-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US09/670,741 Expired - Lifetime US6509226B1 (en) | 2000-09-27 | 2000-09-27 | Process for protecting array top oxide |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6509226B1 (en) |
| WO (1) | WO2002031878A2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050014331A1 (en) * | 2003-07-14 | 2005-01-20 | Sheng-Wei Yang | Process for planarizing array top oxide in vertical mosfet dram arrays |
| US20050070108A1 (en) * | 2003-09-30 | 2005-03-31 | International Business Machines Corporation | Top oxide nitride liner integration scheme for vertical dram |
| US20060019443A1 (en) * | 2004-07-21 | 2006-01-26 | International Business Machines Corporation | Top-oxide-early process and array top oxide planarization |
| US20060226481A1 (en) * | 2005-04-08 | 2006-10-12 | International Business Machines Corporation | SIMPLIFIED VERTICAL ARRAY DEVICE DRAM/eDRAM INTEGRATION: METHOD AND STRUCTURE |
| US20090159947A1 (en) * | 2007-12-19 | 2009-06-25 | International Business Machines Corporation | SIMPLIFIED VERTICAL ARRAY DEVICE DRAM/eDRAM INTEGRATION |
| US20090174031A1 (en) * | 2008-01-07 | 2009-07-09 | International Business Machines Corporation | Dram having deep trench capacitors with lightly doped buried plates |
| US20090173980A1 (en) * | 2008-01-07 | 2009-07-09 | International Business Machines Corporation | Providing isolation for wordline passing over deep trench capacitor |
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| US6620677B1 (en) * | 2002-05-31 | 2003-09-16 | Infineon Technologies Ag | Support liner for isolation trench height control in vertical DRAM processing |
| US7742324B2 (en) | 2008-02-19 | 2010-06-22 | Micron Technology, Inc. | Systems and devices including local data lines and methods of using, making, and operating the same |
| US9190494B2 (en) | 2008-02-19 | 2015-11-17 | Micron Technology, Inc. | Systems and devices including fin field-effect transistors each having U-shaped semiconductor fin |
| US8866254B2 (en) | 2008-02-19 | 2014-10-21 | Micron Technology, Inc. | Devices including fin transistors robust to gate shorts and methods of making the same |
| US7915659B2 (en) | 2008-03-06 | 2011-03-29 | Micron Technology, Inc. | Devices with cavity-defined gates and methods of making the same |
| US8546876B2 (en) | 2008-03-20 | 2013-10-01 | Micron Technology, Inc. | Systems and devices including multi-transistor cells and methods of using, making, and operating the same |
| US7808042B2 (en) | 2008-03-20 | 2010-10-05 | Micron Technology, Inc. | Systems and devices including multi-gate transistors and methods of using, making, and operating the same |
| US7898857B2 (en) | 2008-03-20 | 2011-03-01 | Micron Technology, Inc. | Memory structure having volatile and non-volatile memory portions |
| US7969776B2 (en) | 2008-04-03 | 2011-06-28 | Micron Technology, Inc. | Data cells with drivers and methods of making and operating the same |
| US8076229B2 (en) | 2008-05-30 | 2011-12-13 | Micron Technology, Inc. | Methods of forming data cells and connections to data cells |
| US8148776B2 (en) | 2008-09-15 | 2012-04-03 | Micron Technology, Inc. | Transistor with a passive gate |
| US8294511B2 (en) | 2010-11-19 | 2012-10-23 | Micron Technology, Inc. | Vertically stacked fin transistors and methods of fabricating and operating the same |
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| US6897108B2 (en) * | 2003-07-14 | 2005-05-24 | Nanya Technology Corp. | Process for planarizing array top oxide in vertical MOSFET DRAM arrays |
| US20050014331A1 (en) * | 2003-07-14 | 2005-01-20 | Sheng-Wei Yang | Process for planarizing array top oxide in vertical mosfet dram arrays |
| US7091553B2 (en) | 2003-09-30 | 2006-08-15 | International Business Machines Corporation | Top oxide nitride liner integration scheme for vertical DRAM |
| US20050196919A1 (en) * | 2003-09-30 | 2005-09-08 | International Buisiness Machines Corporation | Top oxide nitride liner integration scheme for vertical DRAM |
| US6972266B2 (en) * | 2003-09-30 | 2005-12-06 | International Business Machines Corporation | Top oxide nitride liner integration scheme for vertical DRAM |
| US20050070108A1 (en) * | 2003-09-30 | 2005-03-31 | International Business Machines Corporation | Top oxide nitride liner integration scheme for vertical dram |
| US20060019443A1 (en) * | 2004-07-21 | 2006-01-26 | International Business Machines Corporation | Top-oxide-early process and array top oxide planarization |
| US7601646B2 (en) | 2004-07-21 | 2009-10-13 | International Business Machines Corporation | Top-oxide-early process and array top oxide planarization |
| US20060226481A1 (en) * | 2005-04-08 | 2006-10-12 | International Business Machines Corporation | SIMPLIFIED VERTICAL ARRAY DEVICE DRAM/eDRAM INTEGRATION: METHOD AND STRUCTURE |
| US7485910B2 (en) | 2005-04-08 | 2009-02-03 | International Business Machines Corporation | Simplified vertical array device DRAM/eDRAM integration: method and structure |
| US20090159947A1 (en) * | 2007-12-19 | 2009-06-25 | International Business Machines Corporation | SIMPLIFIED VERTICAL ARRAY DEVICE DRAM/eDRAM INTEGRATION |
| US20090174031A1 (en) * | 2008-01-07 | 2009-07-09 | International Business Machines Corporation | Dram having deep trench capacitors with lightly doped buried plates |
| US20090173980A1 (en) * | 2008-01-07 | 2009-07-09 | International Business Machines Corporation | Providing isolation for wordline passing over deep trench capacitor |
| US7705386B2 (en) | 2008-01-07 | 2010-04-27 | International Business Machines Corporation | Providing isolation for wordline passing over deep trench capacitor |
| US7923815B2 (en) | 2008-01-07 | 2011-04-12 | International Business Machines Corporation | DRAM having deep trench capacitors with lightly doped buried plates |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2002031878A3 (en) | 2002-10-31 |
| WO2002031878A2 (en) | 2002-04-18 |
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