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US6043529A - Semiconductor configuration with a protected barrier for a stacked cell - Google Patents

Semiconductor configuration with a protected barrier for a stacked cell Download PDF

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US6043529A
US6043529A US09/282,099 US28209999A US6043529A US 6043529 A US6043529 A US 6043529A US 28209999 A US28209999 A US 28209999A US 6043529 A US6043529 A US 6043529A
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layer
silicon nitride
barrier layer
contact hole
nitride layer
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US09/282,099
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Walter Hartner
Gunther Schindler
Carlos Mazure-Espejo
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Siemens AG
Qimonda AG
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Siemens AG
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures

Definitions

  • the present invention relates in general to the field of semiconductors, and specifically to a semiconductor configuration and a method for fabricating a semiconductor configuration including a stacked cell with a protected barrier.
  • the use of a dielectric having a large dielectric constant leads to a reduction in the area required for a capacitor with a corresponding capacitance, and thus to an increase in the integration level.
  • BST (Ba x ST 1-x )TiO 3 , "BST”, which has a dielectric constant of the order of magnitude of 400. It is obvious that BST permits a considerable increase in the integration level when it is used instead of the customary silicon dioxide or silicon nitride layers.
  • conventional storage elements such as, for example, a dynamic random memory (DRAM)
  • DRAM dynamic random memory
  • conventional storage elements use paraelectric materials, although these lose their charge, and consequently also the information stored with the charge, in the event of a supply voltage failure. Because of the leakage current that occurs in conventional storage elements of this type, the charge must be continually "refreshed” or rewritten to.
  • novel ferroelectric materials as a storage dielectric is desirable since this enables the fabrication of nonvolatile semiconductor memory configurations that do not lose their information in the event of a supply voltage failure and, in addition, do not have to be continually refreshed.
  • ferroelectric materials as a storage dielectric is intrinsically desirable in the case of semiconductor memory configurations, since it is then possible to achieve an increase in the integration level in conjunction with protection in respect to a supply voltage failure.
  • ferroelectric or else paraelectric materials in semiconductor memory configurations depends to a great extent on how these materials can be incorporated in an integrated semiconductor circuit configuration.
  • ferroelectric or paraelectric materials that have been taken into consideration heretofore are, in addition to the BST already mentioned, (Pb,Zr)TiO 3 (PZT), SrBi 2 Ta 2 O 9 (SBT), SrBi 2 (Ta,Nb)O 9 (SBTN) SrTiO 3 (ST), ferroelectric and paraelectric polymers, etc. and generally ferroelectric and paraelectric materials.
  • the interface between the plug and the electrode for example, oxidizes, which creates an electrical interruption.
  • FIG. 3 shows such a semiconductor configuration with a memory cell.
  • a dielectric insulator layer 2 made of silicon dioxide, for example, is applied to a semiconductor body 10 having a heavily doped region 9, and a hole 8 etched into the insulator layer.
  • This hole 8 is filled with a filler material or plug 1 made from tungsten or polycrystalline silicon.
  • a barrier layer 3 which is made from, for example, WN, TiWN, TaN, WC, etc.
  • the barrier layer 3 separates a lower electrode 5 made of platinum from the plug 1.
  • a paraelectric or ferroelectric dielectric 6 is situated on the lower electrode 5, and an upper electrode 7 is applied in turn to the dielectric.
  • the barrier layer 3 is oxidized, beginning in the region 11, and this can ultimately lead to an electrical interruption.
  • the oxidation advances from the region 11 along the interface 14 between the barrier layer 3 and the electrode 5 and along the interface 15 between the barrier layer 3 and the insulation layer 2.
  • dielectrics having a high dielectric constant or ferroelectrics have previously been deposited in planar fashion above a LOCOS region only after the completion of a conventional CMOS transistor structure.
  • a capacitor is provided above the LOCOS region.
  • the upper electrode of the capacitor is made from platinum, for example, and is connected to the source electrode of a MOS transistor.
  • the insulating layer of the capacitor is fabricated from a ferroelectric, and the second electrode (common plate), which is situated on a side of the ferroelectric opposite from the first electrode, is likewise fabricated from platinum, for example. SBT can be used as the dielectric.
  • the application of a capacitor above the LOCOS region has the advantage, however, that a sputtering or sol gel method can be used for fabricating the planar ferroelectric layer of the capacitor.
  • a sputtering or sol gel method can be used for fabricating the planar ferroelectric layer of the capacitor.
  • the diffusion of oxygen through the electrode, which is usually made from platinum no longer impairs the layer situated underneath, since an oxide is already present there.
  • ferroelectric layers may be applied directly above the electrically conductive plug, this leads to further oxidation and thus ultimately to insulation of the electrical connections.
  • a method for fabricating the semiconductor configuration is provided.
  • a semiconductor configuration for an integrated circuit comprising:
  • a capacitor including a lower and an upper electrode, and a dielectric selected from the group consisting of a superparaelectric, a paraelectric, and a ferroelectric material disposed between the lower and upper electrodes;
  • barrier layer having a top surface, the barrier layer being disposed in the contact hole and disposed directly on the filler material, the barrier layer disposed between and electrically connecting the filler material and the lower electrode of the capacitor;
  • a silicon nitride layer having a top surface, the silicon nitride layer being disposed on the insulating layer and laterally surrounding the barrier layer;
  • the top surface of the barrier layer and the top surface of the silicon nitride layer substantially forming a plane with the capacitor disposed thereon.
  • the filler material is a conductive material selected from the group consisting of silicides, nitrides, tungsten and polycrystalline silicon.
  • At least one of the lower electrode and the upper electrode is a conductive material selected from the group consisting of platinum, ruthenium, iridium, palladium and conductive oxides thereof.
  • the barrier layer is a material selected from the group consisting of WN, WC, WTiN, TaN, TiN and TiC.
  • a method for fabricating a semiconductor configuration for an integrated circuit which comprises:
  • a conductive filler material selected from the group consisting of silicides, nitrides, tungsten and polycrystalline silicon;
  • a dielectric from the group consisting of a superparaelectric, a paraelectric, and a ferroelectric material
  • a silicon nitride layer is deposited on a wall of the contact hole.
  • the barrier layer is embedded in a "silicon nitride collar" formed by a silicon nitride layer.
  • the material of the barrier layer that is to say, for example, titanium nitride, tungsten nitride, titanium tungsten nitride, tantalum nitride, etc., is reliably protected against oxidation.
  • the "silicon nitride collar" prevents the lateral diffusion of oxygen during the fabrication of the paraelectric or ferroelectric dielectric. In other words, lateral oxidation of the barrier layer, as is the case in the prior art, practically does not occur.
  • An additional effect that is achieved is that the material, e.g. platinum, of the lower electrode adheres well on the silicon nitride layer.
  • FIG. 1 is a section through a first exemplary embodiment of the semiconductor configuration according to the invention
  • FIG. 2 is a section through a second exemplary embodiment of the semiconductor configuration according to the invention.
  • FIG. 3 is a section through a prior art semiconductor configuration.
  • FIG. 1 shows a first exemplary embodiment of a semiconductor configuration.
  • a silicon dioxide layer 2 is situated on a silicon substrate 10 having a heavily doped region 9.
  • the silicon dioxide layer has a contact hole 8 to the heavily doped region 9.
  • Further conductive or heavily doped regions 13 and insulation regions 12 can additionally be provided in the silicon dioxide layer 2 and/or on the silicon substrate 10. These regions 13, 12 may be interconnects or LOCOS, for example.
  • the contact hole 8 is provided with filling material or a plug 1.
  • a barrier layer 3 is arranged between the plug 1 made from a conductive material, for example, tungsten, silicon, nitrides or polycrystalline silicon, and a lower electrode 5 made from for example, platinum.
  • the barrier layer 3 may be fabricated from conductive nitrides, carbides, borides, etc., such as, for example, WN, WC, WTiN, TaN, TiN, TiC, etc.
  • One possible material for the plug 1 is WSi.
  • the barrier layer 3 is surrounded laterally by a silicon nitride layer 4, the top side of which lies in the same plane as the top side of the barrier layer 3.
  • the top side of the barrier layer 3 may also lie somewhat below the top side of the silicon nitride layer 4.
  • a paraelectric, superparaelectric or ferroelectric dielectric 6 is applied to the lower electrode 5 made of platinum, which dielectric is in turn covered with an upper electrode 7.
  • the upper electrode 7 and/or the lower electrode 5 may also be made from ruthenium, iridium, palladium or conductive oxides thereof, such as RuO 2 , IrO 2 , etc.
  • the semiconductor configuration according to the invention may be fabricated in the following manner. First of all, the CMOS plane with the semiconductor body 10, the heavily doped regions 9 and 13, the insulation region 12 and the silicon dioxide layer 2 are fabricated. The silicon nitride layer 4 is then deposited before the contact hole 8 is etched.
  • etching-back is carried out in order to form a recess in the upper region of the plug 1.
  • the depth of the etching-back is matched approximately to the thickness of the silicon nitride layer 4 in such a way that it is somewhat less than the thickness of the silicon nitride layer 4.
  • the barrier layer 3 is then applied in the region of etching-back by means of sputtering or MOCVD.
  • the surface of the barrier layer 3 is aligned with the surface of the silicon nitride layer 4 by means of, for example, an etching-back or a grinding process.
  • the silicon nitride layer 4 surrounds the barrier layer 3 like a "collar".
  • the paraelectric, superparaelectric or ferroelectric dielectric 6 is then applied and structured.
  • the barrier layer 3 acts as protection against indiffusing oxygen and prevents oxidation of the plug 1.
  • the silicon nitride layer 4 reliably protects the embedded barrier layer 3 against oxidation and ensures the integrity of the platinum/barrier layer/plug structure.
  • silicon nitride is a good oxygen diffusion barrier, which, in the present case, prevents oxygen from being fed to the junction region between the barrier layer 3 and the lower electrode 5 from the surroundings.
  • the present invention thus increases the oxidation resistance of the barrier layer 3 to a great extent.
  • FIG. 2 shows a further exemplary embodiment of the invention.
  • the wall of the contact hole 8 is covered with an additional silicon nitride layer 16, which is deposited after the contact hole 8 has been etched.

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Abstract

The invention relates to a semiconductor configuration for integrated circuits, in which a stacked cell has a contact hole filled with a plug in an insulating layer, a capacitor having a lower electrode, which faces the plug, a paraelectric or ferroelectric dielectric and an upper electrode being provided on the contact hole. A barrier layer is situated between the plug and the lower electrode and is surrounded by a silicon nitride collar, which reliably prevents oxidation of the barrier layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This is a continuation of copending International Application PCT/DE97/02133, filed Sep. 19, 1997, which designated the United States.
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates in general to the field of semiconductors, and specifically to a semiconductor configuration and a method for fabricating a semiconductor configuration including a stacked cell with a protected barrier.
Conventional storage elements of semiconductor memory configurations usually use, as the storage dielectric, silicon dioxide or silicon nitride layers, although both of these have a dielectric constant in the region of merely about 6. A higher dielectric constant, however, would lead to a larger capacitance of the corresponding capacitor, so that the dimensions of the capacitor could actually be reduced if a corresponding increase in the capacitance is dispensed with.
In other words, the use of a dielectric having a large dielectric constant leads to a reduction in the area required for a capacitor with a corresponding capacitance, and thus to an increase in the integration level.
The developments practiced in this connection have yielded materials having a dielectric constant considerably higher than 6. Thus, an example of a paraelectric material that has been developed is (Bax ST1-x)TiO3, "BST", which has a dielectric constant of the order of magnitude of 400. It is obvious that BST permits a considerable increase in the integration level when it is used instead of the customary silicon dioxide or silicon nitride layers.
Furthermore, conventional storage elements, such as, for example, a dynamic random memory (DRAM), use paraelectric materials, although these lose their charge, and consequently also the information stored with the charge, in the event of a supply voltage failure. Because of the leakage current that occurs in conventional storage elements of this type, the charge must be continually "refreshed" or rewritten to. The use of novel ferroelectric materials as a storage dielectric is desirable since this enables the fabrication of nonvolatile semiconductor memory configurations that do not lose their information in the event of a supply voltage failure and, in addition, do not have to be continually refreshed.
To summarize, the use of ferroelectric materials as a storage dielectric is intrinsically desirable in the case of semiconductor memory configurations, since it is then possible to achieve an increase in the integration level in conjunction with protection in respect to a supply voltage failure.
However, the practical realization of the use of such ferroelectric or else paraelectric materials in semiconductor memory configurations depends to a great extent on how these materials can be incorporated in an integrated semiconductor circuit configuration. Such ferroelectric or paraelectric materials that have been taken into consideration heretofore are, in addition to the BST already mentioned, (Pb,Zr)TiO3 (PZT), SrBi2 Ta2 O9 (SBT), SrBi2 (Ta,Nb)O9 (SBTN) SrTiO3 (ST), ferroelectric and paraelectric polymers, etc. and generally ferroelectric and paraelectric materials.
Although these materials have high dielectric constants, and for this reason, are already used in ferroelectric random memories (FeRAM), their importance is still limited in practice. This is because it has been shown that the materials having a high dielectric constant cannot readily be used in semiconductor memory configurations. For example, the application of dielectric materials having a high dielectric constant or of ferroelectrics in large scale integrated stacked cells of semiconductor memory configurations is greatly impeded by the fact that the so-called "plug" or the filler material introduced into a contact hole is oxidized upon deposition of the dielectric. This oxidation takes place specifically because dielectrics having a high dielectric constant and ferroelectrics involve oxides which have to be exposed to high temperatures in an oxygen-containing atmosphere during the fabrication of the semiconductor or capacitor configuration.
Since the platinum electrode that is usually used for the capacitor contact is oxygen-permeable, the interface between the plug and the electrode, for example, oxidizes, which creates an electrical interruption.
FIG. 3 shows such a semiconductor configuration with a memory cell. In this semiconductor configuration, a dielectric insulator layer 2 made of silicon dioxide, for example, is applied to a semiconductor body 10 having a heavily doped region 9, and a hole 8 etched into the insulator layer. This hole 8 is filled with a filler material or plug 1 made from tungsten or polycrystalline silicon. Provided above the plug 1 is a barrier layer 3, which is made from, for example, WN, TiWN, TaN, WC, etc. The barrier layer 3 separates a lower electrode 5 made of platinum from the plug 1. A paraelectric or ferroelectric dielectric 6 is situated on the lower electrode 5, and an upper electrode 7 is applied in turn to the dielectric. In this semiconductor configuration, the barrier layer 3 is oxidized, beginning in the region 11, and this can ultimately lead to an electrical interruption. The oxidation advances from the region 11 along the interface 14 between the barrier layer 3 and the electrode 5 and along the interface 15 between the barrier layer 3 and the insulation layer 2.
This is a major reason that, in practice, the integration of a ferroelectric or paraelectric dielectric in a memory configuration in conjunction with a high integration level has been regarded heretofore as having little promise of success.
In an attempt to avoid significant oxidation of the interface between electrode and the plug, dielectrics having a high dielectric constant or ferroelectrics have previously been deposited in planar fashion above a LOCOS region only after the completion of a conventional CMOS transistor structure. In other words, besides a MOS transistor whose drain is connected, for example, to a bit line and whose gate is connected to a word line, a capacitor is provided above the LOCOS region. The upper electrode of the capacitor is made from platinum, for example, and is connected to the source electrode of a MOS transistor. The insulating layer of the capacitor is fabricated from a ferroelectric, and the second electrode (common plate), which is situated on a side of the ferroelectric opposite from the first electrode, is likewise fabricated from platinum, for example. SBT can be used as the dielectric. The sizes of the memory cells formed in this way are, for example, 10.1 μm×16.5 μm=167 μm2 =46 F2, if a basic dimension of 1.9 μm is used for F. In this case, the area of the capacitor is about 3.3 μm×3.3 μm=10.9 μm2 =3 F2. In other words, there is a relatively large space requirement for the memory cell and/or the interconnection thereof to the capacitor.
The application of a capacitor above the LOCOS region has the advantage, however, that a sputtering or sol gel method can be used for fabricating the planar ferroelectric layer of the capacitor. In particular as a result of the application of the ferroelectric layer, which takes place in a greatly oxidizing environment, the diffusion of oxygen through the electrode, which is usually made from platinum, no longer impairs the layer situated underneath, since an oxide is already present there.
To summarize, although the deposition of a CMOS transistor structure above the LOCOS region is readily possible, it leads to a considerable reduction in the integration level.
Although it is possible for the ferroelectric layers to be applied directly above the electrically conductive plug, this leads to further oxidation and thus ultimately to insulation of the electrical connections.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to provide a semiconductor configuration that permits integration of components with ferroelectric and paraelectric materials and in which undesirable oxidation in the region of the barrier layer of the plug is reliably avoided. In addition, a method for fabricating the semiconductor configuration is provided.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor configuration for an integrated circuit, comprising:
a capacitor including a lower and an upper electrode, and a dielectric selected from the group consisting of a superparaelectric, a paraelectric, and a ferroelectric material disposed between the lower and upper electrodes;
an insulating layer formed with a contact hole therethrough;
a filler material disposed in the contact hole;
a barrier layer having a top surface, the barrier layer being disposed in the contact hole and disposed directly on the filler material, the barrier layer disposed between and electrically connecting the filler material and the lower electrode of the capacitor; and
a silicon nitride layer having a top surface, the silicon nitride layer being disposed on the insulating layer and laterally surrounding the barrier layer;
the top surface of the barrier layer and the top surface of the silicon nitride layer substantially forming a plane with the capacitor disposed thereon.
In accordance with an added feature of the invention, the filler material is a conductive material selected from the group consisting of silicides, nitrides, tungsten and polycrystalline silicon.
In accordance with an additional feature of the invention, at least one of the lower electrode and the upper electrode is a conductive material selected from the group consisting of platinum, ruthenium, iridium, palladium and conductive oxides thereof.
In accordance with an another feature of the invention, the barrier layer is a material selected from the group consisting of WN, WC, WTiN, TaN, TiN and TiC.
With the objects of the invention in view, there is also provided a method for fabricating a semiconductor configuration for an integrated circuit, which comprises:
fabricating a CMOS plane with a semiconductor body;
producing an insulating layer;
applying a thickness of a silicon nitride layer on the insulating layer;
forming a contact hole in the insulating layer and in the silicon nitride layer;
filling the contact hole with a conductive filler material selected from the group consisting of silicides, nitrides, tungsten and polycrystalline silicon;
producing a recess in the conductive filler material having a depth corresponding to the thickness of the silicon nitride layer;
producing a barrier layer in the recess;
producing a surface of the barrier layer that is substantially aligned with a surface of the silicon nitride layer by performing an alignment step selected from the group consisting of grinding and etching-back;
applying a lower electrode to the surface of the barrier layer;
selecting a dielectric from the group consisting of a superparaelectric, a paraelectric, and a ferroelectric material;
applying a layer made from the dielectric onto the lower electrode; and
applying an upper electrode onto the dielectric layer.
In accordance with a concomitant feature of the invention, before the step of filling the contact hole, a silicon nitride layer is deposited on a wall of the contact hole.
In the case of the semiconductor configuration according to the invention, the barrier layer is embedded in a "silicon nitride collar" formed by a silicon nitride layer. As a result, the material of the barrier layer, that is to say, for example, titanium nitride, tungsten nitride, titanium tungsten nitride, tantalum nitride, etc., is reliably protected against oxidation.
The "silicon nitride collar" prevents the lateral diffusion of oxygen during the fabrication of the paraelectric or ferroelectric dielectric. In other words, lateral oxidation of the barrier layer, as is the case in the prior art, practically does not occur. An additional effect that is achieved is that the material, e.g. platinum, of the lower electrode adheres well on the silicon nitride layer.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor configuration with a protected barrier for a stacked cell, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a section through a first exemplary embodiment of the semiconductor configuration according to the invention;
FIG. 2 is a section through a second exemplary embodiment of the semiconductor configuration according to the invention; and
FIG. 3 is a section through a prior art semiconductor configuration.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Mutually corresponding structural parts are in each case provided with the same reference symbols in the figures. FIG. 1 shows a first exemplary embodiment of a semiconductor configuration. A silicon dioxide layer 2 is situated on a silicon substrate 10 having a heavily doped region 9. The silicon dioxide layer has a contact hole 8 to the heavily doped region 9. Further conductive or heavily doped regions 13 and insulation regions 12 can additionally be provided in the silicon dioxide layer 2 and/or on the silicon substrate 10. These regions 13, 12 may be interconnects or LOCOS, for example.
The contact hole 8 is provided with filling material or a plug 1. A barrier layer 3 is arranged between the plug 1 made from a conductive material, for example, tungsten, silicon, nitrides or polycrystalline silicon, and a lower electrode 5 made from for example, platinum. The barrier layer 3 may be fabricated from conductive nitrides, carbides, borides, etc., such as, for example, WN, WC, WTiN, TaN, TiN, TiC, etc. One possible material for the plug 1 is WSi. The barrier layer 3 is surrounded laterally by a silicon nitride layer 4, the top side of which lies in the same plane as the top side of the barrier layer 3. However, the top side of the barrier layer 3 may also lie somewhat below the top side of the silicon nitride layer 4. A paraelectric, superparaelectric or ferroelectric dielectric 6 is applied to the lower electrode 5 made of platinum, which dielectric is in turn covered with an upper electrode 7. The upper electrode 7 and/or the lower electrode 5 may also be made from ruthenium, iridium, palladium or conductive oxides thereof, such as RuO2, IrO2, etc.
The semiconductor configuration according to the invention may be fabricated in the following manner. First of all, the CMOS plane with the semiconductor body 10, the heavily doped regions 9 and 13, the insulation region 12 and the silicon dioxide layer 2 are fabricated. The silicon nitride layer 4 is then deposited before the contact hole 8 is etched.
After the contact hole 8 has been etched and filled with tungsten, conductive material such as silicides or polycrystalline silicone, etching-back is carried out in order to form a recess in the upper region of the plug 1. The depth of the etching-back is matched approximately to the thickness of the silicon nitride layer 4 in such a way that it is somewhat less than the thickness of the silicon nitride layer 4. The barrier layer 3 is then applied in the region of etching-back by means of sputtering or MOCVD. The surface of the barrier layer 3 is aligned with the surface of the silicon nitride layer 4 by means of, for example, an etching-back or a grinding process. In other words, the silicon nitride layer 4 surrounds the barrier layer 3 like a "collar".
The lower electrode 5, which is preferably made from platinum, is applied to the barrier layer 3. The paraelectric, superparaelectric or ferroelectric dielectric 6 is then applied and structured. During the deposition of the dielectric 6 and also during the subsequent oxidizing heat-treatment processes, the barrier layer 3 acts as protection against indiffusing oxygen and prevents oxidation of the plug 1. At the same time, the silicon nitride layer 4 reliably protects the embedded barrier layer 3 against oxidation and ensures the integrity of the platinum/barrier layer/plug structure. As is known, silicon nitride is a good oxygen diffusion barrier, which, in the present case, prevents oxygen from being fed to the junction region between the barrier layer 3 and the lower electrode 5 from the surroundings.
The present invention thus increases the oxidation resistance of the barrier layer 3 to a great extent.
FIG. 2 shows a further exemplary embodiment of the invention. In this exemplary embodiment, the wall of the contact hole 8 is covered with an additional silicon nitride layer 16, which is deposited after the contact hole 8 has been etched.

Claims (7)

We claim:
1. A semiconductor configuration for an integrated circuit, comprising:
a capacitor including a lower and an upper electrode, and a dielectric selected from the group consisting of a superparaelectric, a paraelectric, and a ferroelectric material disposed between said lower and upper electrodes;
an insulating layer formed with a contact hole therethrough;
a filler material disposed in said contact hole;
a silicon nitride layer disposed on a wall of said contact hole;
a barrier layer having a top surface, said barrier layer being disposed in said contact hole and disposed directly on said filler material, said barrier layer disposed between and electrically connecting said filler material and said lower electrode of said capacitor; and
a silicon nitride layer having a top surface, said silicon nitride layer being disposed on said insulating layer and laterally surrounding said barrier layer;
said top surface of said barrier layer and said top surface of said silicon nitride layer substantially forming a plane with said capacitor disposed thereon.
2. The semiconductor configuration according to claim 1, wherein said filler material is a conductive material selected from the group consisting of silicides, nitrides, tungsten, polycrystalline silicon, and tungsten silicide.
3. The semiconductor configuration according to claim 2, wherein at least one of said lower electrode and said upper electrode is a conductive material selected from the group consisting of platinum, ruthenium, iridium, palladium and conductive oxides thereof.
4. The semiconductor configuration according to claim 1, wherein at least one of said lower electrode and said upper electrode is a conductive material selected from the group consisting of platinum, ruthenium, iridium, palladium and conductive oxides thereof.
5. The semiconductor configuration according to claim 1, wherein said barrier layer is a material selected from the group consisting of WN, WC, WTiN, TaN, TiN and TiC.
6. A method for fabricating a semiconductor configuration for an integrated circuit, which comprises:
fabricating a CMOS plane with a semiconductor body;
producing an insulating layer;
applying a thickness of a silicon nitride layer on the insulating layer;
forming a contact hole in the insulating layer and in the silicon nitride layer;
depositing a silicon nitride layer on a wall of the contact hole;
filling the contact hole with a conductive filler material selected from the group consisting of silicides, nitrides, tungsten and polycrystalline silicon;
producing a recess in the conductive filler material having a depth corresponding to the thickness of the silicon nitride layer;
producing a barrier layer in the recess;
producing a surface of the barrier layer that is substantially aligned with a surface of the silicon nitride layer by performing an alignment step selected from the group consisting of grinding and etching-back;
applying a lower electrode to the surface of the barrier layer;
selecting a dielectric from the group consisting of a superparaelectric, a paraelectric, and a ferroelectric material;
applying a layer made from the dielectric onto the lower electrode; and
applying an upper electrode onto the dielectric layer.
7. The method according to claim 6, which comprises:
aligning the top surface of the barrier layer with the top surface of the silicon nitride layer and planarising the barrier layer and the silicon nitride layer to one another.
US09/282,099 1996-09-30 1999-03-30 Semiconductor configuration with a protected barrier for a stacked cell Expired - Fee Related US6043529A (en)

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DE19640246A DE19640246A1 (en) 1996-09-30 1996-09-30 Protected barrier semiconductor device for a stacked cell
DE19640246 1996-09-30
PCT/DE1997/002133 WO1998015013A1 (en) 1996-09-30 1997-09-19 Semiconductor device with a protected barrier for a stack cell

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Cited By (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6204070B1 (en) * 1997-12-27 2001-03-20 Hyundai Electronics Industries Co., Ltd. Method for manufacturing ferroelectric capacitor
US6235579B1 (en) * 1999-10-18 2001-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing stacked capacitor
US6326316B1 (en) * 1996-11-14 2001-12-04 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor devices
US6348709B1 (en) * 1999-03-15 2002-02-19 Micron Technology, Inc. Electrical contact for high dielectric constant capacitors and method for fabricating the same
WO2002063679A1 (en) * 2001-02-08 2002-08-15 Infineon Technologies Ag Method for producing a capacitor assembly for a semiconductor memory device
US6465300B2 (en) * 2000-05-19 2002-10-15 Hyundai Electronics Industries Co., Ltd. Method for forming a lower electrode for use in a semiconductor device
US20020179956A1 (en) * 2000-08-07 2002-12-05 Mcteer Allen Memory cell with selective deposition of refractory metals
US20030001186A1 (en) * 2001-06-30 2003-01-02 Soon-Yong Kweon Semiconductor memory device capable of preventing oxidation of plug and method for fabricating the same
US6541808B2 (en) 1998-10-12 2003-04-01 Raffaele Zambrano Contact structure for semiconductor devices and corresponding manufacturing process
US6559497B2 (en) 2001-09-06 2003-05-06 Taiwan Semiconductor Manufacturing Co., Ltd. Microelectronic capacitor with barrier layer
US6579727B1 (en) 1999-11-10 2003-06-17 Stmicroelectronics S.R.L. Process for selectively sealing ferroelectric capacitive elements incorporated in semiconductor integrated non-volatile memory cells
US6608383B2 (en) * 1997-12-24 2003-08-19 Sharp Kabushiki Kaisha Semiconductor device including capacitor with lower electrode including iridium and iridium oxide layers
US6633060B2 (en) 2000-11-17 2003-10-14 Stmicroelectronics S.R.L. Contact structure for a ferroelectric memory device
US6635523B1 (en) * 1997-12-04 2003-10-21 Fujitsu Limited Semiconductor device and method of manufacturing the same
US6645779B2 (en) * 2001-03-28 2003-11-11 Hynix Semiconductor Inc. FeRAM (ferroelectric random access memory) and method for forming the same
US20030222299A1 (en) * 2002-05-29 2003-12-04 Fujitsu Limited Semiconductor device and method of manufacturing the same
KR100410716B1 (en) * 2001-03-07 2003-12-18 주식회사 하이닉스반도체 FeRAM capable of connecting bottom electrode to storage node and method for forming the same
US20040067607A1 (en) * 2001-05-18 2004-04-08 Samsung Electronics Co., Ltd. Metal interconnection with low resistance in a semiconductor device and a method of forming the same
US6734565B2 (en) 2001-04-19 2004-05-11 Stmicroelectronics S.R.L. Contact structure for an integrated semiconductor device
US20040113191A1 (en) * 2000-08-25 2004-06-17 Coursey Belford T. Memory circuitry and mehtod of forming memory circuitry
US20040149477A1 (en) * 2003-01-30 2004-08-05 Haoren Zhuang Sidewall structure and method of fabrication for reducing oxygen diffusion to contact plugs during CW hole reactive ion etch processing
KR100448233B1 (en) * 2001-12-29 2004-09-13 주식회사 하이닉스반도체 Method for fabrication of ferroelectric capacitor having tungsten plug
US20040185653A1 (en) * 2003-03-19 2004-09-23 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
KR100449949B1 (en) * 2002-04-26 2004-09-30 주식회사 하이닉스반도체 Method for fabricating capacitor in ferroelectric memory device
US20040201043A1 (en) * 2003-04-10 2004-10-14 Hui-Min Mao Bit line contact hole and method for forming the same
US6822276B1 (en) * 1998-09-10 2004-11-23 Renesas Technology Corp. Memory structure with a ferroelectric capacitor
US20050009209A1 (en) * 1999-11-10 2005-01-13 Stmicroelectronics S.R.L. Process for selectively sealing ferroelectric capactive elements incorporated in semiconductor integrated non-volatile memory cells
US20050032361A1 (en) * 2001-08-30 2005-02-10 Ammar Derraa High aspect ratio contact structure with reduced silicon consumption
US20050037521A1 (en) * 2003-08-15 2005-02-17 Uwe Wellhausen Methods and apparatus for processing semiconductor devices by gas annealing
US6881643B2 (en) 2000-04-27 2005-04-19 Sharp Kabushiki Kaisha Semiconductor device producing method and semiconductor device
US20050087788A1 (en) * 2003-10-22 2005-04-28 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
US20060202283A1 (en) * 2001-08-30 2006-09-14 Ammar Deraa Metal silicide adhesion layer for contact structures
US20070010089A1 (en) * 2005-07-07 2007-01-11 Hynix Semiconductor Inc. Method of forming bit line of semiconductor device
US20080182409A1 (en) * 2007-01-31 2008-07-31 Robert Seidel Method of forming a metal layer over a patterned dielectric by electroless deposition using a selectively provided activation layer
US20080318378A1 (en) * 2007-06-20 2008-12-25 Chih-Ta Wu MIM Capacitors with Improved Reliability
US20220399352A1 (en) * 2021-06-09 2022-12-15 Microchip Technology Incorporated Ferroelectric random access memory (fram) capacitors and methods of construction
US11937434B2 (en) 2021-06-09 2024-03-19 Microchip Technology Incorporated Ferroelectric random access memory (FRAM) capacitors and methods of construction

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3979237A (en) * 1972-04-24 1976-09-07 Harris Corporation Device isolation in integrated circuits
US5366920A (en) * 1993-04-12 1994-11-22 Nec Corporation Method for fabricating a thin film capacitor
US5418388A (en) * 1993-06-18 1995-05-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a capacitor with an adhesion layer
US5459345A (en) * 1993-06-28 1995-10-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device high dielectric capacitor with narrow contact hole
US5464786A (en) * 1994-10-24 1995-11-07 Micron Technology, Inc. Method for forming a capacitor having recessed lateral reaction barrier layer edges
EP0697719A2 (en) * 1994-08-01 1996-02-21 Texas Instruments Incorporated Microelectronic structure including a conductive exotic-nitride barrier layer for high-dielectric-constant material electrodes and method of fabricating the same
US5506166A (en) * 1993-04-02 1996-04-09 Micron Technology, Inc. Method for forming capacitor compatible with high dielectric constant materials having a low contact resistance layer
EP0739030A2 (en) * 1995-04-19 1996-10-23 Nec Corporation Highly-integrated thin film capacitor with high dielectric constant layer
US5717236A (en) * 1995-05-15 1998-02-10 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory including stacked capacitor having a flat surface
US5739563A (en) * 1995-03-15 1998-04-14 Kabushiki Kaisha Toshiba Ferroelectric type semiconductor device having a barium titanate type dielectric film and method for manufacturing the same
US5852307A (en) * 1995-07-28 1998-12-22 Kabushiki Kaisha Toshiba Semiconductor device with capacitor
US5923062A (en) * 1994-10-11 1999-07-13 Mitsubishi Denki Kabushiki Kaisha Semiconductor device incorporating capacitors

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3979237A (en) * 1972-04-24 1976-09-07 Harris Corporation Device isolation in integrated circuits
US5506166A (en) * 1993-04-02 1996-04-09 Micron Technology, Inc. Method for forming capacitor compatible with high dielectric constant materials having a low contact resistance layer
US5366920A (en) * 1993-04-12 1994-11-22 Nec Corporation Method for fabricating a thin film capacitor
US5418388A (en) * 1993-06-18 1995-05-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a capacitor with an adhesion layer
US5459345A (en) * 1993-06-28 1995-10-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device high dielectric capacitor with narrow contact hole
EP0697719A2 (en) * 1994-08-01 1996-02-21 Texas Instruments Incorporated Microelectronic structure including a conductive exotic-nitride barrier layer for high-dielectric-constant material electrodes and method of fabricating the same
US5923062A (en) * 1994-10-11 1999-07-13 Mitsubishi Denki Kabushiki Kaisha Semiconductor device incorporating capacitors
US5464786A (en) * 1994-10-24 1995-11-07 Micron Technology, Inc. Method for forming a capacitor having recessed lateral reaction barrier layer edges
US5739563A (en) * 1995-03-15 1998-04-14 Kabushiki Kaisha Toshiba Ferroelectric type semiconductor device having a barium titanate type dielectric film and method for manufacturing the same
EP0739030A2 (en) * 1995-04-19 1996-10-23 Nec Corporation Highly-integrated thin film capacitor with high dielectric constant layer
US5717236A (en) * 1995-05-15 1998-02-10 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory including stacked capacitor having a flat surface
US5852307A (en) * 1995-07-28 1998-12-22 Kabushiki Kaisha Toshiba Semiconductor device with capacitor

Cited By (72)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6326316B1 (en) * 1996-11-14 2001-12-04 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor devices
US6635523B1 (en) * 1997-12-04 2003-10-21 Fujitsu Limited Semiconductor device and method of manufacturing the same
US6608383B2 (en) * 1997-12-24 2003-08-19 Sharp Kabushiki Kaisha Semiconductor device including capacitor with lower electrode including iridium and iridium oxide layers
US6204070B1 (en) * 1997-12-27 2001-03-20 Hyundai Electronics Industries Co., Ltd. Method for manufacturing ferroelectric capacitor
US6822276B1 (en) * 1998-09-10 2004-11-23 Renesas Technology Corp. Memory structure with a ferroelectric capacitor
US20050074936A1 (en) * 1998-09-10 2005-04-07 Kazuyoshi Torii Method of fabricating a semiconductor device including a reaction barrier film, a diffusion barrier film and a ferroelectric film
US20030082873A1 (en) * 1998-10-12 2003-05-01 Stmicroelectronics S.R.I. Contact structure for semiconductor devices and corresponding manufacturing process
US6541808B2 (en) 1998-10-12 2003-04-01 Raffaele Zambrano Contact structure for semiconductor devices and corresponding manufacturing process
US6737284B2 (en) 1998-10-12 2004-05-18 Stmicroelectronics S.R.L. Contact structure for semiconductor devices and corresponding manufacturing process
US20050014328A1 (en) * 1999-03-15 2005-01-20 Graettinger Thomas M. Electrical contact for high dielectric constant capacitors and method for fabricating the same
US20060001161A1 (en) * 1999-03-15 2006-01-05 Graettinger Thomas M Electrical contact for high dielectric constant capacitors and method for fabricating the same
US6348709B1 (en) * 1999-03-15 2002-02-19 Micron Technology, Inc. Electrical contact for high dielectric constant capacitors and method for fabricating the same
US6806187B2 (en) 1999-03-15 2004-10-19 Micron Technology, Inc. Electrical contact for high dielectric constant capacitors and method for fabricating the same
US20070114586A1 (en) * 1999-03-15 2007-05-24 Graettinger Thomas M Electrical contact for high dielectric constant capacitors and method for fabricating the same
US20020079581A1 (en) * 1999-03-15 2002-06-27 Graettinger Thomas M. Electrical contact for high dielectric constant capacitors and method for fabricating the same
US6235579B1 (en) * 1999-10-18 2001-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing stacked capacitor
US6579727B1 (en) 1999-11-10 2003-06-17 Stmicroelectronics S.R.L. Process for selectively sealing ferroelectric capacitive elements incorporated in semiconductor integrated non-volatile memory cells
US20050009209A1 (en) * 1999-11-10 2005-01-13 Stmicroelectronics S.R.L. Process for selectively sealing ferroelectric capactive elements incorporated in semiconductor integrated non-volatile memory cells
US6881643B2 (en) 2000-04-27 2005-04-19 Sharp Kabushiki Kaisha Semiconductor device producing method and semiconductor device
US6465300B2 (en) * 2000-05-19 2002-10-15 Hyundai Electronics Industries Co., Ltd. Method for forming a lower electrode for use in a semiconductor device
US7078755B2 (en) * 2000-08-07 2006-07-18 Micron Technology, Inc. Memory cell with selective deposition of refractory metals
US20020179956A1 (en) * 2000-08-07 2002-12-05 Mcteer Allen Memory cell with selective deposition of refractory metals
US20070012987A1 (en) * 2000-08-07 2007-01-18 Mcteer Allen Memory cell with selective deposition of refractory metals
US7148536B2 (en) 2000-08-25 2006-12-12 Micron Technology, Inc. Memory circuitry and method of forming memory circuitry
US7355231B2 (en) * 2000-08-25 2008-04-08 Micron Technology, Inc. Memory circuitry with oxygen diffusion barrier layer received over a well base
US20040113191A1 (en) * 2000-08-25 2004-06-17 Coursey Belford T. Memory circuitry and mehtod of forming memory circuitry
US20050161722A1 (en) * 2000-08-25 2005-07-28 Coursey Belford T. Memory circuitry with oxygen diffusion barrier layer received over a well base
US20040005725A1 (en) * 2000-11-17 2004-01-08 Stmicroelectronics S.R.L. Method of forming a contact structure and a ferroelectric memory device
US6633060B2 (en) 2000-11-17 2003-10-14 Stmicroelectronics S.R.L. Contact structure for a ferroelectric memory device
US6878982B2 (en) 2000-11-17 2005-04-12 Stmicroelectronics S.R.L. Method of forming a contact structure and a ferroelectric memory device
WO2002063679A1 (en) * 2001-02-08 2002-08-15 Infineon Technologies Ag Method for producing a capacitor assembly for a semiconductor memory device
KR100410716B1 (en) * 2001-03-07 2003-12-18 주식회사 하이닉스반도체 FeRAM capable of connecting bottom electrode to storage node and method for forming the same
US6645779B2 (en) * 2001-03-28 2003-11-11 Hynix Semiconductor Inc. FeRAM (ferroelectric random access memory) and method for forming the same
US6734565B2 (en) 2001-04-19 2004-05-11 Stmicroelectronics S.R.L. Contact structure for an integrated semiconductor device
US20040175927A1 (en) * 2001-04-19 2004-09-09 Stmicroelectronics S.R.I. Contact structure for an integrated semiconductor device
US7052985B2 (en) 2001-04-19 2006-05-30 Stmicroelectronics S.R.L. Contact structure for an integrated semiconductor device
US20040067607A1 (en) * 2001-05-18 2004-04-08 Samsung Electronics Co., Ltd. Metal interconnection with low resistance in a semiconductor device and a method of forming the same
US20040195613A1 (en) * 2001-06-30 2004-10-07 Hynix Semiconductor Inc. Semiconductor memory device capable of preventing oxidation of plug and method for fabricating the same
US6744092B2 (en) * 2001-06-30 2004-06-01 Hynix Semiconductor Inc. Semiconductor memory device capable of preventing oxidation of plug and method for fabricating the same
US7205192B2 (en) * 2001-06-30 2007-04-17 Hynix Semiconductor Inc. Semiconductor memory device capable of preventing oxidation of plug and method for fabricating the same
US20030001186A1 (en) * 2001-06-30 2003-01-02 Soon-Yong Kweon Semiconductor memory device capable of preventing oxidation of plug and method for fabricating the same
US20050032361A1 (en) * 2001-08-30 2005-02-10 Ammar Derraa High aspect ratio contact structure with reduced silicon consumption
US6858904B2 (en) 2001-08-30 2005-02-22 Micron Technology, Inc. High aspect ratio contact structure with reduced silicon consumption
US6908849B2 (en) 2001-08-30 2005-06-21 Micron Technology, Inc. High aspect ratio contact structure with reduced silicon consumption
US20060202283A1 (en) * 2001-08-30 2006-09-14 Ammar Deraa Metal silicide adhesion layer for contact structures
US20050233577A1 (en) * 2001-08-30 2005-10-20 Ammar Derraa High aspect ratio contact structure with reduced silicon consumption
US7402512B2 (en) 2001-08-30 2008-07-22 Micron Technology, Inc. High aspect ratio contact structure with reduced silicon consumption
US6559497B2 (en) 2001-09-06 2003-05-06 Taiwan Semiconductor Manufacturing Co., Ltd. Microelectronic capacitor with barrier layer
KR100448233B1 (en) * 2001-12-29 2004-09-13 주식회사 하이닉스반도체 Method for fabrication of ferroelectric capacitor having tungsten plug
KR100449949B1 (en) * 2002-04-26 2004-09-30 주식회사 하이닉스반도체 Method for fabricating capacitor in ferroelectric memory device
US7259416B2 (en) 2002-05-29 2007-08-21 Fujitsu Limited Semiconductor device having a conductive plug
US20030222299A1 (en) * 2002-05-29 2003-12-04 Fujitsu Limited Semiconductor device and method of manufacturing the same
US20070259454A1 (en) * 2002-05-29 2007-11-08 Fujitsu Limited Semiconductor device and method of manufacturing the same
US7465657B2 (en) 2002-05-29 2008-12-16 Fujitsu Limited Method of manufacturing a semiconductor device having a capacitor
WO2004068539A3 (en) * 2003-01-30 2005-02-10 Infineon Technologies Ag Sidewall structure and method of fabrication for reducing oxygen diffusion to contact plugs during cw hole reactive ion etch processing
WO2004068539A2 (en) * 2003-01-30 2004-08-12 Infineon Technologies Ag Sidewall structure and method of fabrication for reducing oxygen diffusion to contact plugs during cw hole reactive ion etch processing
US7042705B2 (en) 2003-01-30 2006-05-09 Infineon Technologies Ag Sidewall structure and method of fabrication for reducing oxygen diffusion to contact plugs during CW hole reactive ion etch processing
US20040149477A1 (en) * 2003-01-30 2004-08-05 Haoren Zhuang Sidewall structure and method of fabrication for reducing oxygen diffusion to contact plugs during CW hole reactive ion etch processing
US7053436B2 (en) 2003-03-19 2006-05-30 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
US20040185653A1 (en) * 2003-03-19 2004-09-23 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
US20040201043A1 (en) * 2003-04-10 2004-10-14 Hui-Min Mao Bit line contact hole and method for forming the same
US20050037521A1 (en) * 2003-08-15 2005-02-17 Uwe Wellhausen Methods and apparatus for processing semiconductor devices by gas annealing
US20050087788A1 (en) * 2003-10-22 2005-04-28 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
US20060124983A1 (en) * 2003-10-22 2006-06-15 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
US20070010089A1 (en) * 2005-07-07 2007-01-11 Hynix Semiconductor Inc. Method of forming bit line of semiconductor device
US20080182409A1 (en) * 2007-01-31 2008-07-31 Robert Seidel Method of forming a metal layer over a patterned dielectric by electroless deposition using a selectively provided activation layer
US20080318378A1 (en) * 2007-06-20 2008-12-25 Chih-Ta Wu MIM Capacitors with Improved Reliability
US8889507B2 (en) 2007-06-20 2014-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. MIM capacitors with improved reliability
US9418999B2 (en) 2007-06-20 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. MIM capacitors with improved reliability
US20220399352A1 (en) * 2021-06-09 2022-12-15 Microchip Technology Incorporated Ferroelectric random access memory (fram) capacitors and methods of construction
US11729993B2 (en) * 2021-06-09 2023-08-15 Microchip Technology Incorporated Ferroelectric random access memory (FRAM) capacitors and methods of construction
US11937434B2 (en) 2021-06-09 2024-03-19 Microchip Technology Incorporated Ferroelectric random access memory (FRAM) capacitors and methods of construction

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