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US5014058A - Method and arrangement for evaluating a measurable analog electrical quantity - Google Patents

Method and arrangement for evaluating a measurable analog electrical quantity Download PDF

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Publication number
US5014058A
US5014058A US07/425,212 US42521289A US5014058A US 5014058 A US5014058 A US 5014058A US 42521289 A US42521289 A US 42521289A US 5014058 A US5014058 A US 5014058A
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United States
Prior art keywords
time divider
period
time
analog
divider
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Expired - Fee Related
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US07/425,212
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English (en)
Inventor
Klaus Horn
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Siemens AG
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Siemens AG
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D3/00—Indicating or recording apparatus with provision for the special purposes referred to in the subgroups
    • G01D3/028—Indicating or recording apparatus with provision for the special purposes referred to in the subgroups mitigating undesired influences, e.g. temperature, pressure
    • G01D3/032—Indicating or recording apparatus with provision for the special purposes referred to in the subgroups mitigating undesired influences, e.g. temperature, pressure affecting incoming signal, e.g. by averaging; gating undesired signals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R17/00—Measuring arrangements involving comparison with a reference value, e.g. bridge
    • G01R17/02—Arrangements in which the value to be measured is automatically compared with a reference value
    • G01R17/06—Automatic balancing arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval

Definitions

  • the invention relates to a method and an arrangement for evaluating an analog measurement quantity according to the time divider principle.
  • the time divider principle contains two integration parts, of which the first part represents a compensation of the measurement quantities by an unbalancing quantity of opposite polarity (up-integration) and the second integration part contains a down-integration. So that at the end of the two integration parts, i.e., at the end of the time divider period, the integration signal has become zero, the time of the first integration part must be adjusted accordingly relative to the total time divider period. Thus, the measurement result can be taken directly from this time divider clock ratio.
  • the time divider ratio i.e., the correct adjustment of the time of the first integration part relative to the total time divider period is obtained by an evaluation extending over a multiplicity of time divider periods, of the amplified control deviation signal as well as over its phase-selective rectification and subsequent smoothing by an analog lowpass filter included in a servo control circuit of the time divider adjustment.
  • the known method has a rather sluggish response behavior to abrupt changes of the measuring quantity.
  • dead times and/or adjustment times t e of approximately 100 ms ⁇ t e ⁇ ls are typical which, in a multiplicity of applications made the practical use of time divider circuits to date at least problematic if not impossible.
  • the method according to the invention is advantageously realized in such a manner that in a first step the control deviation ⁇ 1 ⁇ from the correct time divider ratio is determined by definite integration over the measurement and reference signal, for instance, by a Miller integrator, always exactly over a full time divider period T.
  • An analog integration signal ⁇ U i obtained thereby serves as a measure for the control deviation which is converted after the end of the time divider period into a digital control deviation signal m 1 .
  • the digital control deviation signal is used for the correction of the time divider clock ratio ##EQU1## in the subsequent second time divider period.
  • the overall circuit costs can be kept particularly low if the integrator used, for instance, the Miller integrator is utilized twice in the manner of a dual-slope method by up-integrating alternatingly in a first step, first via the time divider T 1 , the sum of the measurement signal (input voltage U m ) and reference signal (standard voltage U n ) and subsequently, the deviation signal obtained thereby is digitized by a counting-down integration.
  • the dual-slope method known per se for fast analog-digital conversion is described, for instance, in the book Tietze/Schenk "Halbleitersclientechnik", Fifth Edition, 1980, Springer Verlag, pages 663 and 664.
  • An advantageous solution of the stated problem is also provided by an arrangement for carrying out the method of the type mentioned above.
  • An arrangement with an integrating null amplifier, to the inputs of which the reference quantity and/or the measurement quantity are applied via switches, controlled as to the time divider ratio, is known from the already mentioned German Pat. No. 33 30 841.
  • the realization of the deviation encoding period with an evaluation of the control deviation signal is made possible in an advantageous manner by the described design of the control units.
  • the pole alternation for suppressing interference due to thermo and contact voltages in the measuring circuit described in German Pat. No. 33 30 841 is used advantageously also for stringent accuracy requirements, also in case of null drifts and noise components of the integrating null amplifier if the microprocessor weighs the furnished digital signals according to the alternating pole direction with synchronously alternating sign. From the sequence of the measurement values then obtained with alternating sign, the magnitude and sign of d-c voltage drift then obtained can be recognized and taken into consideration when computing the time divider adjustment value. Above all, an analog compensation of the null drift can be added for stringent accuracy requirements so that the null amplifier is protected from overloads and is always operated at its symmetrical operating point.
  • FIG. 1 shows a first embodiment of the invention, from which the basic operation of a measuring method with the time divider can be seen,
  • FIG. 2 the signal and switch diagrams required for an understanding of the embodiment
  • FIG. 3 an expanded embodiment with a measuring pickup in a bridge circuit
  • FIG. 4 the signal and switch diagrams required for an understanding of the expanded embodiment
  • FIG. 5 a third embodiment with a dual-slope analog-digital and cascading the down-integration process
  • FIG. 6 a variant of the embodiment according to FIG. 5, with operation symmetrical to ground of the measurement value pickup,
  • FIG. 7 a fourth embodiment with pole switching of the d-c current and voltage supply of the measuring quantity pickup
  • FIG. 8 a signal and switch diagram necessary for an understanding of the fourth embodiment.
  • an input voltage U m is present as an analog electrical measurement quantity and a standard voltage U N as a comparison or reference quantity which are brought via a switch S 2 and a resistor R to a first input E 1 of a first operational amplifier V 1 and via a double-throw switch S 1 to a second input E 2 of the operational amplifier V 1 .
  • the second input E 2 is at ground potential.
  • the operational amplifier V 1 represents with the resistor R and a capacitor C a Miller integrator for the definite integration of a voltage U D which is formed from the input voltage U m and/or the normal voltage U N .
  • a voltage ⁇ U i which in the case that the time divider ratio ⁇ is set correctly at the end of the integration of U D extending over a full time divider period T is zero but in the presence of a faulty time divider ratio ⁇ has a value which as to sign and magnitude is proportional to the deviation ⁇ of the time divider clock ratio ⁇ from its correct value ##EQU2##
  • either a positive compensation voltage+U k can be applied via a switch S 3 or via a switch S 4 a negative compensation voltage -U k which acts amplified on the first input E 1 of the operational amplifier V 1 .
  • the resistor R A can then be omitted (i.e., R A ⁇ 0) if U k is designed so that the equation
  • U N is fulfilled.
  • the voltage ⁇ U i at the output of the operational amplifier V 1 is brought to one input of a second operational amplifier V 2 connected as a comparator.
  • the comparator output quantity V is present as a binary quantity at the input of a control and counting circuit SZ and gives information regarding the sign of ⁇ U i .
  • This control and counting circuit SZ has as an essential component a microprocessor ⁇ P which is supplied with clock pulses I c by a clock generator CL.
  • a settable down-counter Z according to the method described in detail in German Pat. No. 33 30 841, which can be supplied on the one hand via a switch S 5 with the clock pulses of the clock generator CL and further is given setting information n by the microprocessor ⁇ P.
  • the counter If the counter is counted down to the content zero by the clock pulses T c of the clock generator CL, it furnishes a control pulse (time zero) to the microprocessor ⁇ P.
  • the microprocessor ⁇ P also furnishes control pulses for the switches S 1 ... S 4 via control lines, not shown in detail here.
  • the display of a numerical value equivalent to the measurement quantity is carried out by means of a display unit MA.
  • the circuit of FIG. 1 will be explained, making reference to the diagrams for FIG. 2.
  • the waveform of the voltage U i is shown, from which the integration processes, brought on by the time divider pulses or by the switching processes in the deviation encoding phases AV can be seen.
  • the switching states of the switches S 1 , S 2 , S 3 , S 4 , S 5 as well as the waveform of the comparator output quantity V at the input of the control and counting circuit SZ versus time.
  • the circuit according to FIG. 1 works, first of all according to the voltage compensation principle, in that the input voltage U m is compensated by a part ⁇ U N of the standard voltage U N which, as the arithmetic means, is derived down from U N , according to the time divider principle by operating the double-throw switch S 1 in the ratio ##EQU4##
  • the balance condition U D U m - ⁇ U N is monitored here, according to the invention, intermittently always exactly over a full time divider period as a definite integral ##EQU5## The latter are available at the end of each time divider period T y from t E to t E+T as the control deviation voltage signal ##EQU6## at the output of the amplifier V 1 .
  • such a control deviation signal ⁇ U i is subsequently converted in the control and counting unit SZ into a proportional digital value m ⁇ and the latter is utilized directly for correcting the divider ratio ##EQU7## from the past y time divider period to the divider ratio ##EQU8## in the subsequent (y+l)th time divider period.
  • the counting value m ⁇ is recognized by the control circuit SZ realized by the microprocessor ⁇ P and is used for correcting the cycle time
  • T c represents the period of a clock pulse I c .
  • the measurement quantity and, coupled thereto, the input voltage U m execute a squarewave jump from a o to a 1 .
  • the control deviation signal ⁇ U il will have a correspondingly large value at the time t 4 in the time divider period T following the time t 2 .
  • a sensitivity error should occur in a deviation encoding phase AV, for instance, by incorrect design of R A , the mechanisms customary for any control loop become effective. While at the time t 5 , a small residual voltage ⁇ U i2rest ⁇ 0 remains which however is completely broken down in the following time divider period, sensitivity errors in the control loop components, although they have reactions on the speed of the settling behavior, but not on the steady state balancing result of the overall circuit.
  • FIG. 3 shows a second embodiment, expanded over FIG. 1, with a strain gauge strip pickup at a voltage supply U S , the bridge circuit A of which can be compensated in the event of measuring quantity-dependent unbalances by an unbalance compensation resistor R v which is timed by S 1 .
  • the resistor R v naturally forms the reference normal (see the normal voltage U N from FIG. 1) of the compensation circuit.
  • the addition of the compensation quantity (see compensation voltage +U k ,-U k from FIG. 1) during the deviation encoding phase AV is carried out here by means of a voltage drop at compensation resistors R k and R N which are connected parallel to the voltage supply U S .
  • the arrangement operates otherwise completely similarly to the basic circuit in FIG. 1; only the addition of the compensation quantity leads to somewhat changed down-integration processes during the deviation encoding phases AV.
  • the described cascading has the advantage that in spite of high resolution, only a very short down-integration time (typically less than 100 ⁇ s) is required for obtaining the digital correction values.
  • FIG. 6 shows a further embodiment according to FIG. 5, in which the pickup bridge circuit A is operated with ground symmetry, so that the integrator (operational amplifier V 1 ) provides additionally very great common-mode suppression.
  • the resistors R 1 , R 2 , R 3 and switches S 1 , S 3 , S 4 according to the embodiment as per FIG. 5 are thus provided here for each input of operational amplifier V 1 (R 11 , R 21 , R 31 ; R 12 , R 22 , R 32 ; S 21 , S 31 , S 41 ; S 22 , S 32 , S 42 ).
  • the embodiment according to FIG. 7 includes some circuit variants known from German Pat. No. 33 30 841 which are advantageous if high suppression of noise components, thermal and contact voltage influences as well as null drifts of the operational amplifiers are expected. These are, for one, the cascading of the normal voltage with resistors R g and R f as unbalance compensation resistors and secondly, a clock pole reversal of the supply voltage via a polarity switch S 10 . Furthermore, the additional use of an operational amplifier V o , driven at only a very low level, with wiring by resistor R v1 , R v2 is provided which makes possible a large common-mode suppression and potential separation in spite of a supply U S symmetrical to ground.
  • the circuit variants according to FIG. 7, contains in addition an effective possibility to suppress possible null drifts of the operational amplifier V o which the latter recognizes from the different correction values as to magnitude and sign and which it obtains, for the same measuring quantities in successive time divider periods which, however, are supplied with polarity-reversed sign.
  • a capacitor C o can then be charged, depending on the sign, via switches S 8 and S 11 , respectively, and a resistor R oz which capacitor conducts a drift compensation current i o to the operational amplifier V o via a resistor R 01 .
  • Such stabilization of the operating point can be advantageous for integration purposes as well as for constructing very-high resolution analog-digital converters according to the principle presented.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Electric Clocks (AREA)
US07/425,212 1987-04-01 1988-03-31 Method and arrangement for evaluating a measurable analog electrical quantity Expired - Fee Related US5014058A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19873710904 DE3710904A1 (de) 1987-04-01 1987-04-01 Verfahren und anordnung zur auswertung einer analogen elektrischen messgroesse

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US5014058A true US5014058A (en) 1991-05-07

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US (1) US5014058A (fr)
EP (1) EP0356438B1 (fr)
AT (1) ATE85733T1 (fr)
DE (2) DE3710904A1 (fr)
WO (1) WO1988007658A1 (fr)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993017502A1 (fr) * 1992-02-25 1993-09-02 Laurel Electronics Inc. Convertisseur analogique/numerique a vitesse de conversion inverse a la periode d'integration
US5262780A (en) * 1990-12-14 1993-11-16 Laurel Electronics, Inc. Analog to digital converter with conversion rate inverse to the integration period
US5313208A (en) * 1991-07-26 1994-05-17 Mario Bellini Method of transmitting analog signals in digital form
US5373292A (en) * 1992-07-29 1994-12-13 Kabushiki Kaisha Toshiba Integration type D-A/A-D Conversion apparatus capable of shortening conversion processing time
US5400025A (en) * 1993-03-31 1995-03-21 Honeywell Inc. Temperature corrected integrating analog-to-digital converter
US5565869A (en) * 1994-08-09 1996-10-15 Fluke Corporation Multiple slope analog-to-digital converter having increased linearity
US6476660B1 (en) * 1998-07-29 2002-11-05 Nortel Networks Limited Fully integrated long time constant integrator circuit
US20030016151A1 (en) * 2001-07-19 2003-01-23 Rohm Co., Ltd. Integration type A/D converter, and battery charger utilizing such converter
US20030117098A1 (en) * 2001-12-22 2003-06-26 Papst-Motoren Gmbh & Co. Kg Method and apparatus for digitizing a voltage
US20090207064A1 (en) * 2006-10-27 2009-08-20 Sartorius Ag Measurement amplification device and method
US20140184314A1 (en) * 2012-12-28 2014-07-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
PL1833473T3 (pl) 2004-12-23 2010-02-26 Arena Pharm Inc Kompozycje modulatora receptora 5HT2C i sposoby zastosowania

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4024533A (en) * 1975-07-10 1977-05-17 Analogic Corporation Ratiometric analog-to-digital converter
DE3330841A1 (de) * 1983-08-26 1985-03-14 Siemens AG, 1000 Berlin und 8000 München Auswerteschaltungen fuer passive messgroessenaufnehmer
US4608553A (en) * 1981-05-11 1986-08-26 Ormond A Neuman Analog to digital converter without zero drift
US4694277A (en) * 1985-02-22 1987-09-15 Nec Corporation A/D converter
US4739305A (en) * 1985-04-29 1988-04-19 Ishida Scales Mfg. Co., Ltd. Double integral type A/D converter

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Publication number Priority date Publication date Assignee Title
US3631467A (en) * 1970-05-07 1971-12-28 Singer Co Ladderless, dual mode encoder

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4024533A (en) * 1975-07-10 1977-05-17 Analogic Corporation Ratiometric analog-to-digital converter
US4608553A (en) * 1981-05-11 1986-08-26 Ormond A Neuman Analog to digital converter without zero drift
DE3330841A1 (de) * 1983-08-26 1985-03-14 Siemens AG, 1000 Berlin und 8000 München Auswerteschaltungen fuer passive messgroessenaufnehmer
US4694277A (en) * 1985-02-22 1987-09-15 Nec Corporation A/D converter
US4739305A (en) * 1985-04-29 1988-04-19 Ishida Scales Mfg. Co., Ltd. Double integral type A/D converter

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
"Halbleiterschaltungstechnik", Tietze et al., 5th Edition, Springer-Verlag, pp. 663-664 (1980).
"Uber die Genauigkeit elektrischer Grundnormale und Kompensationsmesseinrichtungen", Angersbach, Archiv fur Technisches Messen (ATM), J930-3 (1964).
Halbleiterschaltungstechnik , Tietze et al., 5th Edition, Springer Verlag, pp. 663 664 (1980). *
Uber die Genauigkeit elektrischer Grundnormale und Kompensationsmesseinrichtungen , Angersbach, Archiv fur Technisches Messen (ATM), J930 3 (1964). *

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5262780A (en) * 1990-12-14 1993-11-16 Laurel Electronics, Inc. Analog to digital converter with conversion rate inverse to the integration period
US5313208A (en) * 1991-07-26 1994-05-17 Mario Bellini Method of transmitting analog signals in digital form
WO1993017502A1 (fr) * 1992-02-25 1993-09-02 Laurel Electronics Inc. Convertisseur analogique/numerique a vitesse de conversion inverse a la periode d'integration
US5373292A (en) * 1992-07-29 1994-12-13 Kabushiki Kaisha Toshiba Integration type D-A/A-D Conversion apparatus capable of shortening conversion processing time
US5400025A (en) * 1993-03-31 1995-03-21 Honeywell Inc. Temperature corrected integrating analog-to-digital converter
US5565869A (en) * 1994-08-09 1996-10-15 Fluke Corporation Multiple slope analog-to-digital converter having increased linearity
US6476660B1 (en) * 1998-07-29 2002-11-05 Nortel Networks Limited Fully integrated long time constant integrator circuit
US7038610B2 (en) * 2001-07-19 2006-05-02 Rohm Co., Ltd. Integration type A/D converter, and battery charger utilizing such converter
US20030016151A1 (en) * 2001-07-19 2003-01-23 Rohm Co., Ltd. Integration type A/D converter, and battery charger utilizing such converter
US20030117098A1 (en) * 2001-12-22 2003-06-26 Papst-Motoren Gmbh & Co. Kg Method and apparatus for digitizing a voltage
US6949903B2 (en) * 2001-12-22 2005-09-27 Ebm-Papst St. Georgen Gmbh & Co. Kg Method and apparatus for digitizing a voltage
US20090207064A1 (en) * 2006-10-27 2009-08-20 Sartorius Ag Measurement amplification device and method
JP2010507944A (ja) * 2006-10-27 2010-03-11 ザトーリウス アクチエン ゲゼルシャフト 測定増幅装置および方法
US7830294B2 (en) 2006-10-27 2010-11-09 Sartorius Ag Measurement amplification device and method
JP4865037B2 (ja) * 2006-10-27 2012-02-01 ザトーリウス ウェイング テクノロジー ゲーエムベーハー 測定増幅装置および方法
US20140184314A1 (en) * 2012-12-28 2014-07-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9316695B2 (en) * 2012-12-28 2016-04-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

Also Published As

Publication number Publication date
WO1988007658A1 (fr) 1988-10-06
EP0356438B1 (fr) 1993-02-10
ATE85733T1 (de) 1993-02-15
DE3878456D1 (de) 1993-03-25
DE3710904A1 (de) 1988-10-13
EP0356438A1 (fr) 1990-03-07

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