US3878370A

US3878370A - Electronic interval timer

Info

Publication number: US3878370A
Application number: US393725A
Authority: US
Inventors: Anthony Santomango; Jr Nicholas N Hatheway
Original assignee: ARTRONICS CORP
Current assignee: ARTRONICS CORP
Priority date: 1973-09-04
Filing date: 1973-09-04
Publication date: 1975-04-15
Anticipated expiration: 1992-04-15

Abstract

An electronic interval timer with an input means for setting an interval and a trigger switch for starting the timer. Actuating the trigger switch loads a number representing the interval into a register and clears a counter. Subsequent clock pulses pass through an enabled gating circuit and advance the counter. A comparator energizes an output circuit until the values in the counter and the register are equal. While the output circuit is energized, the trigger switch is disabled and operation of the input means does not affect the timer.

Description

United States Patent Santomango et a1.

ELECTRONIC INTERVAL TIMER lnventors: Anthony Santomango, West Peabody; Nicholas N. Hatheway, lr., Newbury, both of Mass.

Artronics Corporation, North Andover, Mass.

Filed: Sept. 4, 1973 Appl. No.: 393,725

Assignee:

US. Cl. 235/92 T; 235/92 R; 235/92 CA; 235/92 EC Int. Cl. G06m 3/12 Field of Search 235/92 LG, 92 CA, 92 EC, 235/92 PE, 92 T [56] References Cited UNITED STATES PATENTS 3,075,189 1/1963 Lisicky 235/92 CA 1 Apr. 15, 1975 Dilger 235/92 EC Fowler 235/92 CA Primary Examiner-Gareth D. Shaw Assistant Examiner-Robert F. Gnuse Attorney, Agent, or Firm-Pearson & Pearson [57] ABSTRACT An electronic interval timer with an input means for setting an interval and a trigger switch for starting the timer. Actuating the trigger switch loads a number representing the interval into a register and clears a counter. Subsequent clock pulses pass through an en abled gating circuit and advance the counter. A comparator energizes an output circuit until the values in the counter and the register are equal. While the output circuit is energized, the trigger switch is disabled and operation of the input means does not affect the timer.

4 Claims, 2 Drawing Figures l E +v TRIGGER 0 OFF 1K 4| mp 40 i PATENTEDAPR 1 5l975 SOURCE SHEET 1 0F 2 I 26 ,J G- INPUT SWITCHES CLK -h.lN

COUNTER REGISTER CLR '22 bD I COMPARATOR ,23

TRIGGER F/F 5O RIGGER 0N OFF FIG. l

PATENTEDAPR 1 5m:

sum 2 ur 2 CLOCK CLEAR LATC H CLOCK IN REGISTER GATE IN OUTPUT TO RE LAY TRIGGER EVENT OUTPUT TRIGGER F/ F SET FIG. 2

ELECTRONIC INTERVAL TIMER BACKGROUND OF THE INVENTION This invention relates to timers and more specifically to electronic timers for timing preset intervals.

In prior interval timers, thumbwheel switches or equivalent input means are set to a desired interval. A start or trigger switch is then actuated to start the interval being timed. thereby energizing an output device. Signals representing the present interval are constantly 'compared with signals representing the elapsed time.

When they are equal, the timer tie-energizes the output device. In addition. these timers normally have a stop switch to immediately de-energize the output means during a timed interval.

Prior timers of this type have two operating problems. One becomes apparent if an operator inadvertently actuates the trigger switch while an interval is being timed. In some systems. this stops all operations while in others the timer resets and begins timing a new interval. Sometimes the operator may inadvertently change the setting of the input means during an inter- I SUMMARY In accordance with one aspect of this invention, a trigger switching circuit starts a timer. Once a load device is activated. the output of the trigger switching circuit is disabled. Furthermore, proper operation of the trigger switching circuit enables a gating pulse to load interval signals into a register. As the transfer can occur at no other time. operation of interval input switches cannot adversely affect timer operation even when an interval is being timed.

This invention is pointed out with particularity in the appended claims. A more thorough understanding of the above and further objects and advantages of this invention may be attained by referring to the following description taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 schematically depicts an interval timer constructed in accordance with our invention; and

FIG. 2 illustrates timing for signals at designated locations in the circuit of FIG. 1.

DESCRIPTION OF AN ILLUSTRATIVE EMBODIMENT In the following discussion, a positive voltage represents a logically TRUE signal or a logical ONE signal, while a substantially zero or ground voltage represents a logically FALSE signal or a logical ZERO signal. A ZERO signal applied to the level set S input of flip-flop sets a .IK flip-flop. A negative-going clocking transition at the C input causes the Q output of the flip-flop to assume the same voltage level as exists at the J input, for purposes of this discussion. With respect to the outputs, when the flip-flop is set, the output voltage is at a positive level. Hence the Q output of a flip-flop is TRUE when it is positive.

Various conductors in the circuitry shown in FIG. 1 have letter designations A through P. These letter designations correspond to the letter designations in timing charts of FIG. 2. Therefore the main clocking signal on conductor A appears as a sequence of squate waves in FIG. 2A.

The interval timer shown in FIG. 1 is synchronized to a 60 Hz source 10, such as a standard power line. In order to provide clocking pulses (FIG. 2A) at the proper frequency, the output of the 60 Hz source passes through a divider 11. with a divisor of 6. and selectively through a divider 12 with a divisor of 10. A switch 13, when in the position shown, provides a clocking signal at 1/60 the frequency ofthe signal from the source 10. while in the other position the signal frequence is 1/6 the frequency of the source 10. Thus. in the position shown in FIG. 1, the switch 13 enables the timer to count in seconds; in the other position. the timer counts in tenths of seconds.

Assuming that the timer in FIG. I'is inactive. the clocking pulses have no effect. The signal to the S input (FIG. 2N) is TRUE and the grounded J input keeps the flip-flop l4 reset. As a result, the flip-flop I4 (FIG. 2P) disables a NAND gate 15 and enables a NAND gate 16. Clocking pulses pass through the NAND gate 16 (FIG. 2]) but a latch 17 disables a NAND gate 20 so the clocking pulses do not reach a counter 21 (FIGS. 2E and 2F).

During normal operations. the counter 21 advances from zero and the value in the counter 21 is constantly compared with the value in a register 22 by a comparator 23. During the interval. the flip-flop 14 and comparator 23 energize a NAND gate 24. When the output Signal on conductor K is ZERO. an output circuit 25 is energized. When the comparator 23 senses that the value in the counter 21 has reached that in the register 22. it disables the NAND gate 24 and the resulting ONE output de-energizes the output circuit 25.

Input switches 26 are arranged in decades in one embodiment and can be set to an interval. These switches 26 can comprise thumbwheel or equivalent switches. They also include circuitry for generating binary signals representing the interval as known in the art.

If an operator depresses a CLEAR switch 30, he dis ables the timer. The CLEAR switch is a momentary- ON switch. So as long as it is off, a resistor 31 connected to a source of positive potential (+V) keeps a capacitor 32 charged so a positive or ONE signal. is maintained and a NOT OR gate 33 receives a ONE input (FIG. 28). An inverter 34, together with a resistor 35 which is also coupled to the source of positive potential (+V), keeps the clearing (CLR) input of the counter 21 at a logically ONE level (FIG. 2C).

When the operator moves the CLEAR switch 30 to the ON position, the capacitor 32 discharges rapidly and transmits a logically ZERO pulse (FIG. 28). thereby clearing the counter 21 (FIG. 2C). In addition. this pulse is an input to a NAND gate 36 in the latch 17 and resets the latch 17 if the timer is active. This disables the counter 21. Assuming that this action by the operator occurs at time T1 in FIG. 2, the timer does not respond further.

Now assume that at time T2, the operator actuates a trigger switch 40. The trigger switch 40 is also a momentary-ON switch which normally grounds the S input to a flip-flop 41 so it is set. This provides a positive voltage at the input to a NAND gate 42 (FIG. 2L). The NAND gate 42 also receives ONE output (which is at a positive voltage level) from the NAND gate 24 (FIG. 2K) and a ground voltage from an inverter 43 (FIG. 2M).

A pulse forming network 44 comprises a resistor 45 which couples one side of a capacitor 46 to the source of positive potential (+V) while a parallel circuit. comprising a resistor 47 and diode 50. also couples the other side of the capacitor 46 to the source of positive potential (+V). When the trigger switch 40 is off. the capacitor 46 charges and a positive potential appears at the input to the inverter 43. thereby disabling the NAND circuit 42. When the arm on the trigger switch 40 reaches the ON contact. the capacitor 46 rapidly discharges initially drawing the junction between the capacitor 46 and a resistor 47 to ground. As a result. the inverter 43. which also provides a shaping function. passes a positive-going pulse to the NAND gate 42 (FIG. 2M With all three inputs at a positive level. the output is ZERO and the flip-flop 14 sets (FIG. 2P). When the capacitor 46 recharges sufficiently. the output ofthe inverter 43 reverts to a ground potential. The transition serves as a clocking input and the flip-flop 41 resets thereby disabling the NAND gate 42. This all occurs before the operator can release the trigger switch 40 and it returns to its OFF contact. By the time it does return to the OFF contact. as described. the timer is active and the ZERO output from the NAND gate 24 disables the NAND gate 42. Therefore. the circuitry comprising the trigger switch 40, the flip-flop 41. the NAND gate 42 and the pulse forming network 44 provide one of the advantages of this invention. So as long as an interval is being timed. and the output from the signal on NAND gate 24 (FIG. 2K) is at a ground potential and disables the NAND gate 42. Subsequent pulses caused by inadvertent actuation of the trigger switch 40 cannot pass through the NAND gate 42 to set the trigger flip-flop 14.

As soon as the flip-flop 14 sets (FIG. 2)) the next positive going pulse (FIG. 2A) passes through NAND gate 15 and the NOT OR gate 33 to clear the counter 21 (FIG. 2C The clearing signal lasts until the positive pulse terminates. Concurrently with the appearance of the positive pulse. a signal from the NAND gate 15 (FIG. 2H) sets the latch 17 (FIG. 2E). This provides one enabling input to the NAND gate 24, but the load is not energized because the flip-flop 14 is set. As the NAND gate 16 is disabled (FIG. 2]). the NAND gate 20 shifts to a zero level (FIG. 2F). This does not advance the counter as the clearing input to counter 21 is held at zero.

At the end of the positive pulse on conductor A. the flip-flop 14 resets (FIG. 2P) and disables the NAND gate 15 (FIG. 2H). The clearing input (FIG. 2C) to the counter 21 is released and an inverter 51, which receives the output of the NAND gate 15, clocks the data from the input switches 26 into the register 22 (FIG. 2G). At the same instant. the flip-flop l4 resetting enables the NAND gate 16. The NAND gate 24 also energizes the output unit (FIG. 2K) as the comparator 23 enables the NAND gate 24 as soon as the new data is loaded into the register 22. Thus, the NAND gate 24 simultaneously activates the output device 25 and-disables the NAND gate 42 (FIG. 2K).

With the flip-flop 14 reset. the NAND gate 16 acts as a gated inverter. Thus. while the clock is at a ground potential. the output is at a ONE potential. the output from the NAND gate 20 stays at a logical zero level (FIG. 2F).

At time T3. the positive clock pulse (FIG. 2A) passes through the

NAND gates

16 and 20 and advances the counter 21. Subsequent positive pulses also advance the counter until the numbers in the counter 21 and register 22 are equal.

Now referring to time T4, assume that the operator actuates the clear switch 30. As shown in FIG. 2B by the dashed lines. the resulting pulse passes through the NOT OR gate 33 and inverter 34 to clear the counter 21 (FIG. 2C). In addition. the pulse resets the latch 17 (FIG. 2E) to thereby disable the counter 21 and the NAND gate 24.

In a normal operation, however, the counter 21 eventually reaches the number contained in the register 22. This is time T5. Then the comparator 23 performs two functions. First. as previously indicated, its conductor shifts to a ground potential and disables the NAND gate 24. This turns off the output device 25 and enables the NAND gate 42 to start a new sequence when the operator subsequently actuates the trigger switch 40..

Secondly. the comparator 23 disables the NAND gate 20 so no further clock pulses can pass to the counter 21.

If the clear switch 21 is actuated (at time T6). the comparator 23 tries to enable the NAND gate 24 but the latch. in its reset condition. maintains the NAND gate 24 in a disabled state.

Therefore. in accordance with this invention. the timer controls the interval during which the output device 25 is enabled. If the operator inadvertently manipulates the input switches 26 during such timing interval. nothing happens. The input switches 26 are isolated from the input register 22. Further. the trigger switch 40 can be inadvertently actuated during an interval. but the NAND gate 42 is disabled.

It will be apparent that there are many variations which can be made to the specific circuitry which is shown in FIG. I in the sequence of operations. while still providing an interval timer which has these characteristics. Therefore. it is the object of the appended claims to cover all such variations and modifications as come within the true spirit and scope of this invention.

I claim:

1. An interval timing unit with a source of clock pulses. a counter for transmitting signals representing an interval being timed. a register for transmitting time interval signals representing a number stored therein corresponding to the interval to be timed. a comparator connected to receive signals from the counter and register. the comparator including means for transmitting first and second signals when the counter and register signals are unequal other than equal and, respectively. and output means energized in response to the first signal. the improvement of a starting circuit comprising:

a switch means;

means connected to the comparator and said switch means for generating a trigger pulse when said switch means is actuated while the comparator transmits the second signal;

input gating means for coupling. in response to an enabling signal, clock pulses from the source to the counter whereby the signals from the counter are altered periodically; and an enabling circuit for transmitting the enabling signal to said gating means. said enabling circuit including means responsive to a first clock pulse after said trigger pulse generating means transmits a trigger pulse for clearing the counter. thereby causing the comparator to transmit the first signal and thereby enabling the counter to begin counting. 2. A timing circuit as recited in claim 1. additionally comprising means for generating the time interval signals, said enabling circuit additionally comprising means responsive to said clearing means for coupling the signals from the time interval signal generator to the register.

3. A timer as recited in claim 1., wherein said enabling circuit comprises:

a clocked flip-flop with a first input connected to said input gating means for setting said flip-flop in response to a trigger pulse and a second input for receiving clock pulses. said flip-flop being reset in response to each clock pulse in the absence of a signal at the first input: and

means responsive to a clock pulse when said clocked flip-flop is set for clearing the counter and enabling the counter gate upon completion of the clock pulse.

4. A timing circuit as recited in claim 3. additionally comprising switching means for generating time interval signals and input gating means for the register. said enabling circuit additionally comprising an inverter connected to said clock clearing means for enabling said input gating means.

Claims

1. An interval timing unit with a source of clock pulses, a counter for transmitting signals representing an interval being timed, a register for transmitting time interval signals representing a number stored therein corresponding to the interval to be timed, a comparator connected to receive signals from the counter and register, the comparator including means for transmitting first and second signals when the counter and register signals are unequal other than equal and, respectively, and output means energized in response to the first signal, the improvement of a starting circuit comprising: a switch means; means connected to the comparator and said switch means for generating a trigger pulse when said switch means is actuated while the comparator transmits the second signal; input gating means for coupling, in response to an enabling signal, clock pulses from the source to the counter whereby the signals from the counter are altered periodically; and an enabling circuit for transmitting the enabling signal to said gating means, said enabling circuit including means responsive to a first clock pulse after said trigger pulse generating means transmits a trigger pulse for clearing the counter, thereby causing the comparator to transmit the first signal and thereby enabling the counter to begin counting.

2. A timing circuit as recited in claim 1, additionally comprising means for generating the time interval signals, said enabling circuit additionally comprising means responsive to said clearing means for coupling the signals from the time interval signal generator to the register.

3. A timer as recited in claim 1, wherein said enabling circuit comprises: a clocked flip-flop with a first input connected to said input gating means for setting said flip-flop in response to a trigger pulse and a second input for receiving clock pulses, said flip-flop being reset in response to each clock pulse in the absence of a signal at the first input; and means responsive to a clock pulse when said clocked flip-flop is set for clearing the counter and enabling the counter gate upon completion of the clock pulse.

4. A timing circuit as recited in claim 3, additionally comprising switching means for generating time interval signals and input gating means for the regiSter, said enabling circuit additionally comprising an inverter connected to said clock clearing means for enabling said input gating means.