US3876867A

US3876867A - Electronic timer

Info

Publication number: US3876867A
Application number: US344172A
Authority: US
Inventors: Robert D Schull; Roger R Taggart
Original assignee: Individual
Current assignee: Scientific Drilling International Inc
Priority date: 1973-03-23
Filing date: 1973-03-23
Publication date: 1975-04-08
Anticipated expiration: 1992-04-08

Abstract

An electronic timer including a pulse source, counter means for counting the pulses from said source, and means for producing a series of displays representing the instantaneous count on the counter means at a series of different times, with the counter being adapted to count continuously up to the time of a particular readout actuation of the device, and to thereafter continue counting from that time to the time of a next successive actuation.

Description

United States Patent Schull et a1.

ELECTRONIC TIMER Inventors: Robert D. Schull, Mission Viejo; Roger R. Taggart, Yorba Linda, both of Calif.

James W. Murray, Newport Beach. Calif.

Filed: Mar. 23, 1973 Appl. No.: 344,172

Assignee:

US. Cl. 235/92 T;-235/92 EA; 235/92 TC; 235/92 R; 324/186 Int. Cl H03k 21/32; H03k 21/18 Field of Search 235/92 T, 92 EA, 92 TF 235/92 TC, 92 DN; 324/186; 58/24 References Cited UNITED STATES PATENTS Hilton 235/92 TF DIVIDI-e SHIFT QECaISTEQ MULTI PLE x E12 Coum'ei? Apr. 8, 1975 2.864948 12/1958 Neff 235/92 EA 3.063.631 11/1962 Ray 235/92 EA 3,594,643 7/1971 Hunt 235/92 EA Primary E.\'an1inerGareth D. Shaw Assistant Examiner-Joseph M. Thesz, Jr. Attorney. Agent, or Firm-William P. Green [5 7] ABSTRACT An electronic timer including a pulse source, counter means for counting the pulses from said source, and means for producing a series of displays representing the instantaneous count on the counter means at a series of different times, with the counter being adapted to count continuously up to the time of a particular readout actuation of the device, and to thereafter continue counting from that time to the time of a next successive actuation.

11 Claims, 5 Drawing Figures TO SEVEN SEGMENT ELECTRONIC TIMER BAcxoRouNjrior THE INVENTION This invention relatestto improved electronic timer devices, adapted to be utilized for timing a series of successive intervals, or the total thereof, with readout displays being produced at the end of each such interval. The invention will be discussed primarily as applied to the timing of successive laps of a race, such as for example an automobile race, but it will be apparent that the device is also usuable for other similar timing purposes.

During an automobile race, the crews of the various cars usually find it desirable 'to time some or all of the individual laps driven by their respective drivers, as well as in many cases the split time or lead time between two selected cars. This timing is normally effected by use of a conventional stop watch, which is started by a first manual actuation of the user and then stopped by a subsequent actuation, so that the hands of the watch indicate the total time elapsed between the two actuations. In some cases, an electronic timer has been employed for this purpose, but in the case of both mechanical watches and electric timers the second actuation of the device has had the effect of completely stopping operation of the watch or timer, and thus pre* venting that particular device from continuing to time the next successive lap. As a result, in order to time two successive laps or intervals, it has been necessary with conventional equipment to employ two or more separate watches or timers, one to mark the end of a first lap, and the other to commence the timing of the second lap. Most crews have employed three such watches, all connected together in a single unit for actuation by a single operating bar or element, so that upon each actuation one watch ends its timing period, a second watch is reset, and the third watch com mences timing of the next succesive lap. Equipment of this type has necessarily been very cumbersome and inconvenient, as well as expensive to purchase and maintain, and in addition has been less reliable than would be desired in view of the difiiculty of assuring mechanical actuation of three separate units at precisely the same instant.

SUMMARY OF THE INVENTION The present invention provides an improved timing device which is adapted for the above discussed lap timing and other similar timing purposes, and which in particular can effectively time two successive laps or intervals, and produce a display of the time of the first interval while the device still remains in operation for timing the next successive lap. The device may similarly indicate to the user the split time between two cars, again without halting or interfering with the basic timing of a longer period.

The device includes a source of periodic timed pulses (either AC or DC but preferably the latter), used in conjunction with counter means which function to count the pulses and control display apparatus for producing a preferably digital display representing the length of the interval being timed. The circuitry is so arranged that its actuation to a condition displaying a readout time does not prevent the counter from continuing to count after the timeof the readout actuation. That is, the counter counts pulses continuously up to the time of actuation of the device, and thereafter continues to count pulses, with the display mechanism functioning to give a readout representing the instantaneous count on the counter at the time of actuation of the device. Preferably, an actuation by the operator op-' erates memory means associated with the counter for recording the instantaneous reading of the counter, which reading may then be read out of the memory for display. For best results, the counter assembly includes a series of decade counters acting to count the pulses in decimal fashion, with a series of individual latches associated with the decade counters to record their instantaneous readings for ultimate delivery to the display elements. In one form of the invention or condition of the apparatus each actuation of the device (for example at the end of a lap in a race) automatically resets the counter mechanism to a zero condition, to thereby time individually the successive laps. In another form or condition of the apparatus, the counter is not thus reset at the end of each lap, but rather continues to count upwardly from the total reached at the end of the lap, in a manner ultimately giving a reading of the total time elapsed for a series of laps. The counter preferably reads in seconds and portions of a second, and may be automatically reset to zero at the end of seconds, with the number of minutes being recorded on another display unit.

Each lap timing actuation of the device preferably operates to energize the display elements for a predetermined interval, and to then automatically terminate that display, desirably under the control of a one shot multivibrator or other delay unit. Also, a separate actuating switch may be provided for timing split time between two successive cars, without interfering with the continuance of the operation of the counter to time a full lap or series of laps as discussed above.

BRIEF DESCRIPTION OF THE DRAWINGS DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring first to FIG. 1, I have illustrated at 10 .a small hand held type of timer typically adapted for use in timing a series of laps of an automobile race or other race. The timer 10 may have a rectangular housing 11 with a window 12 through which a number of electrically actuated digital dow 12 through which a number beginning and end of each lap, and a two position selector switch 23 which determines whether the time read out on the device at the end of a particular lap is the time elapsed for only that single lap, or is the total time for a series of laps. The switches on the device also may include a pushbutton switch 24 for rendering the display elements readable at any particular desired time, and a pushbutton or other switch 25 for resetting the lap count digits l3 and 14 at the start of the race.

With reference now to FIG. 2, the circuitry contained within housing includes a source of precisely and uniformly timed repeating pulses, whose known frequency is utilized as the basic timing interval for the device. These pulses may be produced by a crystal oscillator 26, desirably operated at 819.2 KHz with the output of this oscillator being fed to a frequency divider 27, which produces three different output frequencies on

lines

28, 29, and 30 all dependent upon and timed to and controlled by the basic frequency of oscillator 26. These three very accurately controlled frequencies are desirably 100 Hz in lines 28, 400 Hz in line 29, and 1600'l-lz in line 30. The 100 Hz pulses in line 28 are fed tothe first of four

decade counters

31, 32, 33, and 34. Each of these is a divide-by-ten type counter, which counts up to 10 and then repeats in known fashion. As will be understood, the first 10 pulses received on line 28 cause counter 31 to count from zero to nine and then on the tenth count be automatically reset to zero. The tenth count also causes a first actuation of the next counter 32, to its one condition. Similarly, the tenth count of counter 32 causes actuation of counter 33 to its one condition, and the tenth count of counter 33 actuates counter 34 to its one condition, so that the reading on counter 33 represents elapsed time in seconds, while

counters

31, 32, and 34, represent hundredths, tenths, and tens of seconds respectively.

Associated with the four counters 31 through 34 respectively, there are provided four latch type memories 35, 36, 37, and 38, each of which is actuable to any one of 10 conditions from zero to nine, representing the ten possible conditions of the associated counter, 31, 32, 33 or 34. When a latching signal is received on line 39 leading to the four latches, each of these latches is actuated by that signal to a condition corresponding to the instantaneous reading on the associated

counter

31, 32, 33, or 34, and remains in that condition even though the counters continue to count additional pulses. The latch memories thus remember or catch the instantaneous readings of the counters at the time of the signal. The outputs of the four latches are fed to a multiplexer 40, which produces a multiplexed binary coded decimal (BCD) output in four lines 41, which are multiplexed at a frequency four times that of the pulses being counted, under the control of the 400 Hz frequency in line 29. This 400 Hz frequency is fed through appropriate circuitry, such as a scan counter 42 and scan decoder 43, to produce a suitable signal in line 44 timed to the pulses being counted in a fashion producing thev desired multiplexed BCD output in lines 41. The scan decoder 43 also has four

additional output lines

45, 46, 47, and 48, which are energized successively at times corresponding to the delivery of the various individual multiplexed signals to lines 41, and which act through four

transistors

49, 50, 51, and 52 to correspondingly sequentially energize four

lines

53, 54, 55, and 56 leading to first sides of the four

digital display units

17, 18, 19,and respectively, which represent elapsed seconds in decimal-form. The multiplexed BCD signals in lines 41 are decoded by the decoder 57 to an appropriate condition for energization of the particular type of display digit being employed. In the illustrated preferred arrangement, the digits are of a seven segment type, in which any digit from zero to nine is formed by an appropriate arrangement of selected ones of seven segments. When the display units are of this type, the decoder 57 is of a type to produce a seven segment output, on seven lines 58 leading respectively to the seven different segments of each of the various digits. The signals on lines 58 are of course multiplexed in the same manner as the BCD signals on lines 41, so that first one of the digits (e.g. digit 17) is illuminated in correspondence with the signals then present on the seven lines 58, then a next successive one of the digits (e.g. digit 18) is illuminated in correspondence with the next successive group of multiplexed signals on lines 58, etc. The sequential energization of the

different lines

53, 54, 55, and 56 by scanner 43, timed to the multiplexed signals on lines 58, causes each of the digits to be illuminated at exactly the time that the multiplexed signals for controlling that digit are received. In accordance with conventional practice, each of the seven elements of a particular digit may consist of an electroluminescent unit, having its anode connected to one of the lines 58, and with all of these electroluminescent units having a common cathode connected to the

corresponding line

53, 54, 55, or 56.

When the

counters

31, 32, 33, and 34 reach a 60 second count, they are automatically reset to zero. The circuitry for attaining this result may include two

lines

157 and 158 connected to the one and four outputs respectively from the BCD multiplexer 40. When both of these lines are energized, indicating a five signal on the BCD lines 41, these two signals in

lines

157 and 158 function together to actuate an and circuit 59 to produce an output in a line 60. When this five signal in line 60 coincides with a signal in the tens line 53, these two signals together actuate a second and circuit 61 to produce an output in a line 62. Thus, during the entire period when the signals in lines 41 represent counts between 50 and 59 seconds, inclusive, there are produced in lines 62 a series of repeating output pulses. These are smoothed out by a filter 63 to produce a steady output in a line 64 from the time that the count reaches 50 seconds to the time that the count reaches 60 seconds. This signal may be inverted by an inverter.

65, to produce a steady low signal in a line 66 during the fifties. This low signal is combined with a signal in.

another line 67 which occurs each time that the count reaches any multiple of 10 seconds, to actuate a nor inverter gate 68 to a condition producing a signal in the line 69 which is high at 60 seconds. This signal is fed back through a line 70 to the reset inputs of

counters

31, 32, 33, and 34, to thus automatically reset all of those counters to zero simultaneously when the 60 second count is reached. The signal in line 67 which indicated that ten seconds or a multiple thereof has been reached is derived from the output side of the counter 33, which counts the seconds from zero to nine.

The sixty second signal in line 69 is also fed to the input side of an additional counter-decoder-driver 71, which counts minutes from zero to nine and energizes the minute indicating digit 16 in accordance therewith. This digit, like the others previously discussed, may be of a seven segment electroluminescent type, with the output of unit 71 being appropriately coded to energize this seven segment digit through seven lines 72 con-, nected to the anodes of the various segments of digit 16, and with the common cathode of those seven segments being appropriately energized as by grounding at 73.

The particular times which are represented by the seconds and minutes display elements are determined by manual actuation of the previously mentioned pushbutton switch 22 of FIG. 1 (shown in the left-hand portion of the FIG. 2 circuit diagram). Depression of this pushbutton switch closes a circuit which momentarily energizes the input side of a one shot multivibrator 74 through a line 75. This one shot is so designed as to then supply an output signal on a line 76 for a period of five seconds, at which time that signal terminates and a second signal on another line 77 commences. In the preferred arrangement, each of these signals is a low signal. The initiation of the five second signal on line 76 immediately energizes a shift register 78, which then very rapidly progresses through four timed stages, at a rate dependent upon the high frequency 1600 Hz input in line 30. On the first pulse in line 30, shift register 78 energizes two output lines leading to a transistor 79 and connected resistor 80, in a relation turning on the transistor and producing a signal in its collector line 81. This signal is of a character to combine with the condition then present in line 77 and act through an nor circuit 82 to produce an output in line 39 which energizes the latches 35, 36, 37, and 38 to store therein the instantaneous then present counts in

counters

31, 32, 33, and 34. The second pulse received through line 30 actuates the shift register to its next stage, which turns off the transistor 79. The third pulse turns on a second transistor 84, and the fourth pulse turns that second transistor off. During the interval that the second transistor 84 is on, a signal is conducted therefrom through a line 85 to the reset lines of the four

counters

31, 32, 33, and 34, to reset those counters to zero. This reset signal must travel through a selector switch 23 (whose actuator is illustrated in FIG. 1 at 23). When this selector switch is in its open position at the time of any actuation of switch 22, the signal from transistor 84 which results from such actuation cannot reach the reset lines to the counters, and consequently the counters are not reset to zero at that actuation, but rather continue to count in a manner indicating the total time elapsed for a plurality of laps.

The electrical circuitry is energized by appropriate batteries contained within the case of the device, typically including a four and one-half volt battery 85 and a nine volt battery 86. In order to conserve the energy of the nine volt battery, which supplies the power for illuminating the electroluminescent digits, the circuitry is desirably designed to supply power to those digits only during predetermined intervals. More particularly, the apparatus may function to supply power to the digits only during the timed five second period in which multivibrator 74 supplies a signal to its output line 76 (just after each actuation of switch 22). This signal in line 76 acts during the five second interval to turn on a transistor 184, which with two

resistors

185 and 186 is connected across both batteries, with the output of transistor 184 functioning to turn on another transistor 87 whose emitter is connected to the negative side of battery 86, and whose collector is connected through a line 88 and a resistor 89 to decoder 97. The line 88 is also connected through a resistor 90 to'a transistor 91, to turn on that transistor and supply power to counter-decoder-driver 71. The power supplied to

units

97 and 71 through line 88 is the power which is delivered through lines 58 and 72 to the digits, under the control of the counting mechanisms, to energize the digits. The auxiliary display switch 24 is manually actuable at any time, to energize the digits and render them visible at times between the five second intervals when they are automatically illuminated.

The number of laps completed in the race are counted by counting the number of actuations of the lap switch 22. This lap counting signal is taken in FIG. 2 from the output side of transistor 84, through a line 93, which actuates a decimal or divide-by-ten counter 94, and a second similar counter 95. These two counters may produce BCD outputs, which are decoded to seven digit signals in lines 96 by decoders 97, to energize the two electroluminescent seven

segment digits

13 and 14, to indicate the number of laps from zero through ninety-nine. The two

counters

94 and 95 may be reset to zero by actuation of reset switch 25. Digits l3 and 14 are illuminated by power derived from the previously mentioned line 88, through a line 188 leading to decoders 97, to thereby energize these digits along with all of the others whenever switch 24 is closed or transistor 87 is turned on.

To now describe a cycle of operation of the device of FIGS. 1 and 2, assume that it is desired to time a series of successive laps of an automobile race, foot race, or the like. To do this, the operator holds the device 10 of FIG. 1 in his hand, actuates on-off switch 21 to its on position, and actuates selector switch 23 to its closed condition. At the commencement of the first lap, the operator then depresses pushbutton switch 22 momentarily to its on condition, to commence the timing operation. This closure of switch 22 acts through one shot multivibrator 74 to cause shift register 78 to energize transistors 79 and 84 in succession, with the latter functioning to reset

counters

31, 32, 33, and 34 to a zero condition to commence the count. This zero setting is attained on the third pulse of the 1600 Hz signal in line 30, which is almost instantaneously with respect to the actuation of pushbutton 22. Counters 31 through 34 then commence counting of 100 Hz pulses in line 28, to maintain indications in these counters instantaneously representing the time elapsed from initial actuation of switch 22. At the end of that lap, the operator again actuates switch 22, to again energize transistors 79 and 84 in succession, with the first of these transistors energizing latches 35 through 38 to catch in their memories the instantaneous counts in counters 31 through 34, but without interrupting the delivery of the I00 Hz pulses to those countes. The subsequent actuation of transistor 84 resets the counters 31 through 34 to zero, to commence counting for the timing of the next successive lap. Any slight error which might otherwise be caused by the minimal delay which occurs in actuation of transistors 79 and 84 by shift register 78 is avoided by virtue of the fact that the delays which occur on one lap are identical with those which occur on the next successive lap, to thereby compensate for one another.

The counter readings which are caught by latches 35 through 38 act through multiplexer 40 and decoder 57 to control energization of the four

digits

17, 18, 19, and 20, to produce displays corresponding to the instantaneous settings of the counters 31 through 34 at the time of actuation of the latches. Similarly, the digit l6 represents the minutes reading at that time, as previously outlined. All of these

digits

16, 17, 18, 19, and are automatically illuminated for five seconds after actuation of switch 22, by the output signal on line 76 acting through transistors 84 and 87. This five second interval is sufficient time for the operator to view the illuminated digits, following which they are automatically deenergized to conserve battery power until the next successive actuation of switch 22. If the operator wishes to view the instantaneous count in counters 31 through 34 and latches through 38 at any intermediate time, he may merely actuate switch 24 to supply power to the digits to illuminate them. The lap counters 94 and 95

control digits

13 and 14 which indicate the number of laps (the number of actuations of switch 22).

If it is desired to obtain the total time for a series of laps, rather than the individual times of the separate laps, switch 23 is opened after an initial actuation of switch 22 (at the commencement of the first lap) and is kept open thereafter so that the counters 31 to 34 are not reset at the end of each lap, but rather maintain a running total causing display of the total time elapsed on each subsequent actuation of switch 22.

FIG. 3 is a view similar to FIG. 2 but showing a variational circuit which is especially designed to allow the timing of both the lap (or total) time of a particular racer as discussed above, and the split time or lead time between that racer and another car. Most of the circuitry of FIG. 3 is identical with that of FIG. 2, including for example a crystal oscillator 26a, a frequency divider 27a, counters 31a, 32a, 33a, and 34a, latches 35a, 36a, 37a, and 38a, multiplexer 40a, scan counter 42a, scan decoder 43a, decoder 57a, main actuating switch 221:, one shot multivibrator 74a, and shift register 78a, corresponding to the similarly numbered

units

26, 27, 31, 32, 33, 34, 35, 36, 37, 38, 40, 42, 43, 57, 22, 74, and 78 of FIG. 2. Further, FIG. 3 includes four

display digit units

17a, 18a, 19a, and 20a, corresponding to digits 17 through 20 of FIG. 2, and whose sequential energization is controlled by

transistors

49a, 50a, 51a, and 52a. All these various circuit elements are interconnected to function in essentially the same manner as the corresponding units of FIG. 2. The portions of the FIG. 2 circuitry which reset the counters at seconds, and which count minutes, however, are omitted from FIG. 3.

Added to FIG. 3 over and above the circuitry of FIG. 2 is an additional manually operated actuating switch 100, which upon closure supplies an input signal to a second four bit shift register 101, having a transistor 102 which is related to register 101 in the same manner that transistor 79a is related to register 78a, to turn on transistor 102 on the first 1600 cycle pulse of frequency divider 27a, and turn off the transistor on the second pulse. The output from transistor 102 is connected to line 39a to actuate latches 35a through 38a to their count holding condition almost simultaneously with the actuation of switch 100. The signal formed in line 103 upon closure of switch 100 also turns on a transistor 104, which turns on a second transistor 105, to supply power to the decoder 57a for illuminating the

digits

17a, 18a, 19a, and 20a.

In using the FIG. 3 device, assume that the operator has closed selector switch 230 corresponding to switch 23 in FIG. 2, and then desires to measure both lap times and split times in an automobile race. As a first car passes the location of the timer, the user presses pushbutton 22a to supply a signal through one shot multivibrator 74a to shift register 78a, in a manner first energizing latches 35a through 38a to catch the instantaneous counts on counters 31a through 34a, and then resetting the counters, all in a manner previously discussed in connection with FIG. 2. The counters thus commence counting the pulses from frequency divider 27a, to maintain a count representing decimally in seconds the elapsed time since the actuation of switch 22a. When the next successive car passes the same location, the operator presses switch 100, to energize the second shift register 101 in a manner actuating latches 35a through 38a to again remember or catch the instantaneous reading on the counters. Shift register 101 does not, however, reset the counters, but permits them to continue their previous count. The readings which are locked into the latches 35a through 38a are converted to multiplexed BCD signals by multiplexer 40a, and are then decoded to seven segment energizing signals by decoder 57a, to control the energization of the various segments of the four numerals 17a through 20a. Energization of line 106 through

transistors

104 and 105 supplies power to decoder 57a, for illuminating the numerals in the patterns determined by the multiplexed signals from unit 48. These numerals remain illuminated so long as switch remains closed, but go out as soon as that switch is opened. When the first of the two cars again reaches the location of the person doing the timing, he actuates switch 220 again to supply a signal to register 78a through one shot multivibrator 74a. This shift register actuates latches 35a through 38a and resets the counters 31a through 34a. The one shot multivibrator 74a maintains energization of line 106 for a timed five second interval, to illuminate the numerals for that five second period, and then automatically turn the numerals off. As in the case of FIG. 2, each actuation of switch 22a results in a brief display of numerals representing the instantaneous reading of the counters at the time that the switch was actuated, without interrupting the flow of pulses to the countes, so that each lap is timed by the timer, with the periodic displays indicating either individual lap time or total elapsed time as determined by the setting of switch 23a.

While certain specific embodiments of the present invention have been disclosed as typical, the invention is of course not limited to these particular forms, but.

rather is applicable broadly to all such variations as fall within the scope of the appended claims.

We claim:

1. A timer comprising means for generating a series of uniformly timed pulses, counter means for counting said pulses, memory means actuable by said counter means to conditions representing different counts instantaneously attained by said counter means, control means for actuating said memory means at different selected times to remember said instantaneous counts, and display means for producing displays representing said instantaneous counts, said counter means being operable to count said pulses continuously up to a first of said times for inclusion in a first of said displays and t0 thereafter continue to count said pulses from said first time to the next successive one of said selected times for inclusion in the next successive one of said displays, said counter means including a plurality of interconnected decade counters, said memory means including a plurality of latches for remembering instantaneous settings of said decade counters respectively, said control means including an element manually actuable to operate said latches to remember an instantaneous count in said decade counters without interrupting operation of the decade counters, so that the decade counters count both before and after actuation of the latches, said display means including multiplexer means responsive to said latches to produce multiplexed binary coded decimal signals representing the settings of said latches respectively, and means for producing a plurality of display digits dependent upon said signals and representing decimally the times remembered by said latches.

2. A timer as recited in claim 1, in which said signals from said multiplexer means represent times in seconds, there being circuitry connected to said multiplexer means and responsive to said signals therefrom and operable to reset said counters upon attainment of the sixty second count.

3. A timer as recited in claim 1, in which said signals from said multiplexer means represent a seconds count,

there being means responsive to said signals upon attainment of a sixty second count to produce a minutes display.

4. A timer as recited in claim 1, including circuitry for resetting said counter means automatically upon each actuation of said control means, said circuitry containing switching means operable to disable the circuitry to selectively condition the counter means either for said automatic resetting upon actuation of the control means or for a continued count without resetting upon actuation of the control means.

5. A timer as recited in claim 1, in which said element is a first manually actuable switch for actuating said latches to remember an instantaneous count without interrupting operation of the decade counters, said control means including also a second separately manually actuable switch operable to actuate said latches to remember an instantaneous setting in the counter means, there being circuitry operable upon actuation of said second switch to reset said decade counters.

6. A timer as recited in claim 1, in which said element is a first manually actuable switch, said control means including also a first shift register actuable by said switch, a second shift register, a second separately manually operable switch for actuating said second shift register, circuitry operable by said second shift register upon actuation of said second switch to actuate said latches to instantaneously remember the setting of said decade counters, and then reset the counters, and additional circuitry actuable by said first shift register upon operation of said first switch to actuate said latches to remember the instantaneous setting of said decade counters, without resetting of the counters.

7. A timer as recited in claim 6, in which said first mentioned circuitry contains a disabling switch for selectively conditioning said circuitry to either reset the counter means as stated or avoid such resetting upon operation of the corresponding shift register.

8. A timer comprising means for generating a series of uniformly timed pulses, counter means for counting said pulses, memory means actuable by said counter means to conditions representing different counts instantaneously attained by said counter means, control means for actuating said memory means at different selected times to remember said instantaneous counts, and display means for producing displays representing said instantaneous counts, said counter means being operable to count said pulses continuously up to a first of said times for inclusion in a first of said displays and to thereafter continue to count said pulses from said first time to the next successive one of said selected times for inclusion in the next successive one of said displays, said pulse generating means including an oscillator and a frequency divider actuable thereby, said counter means including a plurality of interconnected decade counters representing decimally a time in seconds, said memory means including a plurality of latches for remembering the instantaneous settings of said different counters respectively, said control means including a manually actuable switch for determining the instant at which a time reading is to be taken, a one shot multivibrator actuable by said switch and acting to maintain each of said displays for a predetermined interval and then automatically discontinue the display, a shift register operable upon actuation of said switch to first actuate said latches to remember the instantaneous setting of said counter, and then automatically reset said counters to zero, said display means including a multiplexer responsive to said latches and having output lines carrying multiplexed signals representing the settings of said latches, a decoder responsive to said signals, and means actuable by said decoder to produce a series of display digits representing decimally the setting of said latches in seconds.

9. A timer as recited in claim 8, including additional counter means actuable by said shift register upon each actuation of said switch to count the number of actuations of the switch.

10. A timer as recited in claim 8, including means actuable by said signals from said multiplexer and responsive to the attainment of a sixty second count to automatically reset said counters, and means responsive to said last mentioned means to produce a digital display representing minutes timed.

11. A timer as recited in claim 10, in which said control means include an additional switch actuable manually and separately from said first switch, and an additional shift register actuable by said additional switch to actuate said latches to remember the settings of said counters but to do so without resetting of the counters.

Claims

1. A timer comprising means for generating a series of uniformly timed pulses, counter means for counting said pulses, memory means actuable by said counter means to conditions representing different counts instantaneously attained by said counter means, control means for actuating said memory means at different selected times to remember said instantaneous counts, and display means for producing displays representing said instantaneous counts, said counter means being operable to count said pulses continuously up to a first of said times for inclusion in a first of said displays and to thereafter continue to count said pulses from said first time to the next successive one of said selected times for inclusion in the next successive one of said displays, said counter means including a plurality of interconnected decade counters, said memory means including a plurality of latches for remembering instantaneous settings of said decade counters respectively, said control means including an element manually actuable to operate said latches to remember an instantaneous count in said decade counters without interrupting operation of the decade counters, so that the decade counters count both before and after actuation of the latches, said display means including multiplexer means responsive to said latches to produce multiplexed binary coded decimal signals representing the settings of said latches respectively, and means for producing a plurality of display digits dependent upon said signals and representing decimally the times remembered by said latches.

3. A timer as recited in claim 1, in which said signals from said multiplexer means represent a seconds count, there being means responsive to said signals upon attainment of a sixty second count to produce a minutes display.