US3798632A

US3798632A - Parallel addressed, multiplexed-driver plasma display system and method

Info

Publication number: US3798632A
Application number: US00259128A
Authority: US
Inventors: D Liddle
Original assignee: Owens Illinois Inc
Current assignee: Techneglas LLC
Priority date: 1972-06-02
Filing date: 1972-06-02
Publication date: 1974-03-19
Anticipated expiration: 1991-03-19
Also published as: GB1436388A; CA1009329A; FR2187154A5; DE2327483A1; JPS4963343A; IT985643B

Abstract

There is disclosed a plasma display system which permits the simultaneous addressing of an entire multiplex group (16-line sector) without an increase in the number of driving or mixing elements. This allows an entire sector to be addressed each 20 microseconds, rather than a single point, and reduces the full display screen update time from 5.24 seconds to 0.33 seconds. Run-length coding provides an efficient way to store and transmit pictures for the display, rather than a complete 260Kbit map. An external interface containing a simple serial/parallel shift register cascade allows the codes to be translated into a single-sector bit map of only 8K bits. Two such local buffers used alternately allow a continuous stream of runlength codes to be accepted by the interface while allowing the display to write at full speed.

Description

Uil Iii States atet [191 Liddle Mar. 19, 1974 Primary Examiner-David L. Trafton Attorney, Agent, or Firm-Donald Keith Wedding; Jim Zegeer [75] Inventor: David E. Liddle, Toledo, Ohio [57] ABSTRACT [73] Assigneez Owens-Illinois, Inc., Toledo, OhlO There is disclosed a plasma display system which perl Filedi J 2, 1972 mits the simultaneous addressing of an entire multi- 2 1 N I: 259,128 plex group (l6-line sector) without an increase in the 1] App 0 number of driving or mixing elements. This allows an entire sector to be addressed each 20 microseconds, [1.5. C]. 340/324 M, 3 5/1 340/166 L, rather than a single point, and reduces the full display 340/343 screen update time from 5.24 seconds to 0.33 sec- [51] Int. Cl. G08b 5/36 d [58] held of Search ggif' g k ii Run-length coding provides an efficient way to store and transmit pictures for the display, rather than a complete 26OK-bit map. An external interface [56] References Cned containing a simple serial/parallel shift register UNITED STATES PATENTS cascade allows the codes to be translated into 8. 3,600,626 8/1971 Kupsky 340/324 M single-sector bit map of only 8K bits. Two such local 3.609.746 9/1971 Trogdon 340/324 M buffers used alternately allow a continuous stream of 6 5/1972 Lcuck r 340/166 EL run-length codes to be accepted by the interface while 3.668,688 6/1972 Schmersal 340/324 M allowing the to Write at p t 3.686.661 8/1972 Sharpless 340/324 M 7 Claims, 5 Drawing Figures RUN LENGTH DATA l l l l 6/ SECTOR COUNTER BUFFER A 0 [5 62 4 572 H/GH SPEED STEER/N STEERING p CLOCK LOG/C LOG/C a.

LOW SPEED SECTOR CLOCK DISPLAY BUFFER B READY FLAG (FIG. .3)

INTERFACE USING DUAL BUFFERS PATENTEDMR m4 3798.632

SHEET 1 0F 2 /5 /6 RESISTOR 0/005 RESISTOR 0/005 MULT/PLEX c/Fecu/Ts MULT/PLEX c/Fzcu/Ts 04774 & CONT/20L RUN LENGTH DA m L l l i {6/ SECTOR COUNTER r*=* BUFFER A (FIGS) 3 /5 5 H/GH 5, 550 STEER/N STEER/NG CLOCK LOG/C LOG/C 0-!5 LOW SPEED TOR CLOCK DISPLAY BUFFER 0 READY FLAG (FIG. 3)

INTERFACE USING DUAL BUFFERS FIG. 4

PATENTEMR 19 I974 i F I 5 F/GI. 2b

SUSTA/NER SHEET 2 OF 2 Y PARALLEL INPUTS PARALLEL ADDRESS SYSTEM FIG. 2a

I LOAD/SCAN CONTROL 36 so X i?- /NPUT r'CLOCK L/NE BUFFER /5 L/NE BUFFER l4 70 D/SPLA V DATA INPUTS :D PM

,20 g L/NE BUFFER 0 g;

DETAIL OF SERIAL/PARALLEL SECTOR BUFFER FIG. 3

PARALLEL ADDRESSED, MULTlPLEXED-DRIVER PLASMA DISPLAY SYSTEM AND lVmTI-IOD INTRODUCTION AND BRIEF DESCRIPTION OF INVENTION The concept of simultaneously addressing all the electrodes in one axis of a plasma display has frequently been discussed (Bitzer & Slottow, Principles and Applications of the Plasma Display Panel," Proceedings of IEEE Microelectronics Symposium, 1968), and was implemented several years ago on a small (128 X 128 lines) display by the assignee herein, Owens-Illinois, Inc. Although this technique greatly increases the writing speed of the display, it has the disadvantage of requiring an independent, active driver on every line.

Group multiplexing techniques have been applied to plasma display systems, which address a single line at a time, in order to reduce the number of active drivers required. This invention relates an adaptation of this technique, in which the multiplexed elements are organized to permit an entire group of 16 lines, for example, to be addressed in parallel without increasing the number of active drivers required. In addition, an external interface and a compact data structure are disclosed, which allow efficient picture generation in the parallel mode of operation.

The standard serial mode of operation is most useful for vector generation, curve plotting, and producing characters of various sizes. Parallel operation is preferable where large blocks of text must be displayed, or an entire 5 l 2 X 512 line picture" rapidly updated. In this case, the serial mode writes 1,400 characters/second, or updates the display in 5.24 seconds, while the parallel mode of operation can produce text at 10,000 characters/second, and update the display in 0.33 seconds. The display unit has two 9-bit address registers (X and Y). a 16-bit data register, and control lines to produce write, erase, and clear commands and to select the mode of operation (serial or parallel).

The technique of run-length coding, developed for digital television applications, provides an efficient data structure in which each code tells the display how many successive cells are to be ON or OFF as a single raster is scanned from left to right. This technique reduces memory and transmission requirements, but allows only a single line to be scanned at a time.

In the present invention run-length coding is used with the l6-line parallel display by an external interface which decodes the incoming run-length codes serially into an 8K-bit map, and then scans its map 16 bits at a time into a sector of the display panel. The invention while being applicable because of the inherent memory of the display panel, it is not necessary for the entire 262K-bit map to exist at one time, and so only 8K bits of local buffer (enough for one sector) are required in the external interface.

Ordinary interfaces utilizing run-length codes scan only one line at a time, reducing display speed greatly. Other data structures require the storage and transmission of very large amounts of data (26K bits).

This invention avoids these problems in that it allows use of parallel address display (for increased writing speed) while utilizing a run-length code data structure, which greatly reduces computer memory and data transmission requirements. The invention features inelude: l Serial/parallel operation of the sector buffer (serial input/parallel output); (2) Use of temporary" bit map of only one panel sector at a time; (3) Alternately loading one bufier while scanning from another to achieve uninterrupted input/output.

The above and other objects, advantages and features of the invention will become more apparent from the following specification, considered with the accompanying drawings wherein:

FIG. 1 is a block diagram of a plasma panel display system incorporating the invention,

FIG. 2A is a diagramatic illustration of a resistor diode multiplex system modified in accordance with the invention for parallel panel addressing,

FIG. 2(b) shows one resistor-diode element of the circuit of FIG. 2A,

FIG. 3 is a diagramatic illustration of the serial/parallel sector buffer system and,

FIG. 4 is a block diagram of the interface using dual buffers.

In FIG. 1, the panel P is a display panel (described in greater detail in Baker et al. US. Pat. No. 3,499,167 and other patents of the assignee hereof) constituted by row and column conductor support plates RS and CS, respectively, carrying a plurality of row conductors l0 and a plurality of column conductors 11, respectively. The conductors are coated with a dielectric or insulating coating or layer (not shown) and the plates are joined in spaced relation by a spacer sealant 12 to form a thin gas chamber in which is placed a working or electroresponsive medium, preferably under pressure. It will be appreciated that other electroresponsive mediums may be used, but the preferred embodiment disclosed herein uses a neon-argon gas mixture (99.9% Ne, 0.1% Ar at a pressure of about 600 Torr) as the working medium between the transverse conductor arrays 10 and 11.

The row conductors R are supplied with operating (sustaining and discharge condition manipulating) voltages by way of a row resistor-diode multiplex circuit 15 and the column conductor 11 receive operating (sustaining and discharge condition manipulating) voltages from column resistor-diode multiplex circuit 16, both said multiplex circuits effectively electrically floating on their sustainer generators VSR and VSC, respectively, which have a point of common potential, S. G. Data and control 17 supplies timing control signals to

multiplex circuits

15 and 16 and the row and column sustainer circuits VSR and VSC and include the circuits of FIGS. 3 and 4 hereof.

The basic resistor-diode multiplex scheme of FIG. 2B is described in a paper by Johnson and Schmersal entitled A Quarter-Million-Element AC Plasma Display with Memory, Digest of Papers, SID International Symposium and Exhibition, May 1971), in which each line of the 512 X5 12 line plasma panel connects to two diodes D and D and a resistor R. One diode D provides a current path for the sustaining signal a. The resistor R and remaining diode D perform an AND function, in which a writing pulse is applied to a group of resistors from a voltage pulser for the resistors, R R R and R The entire pulse voltage is dropped across those resistors whose associated diodes D are forward-biased, while a diode D which is back-biased or floating causes the pulse to be applied to the selected panel electrode. Whether a diode is forward biased or back-biased is controlled by diode control circuits D D D D which, with voltage pulsers R R,, R R receive controlling signals from the circuits of FIGS. 3 and 4.

In the modified parallel address system according to this invention, the resistor pulsers and diode switches are grouped in such a way that the selection of single diode switch enables one of 32 sectors of 16 panel lines, i.e., lines 0-15, 16-31, etc. (see FIG. 2). Within this sector, any or all of the 16 lines may be simultaneously addressed by selecting the desired corresponding resistor pulsers R R R etc. It should be noted that, for each line selected in the enabled sector, the pulse voltage is dropped across the corresponding resistor in 31 other sectors, drawing current which is not used in addressing a cell. This situation could be altered by selecting the sectors by resistor pulser and individual lines by diode switch, and thus never energizing more than 16 resistors at one time. However, since the diodes actually used are mounted in dual inline packages (not shown), considerable space and interconnection wiring is saved in grouping the diodes together. Moreover, since the required writing pulse occurs for only about 2 microseconds, with a microsecond period, the actual power dissipation in the resistors is not excessive, and the scheme of selecting a sector via a diode switch and the individual lines via resistor pulsers was implemented. The sustainer VS is shown as having the return connection a via diode D,,.

SERIAL AND PARALLEL OPERATION The standard serial mode of operation is most useful for vector generation, curve plotting, and producing characters of various sizes. Parallel operation is preferable where large blocks of text must be displayed, or an entire 5 l 2 X 512 line picture rapidly updated. In this case, the serial mode writes 1,400 characters/second, or updates the display in 5.24 seconds, while the paral lel mode of operation can produce text at 10,000 characters/second, and update the display in 0.33 seconds. The display unit has two 9-bit address registers (X and Y), a l6-bit data register, and control lines to produce write, erase, and clear commands and to select the mode of operation (serial or parallel).

A DATA STRUCTURE AND INTERFACE FOR PICTURE GENERATION The technique of run-length coding, developed for digital television applications, provides an efficient data structure in which each code tells the display how many successive cells are to be ON or OFF as a single raster is scanned from left to right. This technique reduces memory and transmission requirements, but allows only a single line be scanned at a time.

In accordance with this invention, run-length coding is adapted for use with the l6-line parallel display by an external interface which decodes the incoming runlength codes serially into an 8K-bit map, and then scans this map 16 bits at a time into a sector of the display panel. Because of the inherent memory of the display panel, it is not necessary for the entire 262K-bit map to exist at one time, and so only 8K bits of local buffer (enough for one sector) are required in the external interface.

As shown in FIG. 3 the interface for decoding the run-length data and assembling it in the sector buffer is straightforward. The buffer consists of sixteen 512- bit MOS shift registers 20, 21 36, initially connected in cascade (series). In FIG. 3, the cascade connection of the registers is established by AND

gates

40, 41, 42 55, which have a load signal from control 17 via inverter l as one input and the output of its associated register as a second input, with the output of each AND gate being supplied to the next register in the sequence. The output from the line buffers to display data inputs occurs from AND Gates 80, 81, 82, on receipt of a scan input signal on the load/scan control line.

Referring to FIG. 4, the incoming codes are loaded into a preset counter 61, which enables a high-speed clock 62 to shift in the appropriate number of ones or zeros. When the entire buffer is full, each of the l6 shift registers is separately connected to one of the 16 display data inputs by a steering logic network 64, and the data is shifted out of each shift register 2036 (FIG. 3) and simultaneously displayed as the sector is scanned from left to right, by a low-speed clock 63 enabled by the display unit ready" line at the 50 KHz display unit speed.

If the high-speed clock 62 is run at 800 KHz, the entire buffer is loaded in 10 milliseconds, which is exactly the time required to scan one display sector. If two such 8K buffers are used alternately, one may be loaded while the other is scanned, and the display can accept an uninterrupted stream of run-length codes while writing at full speed. Steering logic 72 is used to control the alternate loading and scanning of sector buffers A and 8.

SUMMARY A serial-type 512 line plasma display unit can thus be reorganized to permit the simultaneous addressing of an entire multiplex group (lo-line sector) without an increase in the number of driving or mixing elements. This allows an entire sector to be addressed each 20 mi croseconds, rather than a single point, and reduces the full screen update time from 5.24 seconds to 0.33 sec onds.

Run-length coding provides an efficient way to store and transmit pictures for the display, rather than a complete 260K-bit map. An external interface containing a simple serial/parallel shift register cascade allows the codes to be translated into a single-sector bit map of only 8K bits. Two such local buffers used alternately allow a continuous stream of run-length codes to be accepted by the interface while allowing the display to write at full speed.

While the invention has been described with reference to a specific embodiment thereof it will be appreciated that various adaptations and modifications thereof, obvious to those skilled in the art, are possible and it is intended that the claims hereof encompass such adaptations and modifications.

What is claimed is:

1. In combination with a matrix display panel system having a plurality of matrix display points defined by selectively energizable row-column conductor pairs for entry of information to said display panel and an electrosponsive medium between said row-column pairs, and a source of serial run-length coded data bits,

means for translating said serial coded data bits for a selected panel sector to parallel data bit format and storing same,

means for transferring said stored data bits for each said selected panel sector to the selected panel sector to energize matrix display points therein according to said parallel data bit format.

2. The invention defined in claim 1 wherein said storage means includes at least a second of said means for translating,

first steering logic means for alternately and sequentially directing said run-length coded data to each said translating means, respectively, and,

second steering logic means for selecting individual ones of said translating means and controlling the transfer of information in said parallel data bit format to said panel.

3. The invention defined in claim 2 wherein said runlength coded data bits are provided at a first rate of speed and said parallel data bits are supplied to said panel at a significantly different second rate of speed.

4. The invention defined in claim 1 wherein said means for translating includes a plurality of line buffer shift registers, means alternately connecting said line buffer shift registers in cascade for input of said runlength coded data and in parallel for output of said parallel data bit format, respectively.

5. In a gas discharge display panel having inherent memory, a plurality of matrix display points defined by selectively energizable row-column conductor pairs for entry of information to said display panel and gas medium between said row-column pairs, means for applying a periodic sustaining voltage to said cross points and a source of serial run-length coded data bits,

means for translating said serial coded data bits for a selected panel size to parallel data bit format and storing same,

means for transferring said stored data bits for each said selected panel sector to the selected panel sector and cooperatively with said sustainer voltage manipulate the discharge condition of matrix display points therein according to said parallel data bit format.

6. The invention defined in claim 5 wherein said means for translating includes a plurality of serial/parallel shift registers for translating said run-length coded signals to a single sector bit map having a selected number of discrete information bits and delivering said single sector bit map to said panel.

7. In a crossed conductor matrix display panel system wherein digital display information is received in serial format, the method of entering display information to said panel comprising:

Step 1. converting and storing the received serial format information to parallel format for a selected number of lines of one of the array of crossed conductors at one selected rate of speed,

Step 2. converting and storing the received serial format information for a like related number of lines of the same array of crossed conductors at said one rate of speed and simultaneously at a second selected rate of speed transferring the stored parallel format information of step 1 to display on said display panel,

and repeating steps 1) and 2) respectively in the above sequence at least one further time to complete entry of the desired information to said panel.

l l i

Claims

1. In combination with a matrix display panel system having a plurality of matrix display points defined by selectively energizable row-column conductor pairs for entry of information to said display panel and an electrosponsive medium between said row-column pairs, and a source of serial run-length coded data bits, means for translating said serial coded data bits for a selected panel sector to parallel data bit format and storing same, means for transferring said stored data bits for each said selected panel sector to the selected panel sector to energize matrix display points therein according to said parallel data bit format.

2. The invention defined in claim 1 wherein said storage means includes at least a second of said means for translating, first steering logic means for alternately and sequentially directing said run-length coded data to each said translating means, respectively, and, second steering logic means for selecting individual ones of said translating means and controlling the transfer of information in said parallel data bit format to said panEl.

3. The invention defined in claim 2 wherein said run-length coded data bits are provided at a first rate of speed and said parallel data bits are supplied to said panel at a significantly different second rate of speed.

4. The invention defined in claim 1 wherein said means for translating includes a plurality of line buffer shift registers, means alternately connecting said line buffer shift registers in cascade for input of said run-length coded data and in parallel for output of said parallel data bit format, respectively.

5. In a gas discharge display panel having inherent memory, a plurality of matrix display points defined by selectively energizable row-column conductor pairs for entry of information to said display panel and gas medium between said row-column pairs, means for applying a periodic sustaining voltage to said cross points and a source of serial run-length coded data bits, means for translating said serial coded data bits for a selected panel size to parallel data bit format and storing same, means for transferring said stored data bits for each said selected panel sector to the selected panel sector and cooperatively with said sustainer voltage manipulate the discharge condition of matrix display points therein according to said parallel data bit format.

7. In a crossed conductor matrix display panel system wherein digital display information is received in serial format, the method of entering display information to said panel comprising: Step 1. converting and storing the received serial format information to parallel format for a selected number of lines of one of the array of crossed conductors at one selected rate of speed, Step 2. converting and storing the received serial format information for a like related number of lines of the same array of crossed conductors at said one rate of speed and simultaneously at a second selected rate of speed transferring the stored parallel format information of step 1) to display on said display panel, and repeating steps 1) and 2) respectively in the above sequence at least one further time to complete entry of the desired information to said panel.