US3796597A - Method of producing semiconducting monocrystalline silicon on spinel substrates - Google Patents
Method of producing semiconducting monocrystalline silicon on spinel substrates Download PDFInfo
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- US3796597A US3796597A US00086205A US3796597DA US3796597A US 3796597 A US3796597 A US 3796597A US 00086205 A US00086205 A US 00086205A US 3796597D A US3796597D A US 3796597DA US 3796597 A US3796597 A US 3796597A
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- 239000000758 substrate Substances 0.000 title abstract description 32
- 238000000034 method Methods 0.000 title abstract description 28
- 229910052596 spinel Inorganic materials 0.000 title description 17
- 239000011029 spinel Substances 0.000 title description 17
- 229910021421 monocrystalline silicon Inorganic materials 0.000 title description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 18
- 239000010703 silicon Substances 0.000 abstract description 18
- 239000000203 mixture Substances 0.000 abstract description 17
- 239000004065 semiconductor Substances 0.000 abstract description 15
- 239000000463 material Substances 0.000 abstract description 8
- 239000003989 dielectric material Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 17
- 238000010438 heat treatment Methods 0.000 description 11
- 239000013078 crystal Substances 0.000 description 8
- 238000000151 deposition Methods 0.000 description 7
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 6
- 230000007547 defect Effects 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 239000001257 hydrogen Substances 0.000 description 6
- 229910052739 hydrogen Inorganic materials 0.000 description 6
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 4
- 238000002003 electron diffraction Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 239000002344 surface layer Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000000563 Verneuil process Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000002939 deleterious effect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 2
- 235000020004 porter Nutrition 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/03—Manufacture or treatment wherein the substrate comprises sapphire, e.g. silicon-on-sapphire [SOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/025—Deposition multi-step
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/053—Field effect transistors fets
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/097—Lattice strain and defects
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/15—Silicon on sapphire SOS
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/967—Semiconductor on specified insulator
Definitions
- This invention relates to semiconductor-on-insulator (SOI) electronic device manufacture and, more specifically, to an improved method of producing monocrystalline silicon on spinel.
- SOI semiconductor-on-insulator
- the invention is directed to a method of producing single crystal semiconducting layers epitaxially on insulating substrate crystals and particularly to improvement in the art as taught in US. Pats. 3,414,434, M. Manasevit and 3,424,955, H. Seiter and C. Zaminer.
- MgO-xAl O One of the problems that arises with the growth of monocrystalline semiconductor layers on variable composition insulating spinel crystals such as MgO-xAl O is that the chemical composition for optimum growth of the spinel is very closely MgO-1Al O whereas the optimum chemical composition for growth of monocrystalline silicon thereon is MgO-xAl O where x is between 1.05 and 1.1.
- MgO-AI O spinel is readily grown by the Czochralski technique, is crystallographically quite perfect, and has no inherent limitations upon diameter.
- MgO-xAl O spinel wherein x is greater than 1, may be grown by the Verneuil or flame fusion technique, but the diameter is essentially limited to less than 1 inch by problems with cracking of the boule, and the crystalline quality is low because of grain boundaries. It is an object of this invention to provide a method utilizing the Czochralski-grown material of composition very nearly MgO-Al O and of high perfection by shifting the composition of the surface layer toward a more desirable composition with regard to deposition of the semiconductor material. It is a further object of the invention to .provide a method wherein a high degree of crystallographic perfection of the insulating surface is achieved while accomplishing the shift of composition. A further object of the invention is to provide a method achieving a greater degree of crystal quality than gained by flame fusion techniques.
- the present invention may be generally described as a heat treatment of the insulating substrate in a stream of reducing gas such as hydrogen while maintaining the substrate within a relatively narrow temperature range so that MgO will be preferentially removed from the surface layer until the layer reduces an optimum composition with regard to deposition and, at the same time, any amorphous spinel material left from the polishing procedure is converted to-well-oriented spinel of high perfection.
- the time and temperature are controlled so that deleterious defects such as grain boundaries, twins, and high concentrations of dislocations are not permitted to arise in the spinel.
- the epitaxial layer of silicon is deposited thereon, said layer similarly exhibits a high degree of perfection.
- FIG. 1 is a cross-section of a starting substrate in accordance with the invention
- FIG. 2 is a cross-section of the substrate after heat treating
- FIG. 3 is a cross-section of the substrate with the semiconductor layer thereon;
- FIG. 4 is a cross-section of the substrate with semiconductor devices diffused and isolated in the semiconductor layer
- FIG. 5 is a standard insulated gate field effect transistor
- FIG. 6 is an insulated gate field effect transistor from a silicon-on-insulator substrate.
- This substrate 10 is a (111) slice from a boule of monocrystalline MgO-Al O grown by the Czochralski technique. This technique has been found to produce crystals which are essentially perfect.
- the substrate 10 may be obtained from the 'boule by any appropriate technique as, for example, sawing. 'Ihe slice is then polished to remove any marks resulting from the slicing operation.
- the substrate 10 therefore has surfaces which, when tested by electron diffraction techniques, are found to be essentially amorphous.
- the surface upon which the monocrystalline semiconductor is to be deposited must be converted to a proper crystal structure before such deposition and surface annealing or chemical etch have been previously suggested as suitable for this purpose.
- the substrate 10 may be placed in a suitable reactor, heat treated at a temperature between 1040 C. and 1145 C. and in a reducing hydrogen atmosphere to recrystallize the amorphous surface region and preferentially remove MgO in the surface layer 12 (FIG. 2) to produce monocrystalline MgO-xAl O wherein x, is between 1.05 and 1.1.
- the temperature of theheat treatment must. be controlled to assure conversion of theentire surface of the substrate 10 to the desired composition without producing deleterious defects such as cracks, twins and dislocations. These defects are found tobe created to an unacceptable level when the substrate is heated over 1145" C.
- the substrate 10 with layer ,11 thereon is a monocrystalline semiconductor layer 13 preferably of silicon (FIG. 3).
- the layer 13 can be conveniently epitaxially produced as a further step in the same reactor as the heat treatment by changing the hydrogen atmosphere to a mixture of 0.3% silane in hydrogen with a phosphine dopant.
- the layer 13 could be produced by any appropriate epitaxial technique with or without dopant material added; From the foregoing, thereis thus provided a semiconductor-on-insulator structure suitable for the manufacture of semiconductor devices and integrated'circuits.
- an array of semiconductor dioxides 15 may be produced in the epitaxial layer 13 by suitable masking and diifusion techniques as are wellknown. Etching of openings 14 through the epitaxial layer provides electric isolation between diodes.
- Example IA slice .020 inch thick was cut from a 1% inch diameter boule of Czochralski-grown spinel crystal and polished.
- the crystal orientation of the slice was approximately 111) and its composition very nearly Electron diffraction by reflected high energy electrons revealed that the surface layers were essentially amorphous, due to the slicing and polishing processes.
- the slice was heated in hydrogen gas along with a high resistivity bulk silicon control slice on a silicon carbide coated susceptor for two hours at a temperature of 1116 C., after which a two micron silicon layer was epitaxially deposited on both samples from a .3% silane-in-hydrogen mixture at a deposition temperature of approximately 1080 C.
- a phosphine dopant was added to the deposition gas stream so that the silicon layer on silicon was ndoped to .15 ohm-cm.
- the silicon-onspinel was again subjected to reflected high energy electron difr'raction and to X-ray measurements.
- the results of electron diffraction showed excellent single crystal silicon films, with no twins and a good Kikuchi diagram pattern.
- the resistivity across the slice was .40i.05 ohmcm.
- the silicon on spinel can be said to have a merit factor of as defined by Mercier in the Journal of the Electrochemical Society 117, No. 5, p. 666 (1970).
- the surface composition lay in the range where x was between 1.05 and 1.1.
- Example II-Another MgO-Al O spinel slice was treated as in Example I, except that the time of heat treatment was only /zhour.
- the electron diffraction results were the same, i.e., high quality silicon.
- only the edges showed substantial M-gO removal to produce at between 1.05 and 1.1.
- the average resistivity was now 1.30 ohm-cm, or a merit factor of 11.7%.
- the composition was not.
- Example IIIAnother slice was treated as in Example I, except that the time of treatment at 1116 C. was only minutes. This time the resistivity was uniform within i% over the entire slice, but its magnitude was 1.03 ohm-cm., which corresponds to a 16% merit figure. Thus, 10 minutes is too short a time for the heat treatment to achieve the crystallographic perfection of the slice in Example I.
- Example IVAnother slice was treated as in Example I, except that the temperature and time of heat treatment were 1200 C. and one hour respectively.
- the deposited silicon had a merit factor of 28% but now showed a series of steps that would make the slice unacceptable for defect content.
- the defect stemmed from cracks in the silicon.
- a temperature of heat treatment of 1200 C. is too hot for maintaining surface quality at an acceptable level.
- Example VAnother slice was treated as in Example 1, except that the temperature and time of heat treatment were 1145 C. and two hours, respectively.
- the deposited silicon had a merit factor of 37.6% but also showed a series of steps that would generally make the slice unacceptable for defect content. Thus, a temperature of 1145 C. is too high for maintaining surface quality with great consistency.
- Example VIAnother slice was treated as in Example I, except that the temperature and time of heat treatment were 1100 C. and two hours, respectively.
- the deposited silicon had a merit factor of 38.1% and was free of the steps resulting in Examples IV and V.
- heat trelatment at 1100 C. for two hours gives acceptable resu ts.
- FIGS. 5 and 6 illustrate insulated gate field eflect transistors on a standard silicon substrate and on a spinel substrate made in accordance with the invention.
- the standard device 20 includes a gate electrode 21 on dielectrio 22 overlying a channel 23 defined between source and drain diffusion 24, 25. Electrodes 26 and 27 make ohmic contact with the ditfusions and overlie the insulating layer 28.
- the inherent capacitanees in the device of this type are the lead capacitance (C between electrodes and substrate, junction capacitance (C between diffusions and substrate, and the Miller capacitance (C between gate electrode 21 and the channel 23.
- the insulated gate field eifect transistor 30 includes a gate electrode 31 on dielectric layer 32 overlying a channel 33 defined by a diffusion 34.
- the source 35 and drain 36 are of the epitaxial silicon from the foregoing process. Electrodes 37 and 38 make electrical contact with regions 35 and 36 and lie directly on the spinel substrate. With the latter construction, the lead capacitance (C becomes approximately 0 and the junction capacitance (C and Miller capacitance (C greatly reduced. A comparison of electrical characteristics is as follows:
- a method of producing monocrystalline semiconductor-on-insulator comprising:
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Abstract
THERE IS DISCLOSED AN IMPROVED METHOD OF PRODUCING MONOCRYSTALLINE SEMICONDUCTOR MATERIAL ON A SUBSTRATE OF DIELECTRIC MATERIAL. THE METHOD COMPRISES HEAT TREATING OF THE SUBSTRATE, SPECIFICALLY MGO.AL2O3 SPINEL TO MODIFY THE COMPOSITION OF ITS SURFACE AND THEN GROWING
A MONOCRYSTALLINE SEMICONDUCTOR MATERIAL, SILICON, THEREON. RESULTANT SEMICONDUCTOR DEVICES HAVE DEMONSTRATED IMPROVED SWITCHING SPEED.
A MONOCRYSTALLINE SEMICONDUCTOR MATERIAL, SILICON, THEREON. RESULTANT SEMICONDUCTOR DEVICES HAVE DEMONSTRATED IMPROVED SWITCHING SPEED.
Description
Mmh'u, 1974 v. R. PORTER ETAL 3,796,597
METHOD OF PRODUCING SEMICONDUCTING MONOCRYSTALLINE SILICON ON SPINEL SUBSTRATES Find Nov. 2. 1970 2 SheetseeSheet 1 l3 fS/h'can/ \i\\ K V// Lawrence 0 Dyer ATTOR/Vf) March 12, 1974 v v. R. PORTER ETAL 3,796,597
METHOD OF PRODUCING SEMICONDUCTING MONOCRYSTALLINE SILICON ON SPINEL SUBSTRATES Filed Nov. 2, 1970 2 Sheets-Sheet I \h I i 1/ NS PE SILICON United States Patent 3,796,597 METHOD OF PRODUCING SEMICONDUCTING MONOCRYSTALLINE SILICON ON SPINEL SUBSTRATES Vernon R. Porter and Lawrence Dean Dyer, Richardson, Tex., assignors to Texas Instruments Incorporated, Dallas, Tex.
Filed Nov. 2, 1970, Ser. No. 86,205 Int. Cl. B44d N18 US. Cl. 117-213 3 Claims ABSTRACT OF THE DISCLOSURE There is disclosed an improved method of producing monocrystalline semiconductor material on a substrate of dielectric material. The method comprises heat treating of the substrate, specifically MgO-Al O spinel to modify the composition of its surface and then growing 'a monocrystalline semiconductor material, silicon, thereon. Resultant semiconductor devices have demonstrated improved switching speed.
This invention relates to semiconductor-on-insulator (SOI) electronic device manufacture and, more specifically, to an improved method of producing monocrystalline silicon on spinel.
'The invention is directed to a method of producing single crystal semiconducting layers epitaxially on insulating substrate crystals and particularly to improvement in the art as taught in US. Pats. 3,414,434, M. Manasevit and 3,424,955, H. Seiter and C. Zaminer.
One of the problems that arises with the growth of monocrystalline semiconductor layers on variable composition insulating spinel crystals such as MgO-xAl O is that the chemical composition for optimum growth of the spinel is very closely MgO-1Al O whereas the optimum chemical composition for growth of monocrystalline silicon thereon is MgO-xAl O where x is between 1.05 and 1.1. MgO-AI O spinel is readily grown by the Czochralski technique, is crystallographically quite perfect, and has no inherent limitations upon diameter. MgO-xAl O spinel, wherein x is greater than 1, may be grown by the Verneuil or flame fusion technique, but the diameter is essentially limited to less than 1 inch by problems with cracking of the boule, and the crystalline quality is low because of grain boundaries. It is an object of this invention to provide a method utilizing the Czochralski-grown material of composition very nearly MgO-Al O and of high perfection by shifting the composition of the surface layer toward a more desirable composition with regard to deposition of the semiconductor material. It is a further object of the invention to .provide a method wherein a high degree of crystallographic perfection of the insulating surface is achieved while accomplishing the shift of composition. A further object of the invention is to provide a method achieving a greater degree of crystal quality than gained by flame fusion techniques.
The present invention may be generally described as a heat treatment of the insulating substrate in a stream of reducing gas such as hydrogen while maintaining the substrate within a relatively narrow temperature range so that MgO will be preferentially removed from the surface layer until the layer reduces an optimum composition with regard to deposition and, at the same time, any amorphous spinel material left from the polishing procedure is converted to-well-oriented spinel of high perfection. The time and temperature are controlled so that deleterious defects such as grain boundaries, twins, and high concentrations of dislocations are not permitted to arise in the spinel. Thus, when the epitaxial layer of silicon is deposited thereon, said layer similarly exhibits a high degree of perfection.
Patented Mar. 12, 1974 ice Further objects and advantages of the invention will be apparent from the following complete specification and the drawings wherein:
FIG. 1 is a cross-section of a starting substrate in accordance with the invention;
FIG. 2 is a cross-section of the substrate after heat treating;
FIG. 3 is a cross-section of the substrate with the semiconductor layer thereon;
FIG. 4 is a cross-section of the substrate with semiconductor devices diffused and isolated in the semiconductor layer;
'FIG. 5 is a standard insulated gate field effect transistor; and
FIG. 6 is an insulated gate field effect transistor from a silicon-on-insulator substrate.
Referring now to FIG. 1, there is depicted generally schematically a spinel substrate 10. This substrate 10 is a (111) slice from a boule of monocrystalline MgO-Al O grown by the Czochralski technique. This technique has been found to produce crystals which are essentially perfect. The substrate 10 may be obtained from the 'boule by any appropriate technique as, for example, sawing. 'Ihe slice is then polished to remove any marks resulting from the slicing operation. The substrate 10 therefore has surfaces which, when tested by electron diffraction techniques, are found to be essentially amorphous. The surface upon which the monocrystalline semiconductor is to be deposited must be converted to a proper crystal structure before such deposition and surface annealing or chemical etch have been previously suggested as suitable for this purpose.
However, in accordance with the invention, the substrate 10 may be placed in a suitable reactor, heat treated at a temperature between 1040 C. and 1145 C. and in a reducing hydrogen atmosphere to recrystallize the amorphous surface region and preferentially remove MgO in the surface layer 12 (FIG. 2) to produce monocrystalline MgO-xAl O wherein x, is between 1.05 and 1.1. The temperature of theheat treatment must. be controlled to assure conversion of theentire surface of the substrate 10 to the desired composition without producing deleterious defects such as cracks, twins and dislocations. These defects are found tobe created to an unacceptable level when the substrate is heated over 1145" C. At a preferred temperature-of approximately 1116 C., total conversion of the surface has been found to take place when the substrate has-been heated for a period of two hours. The heat treatment has been found to yield good results at even lower temperatures, but at approximately 1040 C., the time of treatment exceeds four hours and at 900 C., the time of treatment becomes impractical.
The substrate 10 with layer ,11 thereon is a monocrystalline semiconductor layer 13 preferably of silicon (FIG. 3). The layer 13 can be conveniently epitaxially produced as a further step in the same reactor as the heat treatment by changing the hydrogen atmosphere to a mixture of 0.3% silane in hydrogen with a phosphine dopant. The layer 13 could be produced by any appropriate epitaxial technique with or without dopant material added; From the foregoing, thereis thus provided a semiconductor-on-insulator structure suitable for the manufacture of semiconductor devices and integrated'circuits.
As depicted in FIG. 4, an array of semiconductor dioxides 15 may be produced in the epitaxial layer 13 by suitable masking and diifusion techniques as are wellknown. Etching of openings 14 through the epitaxial layer provides electric isolation between diodes.
Results of the process in accordance with the invention are given in the following examples:
Example IA slice .020 inch thick was cut from a 1% inch diameter boule of Czochralski-grown spinel crystal and polished. The crystal orientation of the slice was approximately 111) and its composition very nearly Electron diffraction by reflected high energy electrons revealed that the surface layers were essentially amorphous, due to the slicing and polishing processes. The slice was heated in hydrogen gas along with a high resistivity bulk silicon control slice on a silicon carbide coated susceptor for two hours at a temperature of 1116 C., after which a two micron silicon layer was epitaxially deposited on both samples from a .3% silane-in-hydrogen mixture at a deposition temperature of approximately 1080 C. A phosphine dopant was added to the deposition gas stream so that the silicon layer on silicon was ndoped to .15 ohm-cm. After deposition, the silicon-onspinel was again subjected to reflected high energy electron difr'raction and to X-ray measurements. The results of electron diffraction showed excellent single crystal silicon films, with no twins and a good Kikuchi diagram pattern. The resistivity across the slice was .40i.05 ohmcm. The silicon on spinel can be said to have a merit factor of as defined by Mercier in the Journal of the Electrochemical Society 117, No. 5, p. 666 (1970). The surface composition lay in the range where x was between 1.05 and 1.1.
Example II-Another MgO-Al O spinel slice Was treated as in Example I, except that the time of heat treatment was only /zhour. The electron diffraction results were the same, i.e., high quality silicon. However, only the edges showed substantial M-gO removal to produce at between 1.05 and 1.1. The average resistivity was now 1.30 ohm-cm, or a merit factor of 11.7%. Thus, although the crystalline quality was acceptable at /2 hour treatment, the composition was not.
Example IIIAnother slice was treated as in Example I, except that the time of treatment at 1116 C. was only minutes. This time the resistivity was uniform within i% over the entire slice, but its magnitude was 1.03 ohm-cm., which corresponds to a 16% merit figure. Thus, 10 minutes is too short a time for the heat treatment to achieve the crystallographic perfection of the slice in Example I.
Example IVAnother slice was treated as in Example I, except that the temperature and time of heat treatment were 1200 C. and one hour respectively. The deposited silicon had a merit factor of 28% but now showed a series of steps that would make the slice unacceptable for defect content. The defect stemmed from cracks in the silicon. Thus, a temperature of heat treatment of 1200 C. is too hot for maintaining surface quality at an acceptable level.
Example VAnother slice was treated as in Example 1, except that the temperature and time of heat treatment were 1145 C. and two hours, respectively. The deposited silicon had a merit factor of 37.6% but also showed a series of steps that would generally make the slice unacceptable for defect content. Thus, a temperature of 1145 C. is too high for maintaining surface quality with great consistency.
Example VIAnother slice was treated as in Example I, except that the temperature and time of heat treatment were 1100 C. and two hours, respectively. The deposited silicon had a merit factor of 38.1% and was free of the steps resulting in Examples IV and V. Thus, heat trelatment at 1100 C. for two hours gives acceptable resu ts.
FIGS. 5 and 6 illustrate insulated gate field eflect transistors on a standard silicon substrate and on a spinel substrate made in accordance with the invention. The standard device 20 includes a gate electrode 21 on dielectrio 22 overlying a channel 23 defined between source and drain diffusion 24, 25. Electrodes 26 and 27 make ohmic contact with the ditfusions and overlie the insulating layer 28. The inherent capacitanees in the device of this type are the lead capacitance (C between electrodes and substrate, junction capacitance (C between diffusions and substrate, and the Miller capacitance (C between gate electrode 21 and the channel 23. The insulated gate field eifect transistor 30 includes a gate electrode 31 on dielectric layer 32 overlying a channel 33 defined by a diffusion 34. The source 35 and drain 36 are of the epitaxial silicon from the foregoing process. Electrodes 37 and 38 make electrical contact with regions 35 and 36 and lie directly on the spinel substrate. With the latter construction, the lead capacitance (C becomes approximately 0 and the junction capacitance (C and Miller capacitance (C greatly reduced. A comparison of electrical characteristics is as follows:
Mobility 280 cmfl/v. see
Field effect mobility cmJ/v. sec 50-12% 1:11?{.)/v. sec. (35-70% Threshold voltage 12-14 v 1012 v. Leakage 10- A. at 10 v- =10 A. at 10 v. Capacitance 5 pi .3 pi.
Although the invention has been described and illustrated in accordance with the preferred embodiment thereof, it will be apparent to one skilled in the art that certain modifications can be made therein without departing from the spirit and scope of the invention.
What is claimed is new and desired to be secured by Letters Patent of the United States:
1. A method of producing monocrystalline semiconductor-on-insulator comprising:
(a) heat treating a substrate of MgO-Al o at 1045- 1145 C. for a time sufficient to modify the surface composition of the substrate to MgO-xAl O where x is between 1.05 and 1.1; and
(b) epitaxially depositing a thin monocrystalline layer of silicon on the modified surface.
2. A method as recited in claim 1 wherein said heating is at a temperature of 1116 C. for approximately two hours.
3. A method as recited in claim 1 wherein said heating is in a hydrogen atmosphere.
Wang, C. C. Growth and Characterization of Spinel Smgle Crystals for Substrate Use in Integrated Electroni1c;,69In J. Applied Phys. 40(9), pp. 3433-3444, August Colin, F. Phases Obtained During the Reduction of Some n-Al O -MO Oxides, In Chem. Abstracts, 70-: 109538 c (1969).
CAMERON K. WEIFFENBACH, Primary Examiner US. Cl. X.R. 117-201; l48175; 317-234 R
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US8620570A | 1970-11-02 | 1970-11-02 |
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JP (1) | JPS557017B1 (en) |
CA (1) | CA957250A (en) |
DE (1) | DE2153862B2 (en) |
FR (1) | FR2113447A5 (en) |
GB (1) | GB1368315A (en) |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4016016A (en) * | 1975-05-22 | 1977-04-05 | Rca Corporation | Method of simultaneously forming a polycrystalline silicon gate and a single crystal extension of said gate in silicon on sapphire MOS devices |
US4147584A (en) * | 1977-12-27 | 1979-04-03 | Burroughs Corporation | Method for providing low cost wafers for use as substrates for integrated circuits |
US4177321A (en) * | 1972-07-25 | 1979-12-04 | Semiconductor Research Foundation | Single crystal of semiconductive material on crystal of insulating material |
US4330932A (en) * | 1978-07-20 | 1982-05-25 | The United States Of America As Represented By The Secretary Of The Navy | Process for preparing isolated junctions in thin-film semiconductors utilizing shadow masked deposition to form graded-side mesas |
US4447497A (en) * | 1982-05-03 | 1984-05-08 | Rockwell International Corporation | CVD Process for producing monocrystalline silicon-on-cubic zirconia and article produced thereby |
US20040089220A1 (en) * | 2001-05-22 | 2004-05-13 | Saint-Gobain Ceramics & Plastics, Inc. | Materials for use in optical and optoelectronic applications |
US6844084B2 (en) | 2002-04-03 | 2005-01-18 | Saint-Gobain Ceramics & Plastics, Inc. | Spinel substrate and heteroepitaxial growth of III-V materials thereon |
US20050061230A1 (en) * | 2003-09-23 | 2005-03-24 | Saint-Gobain Ceramics & Plastics, Inc. | Spinel articles and methods for forming same |
US20050061229A1 (en) * | 2003-09-23 | 2005-03-24 | Saint-Gobain Ceramics & Plastics, Inc. | Optical spinel articles and methods for forming same |
US20050061231A1 (en) * | 2003-09-23 | 2005-03-24 | Saint-Gobain Ceramics & Plastics, Inc. | Spinel boules, wafers, and methods for fabricating same |
US7919815B1 (en) | 2005-02-24 | 2011-04-05 | Saint-Gobain Ceramics & Plastics, Inc. | Spinel wafers and methods of preparation |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT1128752B (en) * | 1980-01-18 | 1986-06-04 | Olivetti & Co Spa | POCKET ELECTRONIC CALCULATOR |
JPS5879358U (en) * | 1981-11-26 | 1983-05-28 | シャープ株式会社 | Small electronic device with printer |
US4477308A (en) * | 1982-09-30 | 1984-10-16 | At&T Bell Laboratories | Heteroepitaxy of multiconstituent material by means of a _template layer |
JPS61120548U (en) * | 1985-01-18 | 1986-07-30 |
-
1970
- 1970-11-02 US US00086205A patent/US3796597A/en not_active Expired - Lifetime
-
1971
- 1971-10-08 CA CA124,776A patent/CA957250A/en not_active Expired
- 1971-10-14 GB GB4791271A patent/GB1368315A/en not_active Expired
- 1971-10-28 DE DE2153862A patent/DE2153862B2/en active Granted
- 1971-11-01 JP JP8708071A patent/JPS557017B1/ja active Pending
- 1971-11-02 FR FR7139182A patent/FR2113447A5/fr not_active Expired
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4177321A (en) * | 1972-07-25 | 1979-12-04 | Semiconductor Research Foundation | Single crystal of semiconductive material on crystal of insulating material |
US4016016A (en) * | 1975-05-22 | 1977-04-05 | Rca Corporation | Method of simultaneously forming a polycrystalline silicon gate and a single crystal extension of said gate in silicon on sapphire MOS devices |
US4147584A (en) * | 1977-12-27 | 1979-04-03 | Burroughs Corporation | Method for providing low cost wafers for use as substrates for integrated circuits |
US4330932A (en) * | 1978-07-20 | 1982-05-25 | The United States Of America As Represented By The Secretary Of The Navy | Process for preparing isolated junctions in thin-film semiconductors utilizing shadow masked deposition to form graded-side mesas |
US4447497A (en) * | 1982-05-03 | 1984-05-08 | Rockwell International Corporation | CVD Process for producing monocrystalline silicon-on-cubic zirconia and article produced thereby |
US6839362B2 (en) | 2001-05-22 | 2005-01-04 | Saint-Gobain Ceramics & Plastics, Inc. | Cobalt-doped saturable absorber Q-switches and laser systems |
US20040089220A1 (en) * | 2001-05-22 | 2004-05-13 | Saint-Gobain Ceramics & Plastics, Inc. | Materials for use in optical and optoelectronic applications |
US6844084B2 (en) | 2002-04-03 | 2005-01-18 | Saint-Gobain Ceramics & Plastics, Inc. | Spinel substrate and heteroepitaxial growth of III-V materials thereon |
US20050061230A1 (en) * | 2003-09-23 | 2005-03-24 | Saint-Gobain Ceramics & Plastics, Inc. | Spinel articles and methods for forming same |
US20050061229A1 (en) * | 2003-09-23 | 2005-03-24 | Saint-Gobain Ceramics & Plastics, Inc. | Optical spinel articles and methods for forming same |
US20050064246A1 (en) * | 2003-09-23 | 2005-03-24 | Saint-Gobain Ceramics & Plastics, Inc. | Spinel articles and methods for forming same |
US20050061231A1 (en) * | 2003-09-23 | 2005-03-24 | Saint-Gobain Ceramics & Plastics, Inc. | Spinel boules, wafers, and methods for fabricating same |
US7045223B2 (en) | 2003-09-23 | 2006-05-16 | Saint-Gobain Ceramics & Plastics, Inc. | Spinel articles and methods for forming same |
US7326477B2 (en) | 2003-09-23 | 2008-02-05 | Saint-Gobain Ceramics & Plastics, Inc. | Spinel boules, wafers, and methods for fabricating same |
US7919815B1 (en) | 2005-02-24 | 2011-04-05 | Saint-Gobain Ceramics & Plastics, Inc. | Spinel wafers and methods of preparation |
Also Published As
Publication number | Publication date |
---|---|
FR2113447A5 (en) | 1972-06-23 |
DE2153862A1 (en) | 1972-05-10 |
GB1368315A (en) | 1974-09-25 |
CA957250A (en) | 1974-11-05 |
JPS557017B1 (en) | 1980-02-21 |
DE2153862C3 (en) | 1980-10-23 |
DE2153862B2 (en) | 1980-03-06 |
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