US3667001A

US3667001A - Selection circuit

Info

Publication number: US3667001A
Authority: US
Inventors: Stephane Marcel Clement Simon; Henri Albert Juli Verhille
Original assignee: International Standard Electric Corp
Current assignee: Alcatel Lucent NV
Priority date: 1969-12-31
Filing date: 1970-12-10
Publication date: 1972-05-30
Anticipated expiration: 1989-05-30
Also published as: BE760950R; ES386895A1; GB1279910A; FR2074395A5; CH534991A; NL6919630A; AU2286470A

Abstract

Selective transfer circuit using transistors and diodes. A time variable gating signal is applied to a coincidence gating chain to trigger a selected transistor into conduction thereby activating an output device individual to the activated transistor. Isolating diodes are used to prevent cross activation of transistors.

Description

United States Patent 6 340/16 6 R; 307/38, 39, 142; 179/186 E, 186 F Simon et al. 1 May 30, 1972 SELECTIONCIRCUIT v R f r nces Cited [72] Inventors: 'Stephane Marcel Clement Simon, UNITEDSTATE'S PATENTS Bl'ussds; Henri M5011 J 2,869,110 1/1959 Wagner..... ..317/ 136 8 3,469,151 9/1969 I Newland.... 17/136 [73] A i nee; I t ti l st d d m m c 2,867,754 1/1959 OBleness ..317/ 141 S tion o Primary Examiner-J. D. Miller [22] Filed Dec. 1970 Assistant Examiner-Harry E. Moose,Jr. v [21] Appl. No.: 96,754 Attorney-C. Cornell Remsen, Jr., Walter J. Baum, Paul W. Hemminger, Charles L. Johnson, Jr., James B. Raden, Delbert [30] Foreign Application Priority Data Warner and w Chaban Dec. 31, 1969 Netherlands ..6919630 [57] ABSTRACT s2 us.C1......,...... ....-...517/137,305/58317/161 s, cti e transfer ci cuit using transistors and diodes. A time 317] 1 36 variable gating signal is applied to a coincidence gating chain [51 Int. CIT. ..ll0lh 47/22 88 a selected u'ansistol' into conductib" thereby activat- [58] Field ofSearch ..317/l36,'137, 141 S; ing an'output device individual to the activated transistor.

Isolating diodes are used to prevent cross activation of transistors. Y

15 Claims, 2 Drawing (P. a e 1.91 59 9 sELEcnoN cmcurr The present invention relates to a selection circuit including a plurality of selection indicating devices, preference means to selectively establish a preference order of operation of said devices and operating means to effectively operate the first device of said established order, said preference means being constituted by a closed loop of series connected elements which are each coupled to a distinct one of said devices and by means to selectively connect a bias source to a junction point of said series connected elements.

Such a selection circuit is already known from Belgian Pat. No. 647 018 (A. Henquet et al. 53l--l In this known selection circuit said devices are constituted by relays each with an operate winding and with a hold winding. This hold winding is connected to a distinct one of said elements which are each constituted by a changeover contact of the as sociated relay and more particularly to-the make contact of this change-over contact. Due to the fact that the above devices are constituted by relays which operate relatively slowly and also due to their contacts operating relatively slowly a relay is only effectively operated, i.e., maintained in operative condition through its hold winding, after a con siderable time has elapsed. Subsidiarily, no means are provided to prevent the temporary operation of a relay via its operate winding since said preference means only control the holding of the relays and not the initial operation thereof.

It is therefore an object of the present invention to provide a selection circuit of the above type, but which does not present the above drawbacks.

The selection circuit according to the present invention is particularly characterized in that said elements are constituted by unidirectional second bias sources the junction points of which are each coupled to a distinct one of said devices.

The present selection circuit is also characterized in that each of said devices is constituted by a coincidence gating circuit with a first and a second input, the first and second inputs of the gating circuits being coupled to said operating means and to said junction points respectively, that said operating means are adapted to apply a time variable operating signal to said first inputs tending to activate said gating circuits and includes at least one capacitor charge circuit at the output of which said time variable operating signal is generated.

In this way the output of a gating circuit the second input of which is given preference is activated when the time variable signal applied to its first input reaches a predetermined threshold value.

It should be noted that Belgian Pat. No. 579 685 (F. Clemens et a]. 2-1) already discloses the use of a time variable signal obtained with the help of a capacitor charging circuit but this signal is used as an inhibiting signal and not as a gating signal. Moreover, this circuit is a common one which is switched to inhibit some devices so that it is not effective if none of the remaining devices is driven.

in accordance with a preferred embodiment of the invention, the present selection circuit includes a plurality of capacitor charge circuits which are each connected to the base of a respective transistor, the emitters of these transistors being connected to distinct one of the junction points of a number of diode rectifiers which are connected in a closed loop and a ring counter being adapted to cyclically apply a bias potential to these junction points. The collector of each transistor is connected to the winding of a relay and to the bases of each of the other transistors via another diode rectifier so that an operated transistor prevents the operation of all the other ones.

According to a further aspect of the invention the present selection circuit which includes a plurality of selection indicating devices and operating means to effectively operate a single one of said devices, is characterized in that each of said devices is constituted by a coincidence gating circuit with a first input and a second input, the first inputs being connected to a common bias source and the second inputs being each connected to a said operating means adapted to apply to this input a time variable signal tending to activate the corresponding gating circuit, and that the output of each one of said gating circuits is connected to the second input of each of the other gating circuits via a diode rectifier so as to prevent said other gating circuits from becoming activated when said one gating circuit is activated.

The above mentioned and other objects and features of the invention will become more apparent and the invention itself will be best understood by referring to the following description of an embodiment taken in conjunction with the accompanying drawings in which:

FIG. 1 is a schematic view of a part of an automatic telecommunication switching system including'selection circuits LASMl 1 and LASM12 according to the invention;

FIG. 2 shows the selection circuit LASMll in detail.

In the copending Dutch patent application dated Dec. 12, 1969, entitled "Automatic telecommunication switching system"(H. Verhille-QKonkers 8-1) an automatic telecommunication system including eight identical switching network parts P1 to P8 is described.

Principally referring to FIG. 1, the switching network part Pl shown therein includes six crossbar switches CS1 to CS6 each with seven vertical operate bars V11 V17 to V61 V67 respectively and with 28 horizontal select bars H11 H128 to H61 H628. The crospoints of the 22 X 6 rows which are each controlled by a respective one of the 22 X 6 horizontal select bars Hll-Hl22 of the crossbar switches CS1 to CS6 are multiplied per row and give access to the incoming junctions U1 1-1.1122 to 1.161-1J622 respectively. The crosspoints of the 6 X 6 remaining rows which are each controlled by a respective one of the 6 X 6 horizontal select bars 11123-11128 of these crossbar switches CS1 to CS8 are not multipled per row, but the homologous ones of these crosspoints are multipled. Each group of six thus multipled homologous crosspoints has access to a same register among 42 registers RE] to R1542. For instance the first crosspoints of the crossbar switches CS1 to CS6, controlled by the horizontal select bars H123 to H126, are multipled and give access to register RE]. Switching network part Pl further includes six switch control circuits, hereinafter called link access circuits LAC] to LAC6, each associated to a respecfive one of the switches CS1 to CS6.

From the above it follows that all the incoming junctors have access to all the registers RE] to R1542. More particularly these incoming junctors have access to the seven groups of registers RBI-R136, RE37-RE42 each time under the control of a respective one of the seven vertical bars forming part of the switch to which these incoming junctors are connected.

The above switching network part P1 is controlled by two markers M11 and M12 which include each a link access selection matrix LASMl l and LASM12 respectively.

In brief the above circuitry which is described in detail in the above mentioned patent application operates as follows. When one or more of the incoming junctors 1.11 14.1628 calls or call for being connected to one of the registers RBI to R542, this call or these calls is or are transmitted to and registered by a call registering relay Ear (not shown) in the link access circuit LAC1-LAC6 associated to the crossbar switch CS1-CS6 to which the calling incoming junctor is connected. This registration is however only performed on condition that at least one of the vertical operate bars V1 1-V17 to V61-V67 of this switch and at least one of the registers coupled to a crosspoint controlled by this vertical bar is available.

Each of the six link access circuits LACl to LAC6 which has thus registered a call from at least one of the incoming junctors connected to the respective crossbar switch CS 1-CS6 calls for the intervention of one of thetwo markers M11 and M12 by applying a calling battery simultaneously to the link access matrices LASMl l and LASM12 included in these markers. Hereby it should be noted that a link access circuit is only able to apply a calling battery to a link acces matrix when the start relay Str (not shown) included in this circuit is in the released condition, and that a link access matrix is available only when all the relays included in the corresponding marker are also in the released condition. Each available link access matrix then selects one of the six possible calling link access circuits LAC1-LAC6 according to a predetermined priority. For instance, the LASMll included in the marker M11 selects the calling LACl associated to the crossbar switch CS1 by operating relay Llr which is associated to the LACl in the LASMll. Following the operation of the relay Llr the relays Mgr (FIG. 2) and Mlr (not shown) are operated. These relays hereby block the LASMl 1 against calls from one of the other link access circuits LAC2 to LAC6. The marker M11 then selects a calling incoming junctor, e.g., U1 1 connected to a crosspoint of crossbar switch CS1 to which the selected LAC1 is associated and operates the horizontal select bar 1111 controlling this crosspoint. Consequently the above start relay Str is then energized in the LACl to prevent this circuit from making a renewed call although other incoming junctors IJ 12-11122 connected to the CS1 may be in the calling condition. The operation of relay Str is followed by the release of relay Llr due to which the relays Mgr and Mlr now block the LASMll against calls from all the link access circuits LAC1 to LAC6. A connection is then established between the selected calling incoming junctor U11 and a free register, e.g., RE], by the subsequent operation of the horizontal select bar H123 and the vertical bar V11. Afterwards the relays Str, Mgr and Mlr are released in succession, the LASM11 and the marker M11 being again available when relay Mlr is in the released condition.

Principally referring to FIG. 2, the link access selection matrix LASM11 shown therein includes six capacitor charge circuits part of which is located in a respective one of the link access circuits LAC 1-LAC6 and which are each consituted by the series connection of a ground in the LASMl, a parallel circuit R11, C11-R16, C16, a Zener diode Z11-Zl6, a column conductor CWl-CW6, a terminal V1-V6, a resistance R21-R26, a terminal X1-X6 connected to the LAC1-LAC6, a break contact st (LACl) st (LAC6) of the start relay Str included in the LAC 1-LAC6, a make contact ea (LAC1)- ea (LAC6) of the call registering relay Ear included in the LAC l-LAC6, a resistance R31R36 and a battery.

The junction, points I1 to I6 of each parallel circuit R11, C11-R16, C16 and the respective Zener diode Z11-Z16 is connected to the base electrode of a respective PNP transistor T1 T6. The emitter electrodes of these transistors T1-T6 are each connected to a respective one of the junction points J1 to J6 of the six doide rectifiers D11 to D16 which are series connected in a closed loop. A step-by-step switch 8 is adapted to cyclically apply a bias ground to terminals P1 to P6 and hence to the junction points J1 to J6. Obviously any other type of ring counter could be used instead of switch S.

The collector electrodes of the transistors T1 to T6 are connected to the tapping point T of a common potentiometer R4, R via the series connection of a respective conductor C1C6, a respective terminal Y-Y6, and the winding of a respective relay L1r-L6r. The collector electrodes of the transistors T1 to T6 are further each connected to a respective one of the row wires rwl to rw6 of a diode matrix DM via a respective diode rectifier D21 to D26. These row wires rwl to rw6 are themselves each connected to five column wires cwZ-cw6 to cwl-cw 5 each time via an individual diode rectifier. For instan e the row ,W LQ miamlrwfiof he M a e anns sd 19.

the column wires cw2-cw6 and cwl-cwS respectively via diode rectifiers D'l2-D 16 and D 16-D'65 respectively.

The above relays L1r-L6r each have a make contact 111-! 61, which is adapted to connect a ground to a respective one of the terminals Z1-Z6 leading to the row wires rw1-rw6 respectively, the diode rectifiers'D41-D46 being not always necessary.

The above described circuitry is the basic one but additional circuitry may be added to it.

For security reasons, as will be explained later, a ground is connected to theabove junction points J 1-J6 via a common Zener diode Z21 and a respective diode rectifier D31-D36.

The make contacts l11-I16 may be connected to the winding of a control relay Mgr in which case the decoupling rectifiers D41-D46 and D51-D56 must be provided. The make contact mgl of this relay Mgr is used to connect a common ground to the terminals Ul-U6 of the respective column wires cwl-cw6 via a respective break contact 112-162 of the relay L14-L6r and a respective diode rectifier D61-D66. The make contact mgl is shunted by contact ml of the above mentioned relay mlr (not shown).

The matrix DM may also include an inhibiting row conductor rw7 which is connected to each of the terminals V1 to V6 on the column conductors cwl to cw6 via a respective diode rectifier D81-D86' and the terminal P. The latter terminal P is connected to ground via a break contact am of control relay Amr (not shown) and a diode rectifier D7 in series.

Finally the terminal Wl-W6 of each of the row conductors rw1-rw6 of the LASMll may be connected in the LASM12 to the junction point V1-V6 of a column conductor cwl-cw6 and a resistan ce R2L -RZ6 via a decoupling diode rectifier D9l-D96 and a terminal 01-06.

The operation of the above described selection matrix LASMll without considering the inhibiting row conductor rw7 as follows.

It is supposed that at the moment the marker M1 1 becomes available due to its relay mlr being released all the contacts of the LACl-LAC6 and of the marker M11 are in theposition shown, except for the contacts ea (LACl) and ea (LAC6) which are supposed to be in their operated condition due to the corresponding relays Ear (LACl) and Ear (LAC6) being in their operated condition. The operated relays Ear in the LACl and in the LAC6 indicate that one of the incoming junctors connected to the CS1 and to the CS6 respectifely call for a register.

Due to contacts ea (LACl) and ea (LAC6) being closed the capacitors C11 and C16 simultaneously start charging between ground and battery in the following respective circuits:

R11, C11, Z11, cwl, R21, X1, sl(LAC1), ea (LACl) and R31; R16, C16, Z16, ew6, R26, X6, st(LAC6), ea(LAC6) and R36. Consequently the potential at the

base electrodes

11 and 16 of the transistors T1 and T6 gradually decreases towards battery. Since the emitter of transistor T1 is directly connected to the ground provided by the switch S, whereas the emitter of transistor T6 is connected to the same ground via the series connection of five diode rectifiers D1 1 to D15 each producing a voltage drop of v Volts, it is clear that transistor T1 will be rendered conductive before transistor T6. As soon as the transistor T1 is rendered conductive the ground connected to its emitter is applied via its emitter-to-collector junction to conductor 01 and from there on the one hand to the column conductors cw2 (not shown) to cw6 via the common diode rectifier D21, the row wire M1, and the individual diode rectifiers D'l2 to D16 respectively. Due to this none of the capacitors C12 to C16 can be charged to a potential sufficient to render conductive the associated transistor T2-T6. In other words an electronic exclusion of the transistors T2 to T6 is realized. Hereby it should be noted that an electronic exclusion is already known from the above mentioned Belgian Pat. No. 579 685 (F. Clemens et al. 2-1);

on the other hand to the one end of the winding of relay Llr, the other end of this winding being connected to the tapping point T of the potentiometer R4, R5. The transistor T1 and the relay Llr are hence operated in seties.

The energized relay Llr which indicates that the LACl is selected closes its contact 111 due towhich a further ground is connected to the row wire rw1 via diode rectifier D41 and hence to the column conductors cw2 (not shown) to cw6 via the diode rectifiers D'l2 to D16 respectively. The transistors T2 to T6 and the associated relays L2r to L6r are hence closure of contact 111 an electromechanical exclusion of the transistors T2-T6 is realized. By preventing the transistors T2 to T6 from being operated it is clear that the LASMll is blocked against calls from the link access circuits LAC2-LAC6, this blocking being under the control of T1 and Llr.

In the above example the column conductors cw2 to (M6 are each connected to ground via three diode rectifiers subsequent to the operation of transistor T1, i.e., the emitter-tocollector junction of this transistor, D21 and D12'-D16 since the emitter of this transistor T1 is directly grounded due to the switch S being in the first position P1 shown. When the switch S is, however, for instance in the second position P2, it is clear that this ground will be applied to the emitter of transistor T1 via the five diode rectifiers D12 to D16 so that the ground potential is then applied to the column conductors cw2-cw6 via eight diode rectifiers, i.e., D12 to D16, T1, D21 and D'12-D'16 at the moment the transistor T1 is rendered conductive. Since each diode rectifier producesa voltage drop of v Volts, e.g., 0.3 Volts, it is clear that even after the above electronic exclusion has been realized the capacitors C12 to C26 are able to charge between 8 v Volts and ground. This is obviously undesirable. Due to the closure of contact 11 1 such charging of the capacitors C12 to C16 is, however, prevented or these capacitors are substantially completely discharged since this contact applies a ground to each of the column conductors cwl-cw6 via two series connected diode rectifiers D41 and D12-D'16 only. This is the reason why the contacts 11 1 to 161 have been provided.

The energized relay Llralso opens its break contact 112 due to which terminal U1 is disconnected from contact mgl.

By the closure of contact 111 relay Mgr is energized via diode rectifier D51 and its first winding. It is locked in a not shown circuit including its second winding. By the subsequent closure of contact mgl a locking ground is applied to the terminals U2 (not shown) to U6 via this common contact mgl, a respective contact 122 (not shown) -162 and a respective diode rectifier D61-D62 so that the operation of the transistors T2 (not shown) to T6 is inhibited independently from the condition of transistor T1 and hence of relay Llr. This means that even when transistor T1 is blocked and relay Llr is released the transistors T2 to T6 cannot be operated as long as relay Mgr is operated, and that the LASMll is then hence blocked against calls from the link access circuits LACZ to LAC6. The operation of relay Mgr is followed by that of relay Mlr (not shown) which closes its make contact mlshunting contact mgl and thus also blocking the LASMll against calls from the link access circuits LAC2 to LAC6 in a manner independent from relay Llr.

As already described above the marker M11 of which the LASMll forms part then selects a calling incoming junctor connected to a crosspointof crossbar switch CS1 and operates the horizontal bar controlling this crosspoint. Consequently the start relay Str of the LAC] is then energized. By the open ing of break contact st (LACl) transistor T1 is cut-off and relay Llr is released so that the above locking ground is now also applied to the terminal U1 via contacts mg] and ml in parallel, contact 112 and diode rectifier D61. The LASMll is hence blocked against calls from all the link access circuits LACl to LAC6.

A connection is then established between the selected incoming junctor and a free register and afterwards the relays Str, Mgr and Mlr are released in succession, the marker M11 and hence the LASMl being again available when the relay Mlr is in the released condition. It should be noted that alter the release of relay Mgr the switch S is stepped to its next positron.

It should be noted that as soon as the row conductor rwl has been grounded due to transistor T1 having been operated this ground is also applied to the line access selection matrix' LASM12 of the marker M12. Indeed, the terminal Q1 of this row conductor rwl is connected to the temiinal VI of the conductor c1 of the LASM12 so that the transistor T1 included therein is also prevented from being operated. This is done in order to prevent that both selection circuits LASMll and LASM12 would select the same link access circuit LAC].

If in the above described example the switch S is positioned on any of the tenninals P2 to P6 it is clear that the transistor T6 is made conductive before transistor T1 since the emitter of the transistor T6 is then connected to ground via four, three, two, one or zero rectifiers in series, while the emitter of transistor T1 is connected to this ground via five rectifiers in to T5 via eight diode rectifiers in series, i.e., the five diodes D11 to D15, the emitter-to-collector junction of transistor T6 and the diodes D26 and D61-D65 so that the negative potential applied to these bases is substantially equal to V=8v Volts, v being the potential drop produced across each diode. If before the relay L6r has closed its contact I61 contact ea (LACl) is now closed, the capacitor C11 starts charging between ground and V. Without the Zener diode Z1 1, it may hence happen that also the transistor T1 is rendered conductive since the emitter thereof is directly connected to ground. By connecting a Zener diode Z11 in the last mentioned charge circuit in such a manner that it presents a high resistance and by choosing the Zener voltage higher than V the above conflicting situation cannot occur. 7

As already mentioned above, the circuit constituted by the diodes Z21 and D31 to D36 has been chosen for security reasons. It may indeed happen that for one or the other reason the switch S or the equivalent counter does not connect a ground to one of the terminals P1 to P6. It is clear that in this case and without precautions the circuit cannot operate. However, by providing a Zener diode Z21 and the diodes D31 to D36 a voltage of about 3 Volts then appears at the junction points J1 to .16 when choosing a Zener diode Z21 with a Zener voltage of about 2.7 Volts. Thus the operation of the LASMll is enabled. The above security circuit normally does not intervene in the operation of the selection circuit since the diodes D31 to D36 are normally blocked, but in case the security circuit becomes operative the above priority established by the diodes D11 to D16 has no effect.

It should be noted that each of the diode rectifiers D11 to D16 may be replaced by the series connection of a bias source and a diode rectifier, thus forming a unidirectional bias source. Also each of the transistors T1 to T6 could be replaced by a coincidence gating circuit.

In the above described example the selection matrix LASMll is normally available since the relays Mgr and Mlr are normally in the released condition. In this way, when one of the link access circuits calls for a marker the LASMll is able to operate immediately.

In case the above selection matrix is for instance used to select a vertical bar among a plurality of such bars and that the availability indicating batteries of these bars is applied to the selection matrix by contacts corresponding to eaof a same relay, this selection matrix oftenly selects the same vertical bars since the last mentioned contacts are substantially never closed simultaneously although they belong to a same relay. In this case it is therefore preferable to normally block the selection matrix and to unblock it only after all the above mentioned contacts have been closed. Such a circuit for normally blocking the selection matrix is constituted by the above described additional row wire rw7 since contact am normally applies a locking ground to this row wire and from there to all the column wires cwl to cw7. In order to unblock the matrix LASMll it is sufficient to operate relay Amr (not shown) which then opens its contact am.

It should be noted that when contact am is provided instead of the contacts 11 1-161, 112-162 mgl the diodes D2l-D26 may be replaced by a short-circuit.

In the above described selection circuit the operated relay Llr remains under the control of the start battery since when the latter battery is removed transistor T1 is cut-off and relay Llr is released. One may, however, also lock the relay Llr over its own contact. For instance one make contact each of the contacts 11 1-161 to the lower ends of the windings of the respective relays Llr-L64 in which case the diodes D2l-D26 are obviously not required. Or when one provides contact am the latter may be a change-over contact the make contact of which is connected to the lower ends of the windings of the relays Llr-L6r via a make contact of these relays.

While the principles of the invention have been described above in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the invention.

What is claimed is:

1. Selection circuit including a plurality of selection indicating devices, preference means to selectively establish a preference order of operation of said devices and operating means to effectively operate the first device of said established .order, said preference means comprising a closed loop of series connected elements each coupled to a distinct one of said devices and means to selectively connect a bias source to a junction point of said series connected elements, wherein said elements comprise unidirectional second bias sources, the junction points of which are each coupled to a distinct one of said devices, each of said unidirectional second bias sources comprising a conductive rectifier, and each of said devices comprising a coincidence gating circuit with a first and a second input, the first and second inputs of the gating circuits being coupled to respective operating means and including means for generating a time variable operating signal, operating means to apply said signal to said first inputs .for activating said gating circuits includes at least one capacitor charge circuit at the output of which said time variable operating signal is generated, and a plurality of said capacitor charge circuits, each coupled to the first input of a distinct one of said gating circuits, and wherein each of said capacitor charge circuits comprises a series circuit branched between a first and a second DC source and including a parallel circuit formed by a capacitor, a first resistance and a second resistance, the output of said parallel circuit being connected to a said first input of a gating circuit.

2. Selector circuit according to claim 1, wherein said bias source is constituted by said first DC source; and wherein said means to selectively connect said bias source comprise a ring counter which is adapted to cyclically connect said bias source to said junction points.

3. Selection circuit according to claim 2, further including a plurality of inhibiting means, each individually associated with a distinct one of said devices and each of which when in the operative condition prevents the effective operation of the associated device.

4. Selection circuit according to claim 3, wherein each of said capacitor charge circuits includes a make contact constituting said inhibiting means; and wherein each of said gating circuits comprises an electrical conduction device, with at least a first input electrode, a second input electrode, and an output electrode.

' 5. Selection circuit according to claim 4, further including lockout means to prevent the operation of more than one of said devices at a time.

6. Selection circuit according to claim 5, wherein the first of said lock-out means comprise a plurality of rectifiers branched between the output of each one of said gating circuits.

7. Selection circuit according to claim 6, wherein a said gating circuit is activated, a lock-out DC source is coupled to the output thereof; and said lock-out DC source comprises said first DC source.

8. Selection circuit according to claim 7, wherein the second of said lock-out means comprise a plurality of make contacts of a relay, each such contact connected to the output of a respective gating circuit, each make contact capable of connecting said lock-out DC source to the first input of each of said remaining gating circuits via a said second rectifier.

9. Selection circuit according to claim 8, wherein the output of each one of said gating circuits is decoupled from said make contact of the associated relay by a rectifier.

l0. Selection circuit according to claim 9, wherein the rectifiers coupled to the first input of a same gating circuit are connected to this input via a common Zener diode.

l1. Selection circuit according to claim 10, wherein each said make contact of a relay is connected, on the hand, to the winding of a second relay via an individual rectifier and, on the other hand, to a corresponding said rectifier via a rectifier and that said lock-out DC source is coupled to the first input of each said gating circuit via the series connection of a common make contact of said second relay, an individual break contact of said first relay and an individual rectifier.

l2. Selection circuit according to claim 11, wherein each said last mentioned rectifier is connected to the first input of a said gating circuit via a said common Zener diode.

13. Selection circuit according to claim 12, wherein said make contact of said relay is able to connect said lock-out DC source to the output of the gating circuit to which this relay is connected.

l4. Selection circuit according to claim 13, wherein a third bias source is connected to each of said junction points via a common second Zener diode and an individual rectifier.

15. A selection circuit including a plurality of selection indicating gating circuits, preference means to selectively establish a preference order of operation of said gating circuits and operating means to effectively operate the first gating circuit of said established order, said preference means comprising a closed loop of series connected elements each coupled to a distinct one of said gating circuit and means to selectively connect a bias source to a junction point of said series connected elements, wherein said elements comprise unidirectional second bias sources, the junction points of which are each coupled to a distinct one of said gating circuits, means for generating'a time variable operating signal for activating said gating circuits, said generating means include at least one capacitor charge circuit at the output of which said time variable operating signal is generated, said capacitor charge circuits comprising a series circuit branched between a first and a second DC source and including a parallel circuit formed by a capacitor, a first resistance and a second resistanoe, the output of said parallel circuit being connected to an input of a gating circuit.

Claims

1. Selection circuit including a plurality of selection indicating devices, preference means to selectively establish a preference order of operation of said devices and operating means to effectively operate the first device of said established order, said preference means comprising a closed loop of series connected elements each coupled to a distinct one of said devices and means to selectively connect a bias source to a junction point of said series connected elements, wherein said elements comprise unidirectional second bias sources, the junction points of which are each coupled to a distinct one of said devices, each of said unidirectional second bias sources comprising a conductive rectifier, and each of said devices comprising a coincidence gating circuit with a first and a second input, the first and second inputs of the gating circuits being coupled to respective operating means and including means for generating a time variable operating signal, operating means to apply said signal to said first inputs for activating said gating circuits includes at least one capacitor charge circuit at the output of which said time variable operating signal is generated, and a plurality of said capacitor charge circuits, each coupled to the first input of a distinct one of said gating circuits, and wherein each of said capacitor charge circuits comprises a series circuit branched between a first and a second DC source and including a parallel circuit formed by a capacitor, a first resistance and a second resistance, the output of said parallel circuit being connected to a said first input of a gating circuit.

5. Selection circuit according to claim 4, further including lock-out means to prevent the operation of more than one of said Devices at a time.

10. Selection circuit according to claim 9, wherein the rectifiers coupled to the first input of a same gating circuit are connected to this input via a common Zener diode.

11. Selection circuit according to claim 10, wherein each said make contact of a relay is connected, on the hand, to the winding of a second relay via an individual rectifier and, on the other hand, to a corresponding said rectifier via a rectifier and that said lock-out DC source is coupled to the first input of each said gating circuit via the series connection of a common make contact of said second relay, an individual break contact of said first relay and an individual rectifier.

12. Selection circuit according to claim 11, wherein each said last mentioned rectifier is connected to the first input of a said gating circuit via a said common Zener diode.

14. Selection circuit according to claim 13, wherein a third bias source is connected to each of said junction points via a common second Zener diode and an individual rectifier.

15. A selection circuit including a plurality of selection indicating gating circuits, preference means to selectively establish a preference order of operation of said gating circuits and operating means to effectively operate the first gating circuit of said established order, said preference means comprising a closed loop of series connected elements each coupled to a distinct one of said gating circuit and means to selectively connect a bias source to a junction point of said series connected elements, wherein said elements comprise unidirectional second bias sources, the junction points of which are each coupled to a distinct one of said gating circuits, means for generating a time variable operating signal for activating said gating circuits, said generating means include at least one capacitor charge circuit at the output of which said time variable operating signal is generated, said capacitor charge circuits comprising a series circuit branched between a first and a second DC source and including a parallel circuit formed by a capacitor, a first resistance and a second resistance, the output of said parallel circuit being connected to an input of a gating circuit.