US3654612A

US3654612A - Display system using a cathode-ray tube

Info

Publication number: US3654612A
Application number: US22639A
Authority: US
Inventors: Katsuhiko Ohara; Kazuchiyo Matsuzawa
Original assignee: Takachiho Koheki KK
Current assignee: Takachiho Koheki KK; Unisys Corp
Priority date: 1969-03-29
Filing date: 1970-03-25
Publication date: 1972-04-04
Anticipated expiration: 1989-04-04
Also published as: JPS4826409B1

Abstract

A display system for displaying information patterns on the screen of a cathode-ray tube obtained in a logical operation device, such as a calculator, where counters and registers are commonly used for both the logical operation of the logical operation device and the display operation of the system. The average DC values of the inputs to the vertical signal amplifier and the horizontal signal amplifier for the cathode-ray tube are maintained at stable values at both a period of the logical operation and a period of the display operation in order to eliminate the disturbance and fluctuation of the displayed pattern during the transition - an instant when the operation mode of the system is switched - from the logical operation to the display operation. Slope signals for displaying each digit are generated after a predetermined time from the start of the digit display time for a displayed unit-pattern.

Description

United States Patent Ohara et a1. 1451 Apr. 4, 1972 [54] DISPLAY SYSTEM USING A CATHODE- 3,453,601 7/1969 Bogert et al. .340/1725 RAY TUBE 3,476,973 11/1969 Chesarek et al. ....3l5/l8 3,479,552 11/1969 Tomaszewski et al. ..315/18 [721 1mm: Ka'suhlk" Kmchiy" Matsulawa, 3,479,553 11/1969 Yanishevsky et al. ..3 15/18 Japan 3,483,425 12/1969 Yanishevsky ....315/18 [73] Assignee: Takachlho Koeki Kabushiki Kaisha, Ko- 3,488,551 l/ l 970 Bryden ..3 1 5/1 8 matsubara-machi, Kita-ku, Ohsaka-shi, Ja a Primary ExaminerPaul .1. Henon Assistant Examiner-Jan E. Rhoads [22] Flled: 1970 Attorney-Robert E. Burns and Emmanuel J. Lobato [21] Appl. No.: 22,639

[57] ABSTRACT [30] F reign Application Pri it D t A display system for displaying information patterns on the screen of a cathode-ray tube obtained in a logical operation M31. 29, 1969 Japan device, such as a calculator where counters and registers r commonly used for both the logical operation of the logical [52] US. CL ..340/172.5, 340/324 A, 315/18 Operation device and the display operation of the System The [5 l 1 f Cl "Gosf 5/00 Gosh I 1/ 1 15/20 average DC values of the inputs to the vertical signal amplifier [58] new of Search 340/1725 324 315/ and the horizontal signal amplifier for the cathode-ray tube are maintained at stable values at both a period of the logical operation and a period of the display operation in order to [56] References Cited eliminate the disturbance and fluctuation of the displayed pat- UNITED STATES PATENTS tern during the transition an instant when the operation mode of the system is switched from the logical operation 2,931,022 3/1960 Triest ..340/324 A to the display operation. slope Signals f displaying each digit 31243-725 4/ 1 966 et A are generated after a predetermined time from the start of the 3,320,595 5/1967 Yanlshevsky ..340/172.5 digit display time f a displayed unigpaneml 3,403,286 9/1968 Carlock et a1. ..3l5/18 3,419,750 12/1968 Rothschild et a1 ..315/18 5 Claims, 16 Drawing Figures CONTROL CIRCUIT HIGH VOLTAGE SOURCE BLANK/N6 CIRCUIT PATENTED PR 4 I912 SHEET 3 OF 5 a u a h mimitmwtmifigmm::8:mmm mfim KATSUHIKO OHARA and KAZUCHIYO MATSUZAWA [N VEN'I'URS PATENTEUAPR 4 1972 SHEET UF 5 xfi 50 D E F H. F B

KA'lSUI-IIKO' OHARA and KAZUCHIYO MATSUZAWA IN VENTORS Atty.

PATENTEDAPR 4 1972 SHEET 5 OF 5 F v m 5 in 2 J 9 3: T Em5 $51 52% 1%? 69 N o J $538 1 d\ m v m N 2m w m m v m m im w llnfiliflm v wiring m im :iifiliimi wmrw fi INVENTORS KATSUHIKO OHARA KAZUCHIYO MATSUZAWA DISPLAY SYSTEM USING A CATHODE-RAY TUBE BACKGROUND OF THE INVENTION This invention relates to a display system using a cathoderay tube and more particularly to a display system for displaying on the screen of a cathode-ray tube pattern information, such as numerals, corresponding to input information in a logical operation device, such as a calculator.

DESCRIPTION OF THE PRIOR ART Display systems of this type can display a large amount of information and have a display screen which is within the field of view of the operator. However, the cost of the display system of this type is higher than the price of other display systems using indicator tubes, such as a Nixie tube. Accordingly, display systems of this type are usually employed in more sophisticated calculators, whose high prices may be attributed to the following reasons. In a case where a cathoderay tube is employed to display numerals for a calculator etc., registers and counters used solely for the display operation are provided to eliminate disturbances and fluctuations of patterns displayed on the screen of the cathode-ray tube. Otherwise deflecting circuits for the cathode-ray tube comprise direct-coupling amplifiers. However, these direct-coupling amplifiers are necessarily provided to eliminate drift, with complicated compensation circuitry for eliminating fluctuations by deviation of temperature(i.e., a temperature-compensating network). Accordingly, the deflecting circuits become expensive.

SUMMARY OF THE INVENTION An object of this invention is to provide a display system using cathode-ray tube for a logical operation device capable of reduction to practice by the use of a set of counters and registers commonly used for the logical operation and the display operation in an alternately switched manner.

Another object of this invention is to provide a display system using a cathode-ray tube for logical operation device capable of displaying patterns necessary for the logical operation by the use of non-direct-coupled deflection-amplifiers without fluctuation and disturbance of the displayed pattern.

In the display system of this invention, standard pattern signals, each indicative of a predetermined standard pattern, are successively generated, and necessary'patterns relating to logical operations performed by the use of counters and registers are displayed on the screen of a cathode-ray tube by blanking the respective standard pattern signals so as to obtain the necessary patterns. In accordance with a feature of this invention, the aforementioned counters and registers are commonly employed for the display operation and the above-mentioned logical operation, and the display function of the cathode-ray tube is interrupted during the period of the logical operation. However, the direct-current voltages applied respectively to the deflection amplifiers at the logical operation time are respectively adjusted so as to be equal to the respective average DC value of the voltages applied to the deflection amplifiers at the display time. Moreover, the generating time of each of the standard pattern signals is determined so as to be shorter than a display time for a unit displayed pattern and so as to be slightly delayed from the start of the display time. As a result of the above construction, fluctuations on the displayed pattern are effectively eliminated, and deflecting circuitry can be constructed without use of the aforementioned direct-coupling amplifiers having such defects.

BRIEF DESCRIPTION OF THE DRAWINGS The principle of the invention will be better understood from the following more detailed discussion in conjunction with the accompanying drawings, in which the same or equivalent parts are designated by the same or equivalent numerals, characters, and symbols, and in which:

FIG. 1 is a block diagram illustrating an embodiment of this invention;

FIG. 2 is block diagram illustrating an example of control means for counters in the system of this invention;

FIG. 3A is a diagram explanatory of a standard pattern used in the system of this invention;

FIG. 3B shows patterns indicative of numerals which are displayed in the system of this invention;

FIG. 3C shows time charts explanatory of slope waves used in the system of this invention;

FIG. 4A is a circuit diagram illustrating an example of an adder used in the system of this invention;

FIG. 4B shows time charts explanatory of the logical operation time and the display time in the system of this invention;

FIGS. 5A, 5B, 5C, SD, SE and SF are time charts explanatory of the operations of the system of this invention FIG. 6 shows time charts explanatory of the operations of the system of this invention at the logical operation mode; and

FIGS. 7A and 7B show time charts explanatory of the operations of the system of this invention at an instant when the operation mode of the system is switched from the logical operation to the display operation.

DESCRIPTION OF THE PREFERRED EMBODIMENTS At first, the principle of the system of this invention will be described. With reference to FIG. 1, the operation of the system of this invention is started by controlling a keyboard 5 to instruct a control circuit 1 to control

counters

2, 3 and 4 so as to perform logical operations and display operations. In this case, the counter 2 is a scale-of-four counter, the counter 3 a scale-of-ZO counter, and the counter 4 a scale-of-l6 counter. Input data are applied from the keyboard 5 to a register 9 under control of the

counters

2, 3 and 4 to store the input data in the register 9. If instruction for calculation A X B C) is generated by way of example, values A and B are respectively stored in

registers

7 and 8, while the result C" of this calculation is stored in the register 9. A register 6 is a memory for temporarily storing necessary data. Each of these

registers

6, 7 and 8 has a capacity of 16 bits. After the abovementioned logical operation, the operation condition of this system is changed to display the operation under control of the control circuit 1. Accordingly, one grand cycle of the operation of this invention comprises logical operation time and display time which are indicated by notations t, and 2,, respectively. The

counters

2, 3 and 4 are originally provided for the logical operation in conventional systems. However, these

counters

2, 3 and 4 are used both for the logical operation and the control of display operation in the system of this invention.

In the display time r the contents of the

registers

6, 7, 8 and 9 are displayed on the screen of a cathode-ray tube 27 in four lines. For this display, a vertical slope wave W and a horizontal slope wave W are at first generated, by the use of the output pulses of the counter 3, at a vertical slope generator 11 and a horizontal slope generator 12 respectively as standard pattern signals which are successively generated and each representative of a standard pattern shown in FIG. 3A. The output pulses of the counter 3 are synchronized with successive changes of the counting state of the counter 3. The vertical slope wave W is applied through a buffer amplifier 15 to a V-adder 20 and added to a vertical step wave w of four steps which is generated at a vertical step generator 14 in response to the output pulses of the counter 2. These output pulses of the counter 2 are synchronized with successive changes of the counting states of this counter 2. The vertical step wave W is employed to successively switch lines of the displayed pattern of numerals. On the other hand, the horizontal slope wave W is applied through a buffer amplifier 17 to a H-adder 22 and added to both the vertical slope wave w applied through a buffer amplifier l6 and a horizontal step wave w of 16 steps which is generated at a horizontal step generator 18 in response to the output pulses of the counter 4. These output pulses of the counter 4 are synchronized with successive changes of the counting states of this counter 4. The horizontal step wave w,, is employed to switch digits of the displayed pattern of numerals. The vertical slope wave w, applied to the l-l-adder 22 is employed to incline the displayed patterns of numerals with respect to the vertical direction of the displayed pattern. The output of the V-adder 20 and the output of the I-l-adder 22 are applied to deflection coils of a cathode-ray tube 27 through a vertical signal amplifier 25 and a horizontal signal amplifier 26 respectively to display standard patterns on the screen of the cathode-ray tube 27 without blanking signals.

On the other hand, the contents of the

registers

6, 7, 8 and 9 are successively read out, for one digit of four bits, to a buffer register 10 from the least significant bit positions of each register and applied to a decoder 13, in which each digit read out is decoded. The decoded output of the decoder 13 is applied to a read-only memory 19 storing blanking signals, so that one of the stored blanking signals corresponding to the decoded output of the decoder 13 is applied from the readonly memory 19 to a blanking circuit 23. This blanking circuit 23 controls the cathode-ray tube 27 to blank the unnecessary parts (shown by dotted line in each numeral pattern in FIG. 3B) of the above-mentioned standard pattern so as to obtain a pattern of numeral (shown in FIG. 3B) corresponding to the digits read out from of the

registers

6, 7, 8 or 9.

In the above-mentioned operations, the displayed patterns of numerals are disturbed or fluctuated at the switching instant from the logical operation time 1,, to the display time t due to the time constants of the deflection circuits (25 and 26) and the deflection coil of the cathode-ray tube 27. To eliminate the disturbance and fluctuation of the displayed pattern, a signal DISPLAY (W) shown in FIG. 4B is applied to an inverter 21 to obtain a signal DISPLAY (W6) shown in FIG. 4B. The signal w is applied to both the V-adder 20 and the H- adder 22 to maintain, at respective stable values, the respective direct-current average voltages of the inputs of the horizontal signal amplifier 26 and the vertical signal amplifier 25 at both the logical operation time t and the display time t Moreover, the starts of the slope waves w, and W2 are delayed by four clock pulses from the start of a display time t, for a displayed unit-pattern, so that a digit to be displayed at a just-succeeding digit display time 2,, is read out to the buffer register from one of the

register

6, 7, 8 and 9. Thus the principal feature of this invention is that the signal DISPLAY (W5) and its inverted signal DISPLAY (w are applied to the

adders

20 and 22 so as to maintain, at respectively stable values, the respective average DC value of voltages of the inputs of the horizontal signal amplifier 26 and the vertical signal amplifier 25 at both the logical operation time t and the display time t and that a digit to be displayed at a succeeding digit display time t, is read out to the buffer register 10 at the delayed time t, (e.g., a time of four clock pulses) to eliminate the effect caused by the time constant of the deflection circuit of the cathode-ray tube 27. The operation of this construction will be described in detail below.

With reference to FIG. 2, operations of the

counters

2, 3 and 4 will be described in detail. At the input side of the counter 2 (i.e., a scale-of-4 counter), AND gates G, and G and an OR gate OR, are provided. To the AND gate G,, the signal DISPLAY (W5), clock pulses CP, and the carry outputs of the

counters

3 and 4 are applied from terminals T, and T and counters 3 and 4 respectively. To the AND gate G the signal DISPLAY (W6) and a first counting pulse train P, are applied from terminals T and T.,. The outputs of the AND gates G, and G are applied to the counter 2 through the OR gate OR,. At the input side of the counter 3 (i.e.; a scale-of-20 counter), AND gates G and G, and an OR gate 0R are provided. To the AND gate G the signal DISPLAY (W5) and the clock pulses C? are applied from the terminals T, and T respectively. To the gate 6,, the signal DISPLAY (W5) and a second counting pulse train P are applied from the terminal T and a tenninal T The outputs of the AND gates G and G are applied to the counter 3 through the OR circuit OR,. At the input side of the counter 4 (i.e., a scale-of 16 counter), AND gates G and G and an OR circuit 0R are provided. To the AND gate 6,, the signal DISPLAY (W5), the clock pulses CP and the carry output of the counter 3 are applied from the terminals T, and T and the counter 3 respectively. To the AND gate G the signal DISPLAY (w and a third counting pulse train P are applied from the terminal T, and a terminal T The outputs of the AND gates G and G are applied to the counter 4 through the OR gate OR,,. The above-mentioned AND gates G,, G G 6,, G and G the OR circuits OR,, CR and CR and the terminals T T T T.,, T and T are provided in the control circuit 1 shown in FIG. 1.

Operations of the

counter

2,3 and 4 at the logical operation time t are as follows. At this time, the signal DISPLAY (w are applied to the AND gates G G, and G,,, so that all the AND gates G G, and G are opened. The terminal T, is coupled with the terminal T in the control circuit 1, so that the first pulse train P, corresponds to the clock pulses CP. Accordingly, the counter 2 counts the number of clock pulses CP. Four counting states (BC=1, BC=2, BC=3 and BC=4) are employed to indicate four bits of each digit. For example, a digit designated by one true at the counting state BC=1 and the three falses at the counting states BC=2, BC=3 and BC=4 corresponds to a decimal number 1, while a digit designated by one true at the counting state BC=2" and three falses at the counting states BC=1, BC=3 and BC= 4 corresponds to a decimal number 2." The carry pulses of the counter 2 are applied to the terminal T, as the second pulse train P in the control circuit 1. The number of pulses of the second pulse train P is counted by the counter 3. Twenty counting states (DC=1, DC=2, DC-20) of the counter 3 are employed to determine ordinal numbers of digits. For example, serial date obtained at the outputs of the

registers

6,7,8 and 9 at the counting state (DC=1) are determined as a first digit. Similarly, serial date obtained at outputs of the

registers

6,7 ,8 and 9 at the counting state (DC=16) are determined as a 16th digit. The counter 4 is employed for counting the number of shifts so as to detect how many digits are shifted in the registers from lower to higher. Accordingly, the pulse train P, is applied to the terminal T from the control circuit 1 when the number of shifts is to be detected. The 16 counting states of the counter 4 are called as SC=0, SC=1,... and SC-IS. Moreover, the counter 4 is reset to the counting states SCfil except necessary times. In FIG. 6 time charts for the counting states of the

counters

2,3 and clock pulses CP are shown. In the display time, the

counters

2, 3 and 4 operates as mentioned below. FIGS. 7A and 7B show the clock pulses CP, states of the

counters

2,3 and 4 and the signal DISPLAY (W5) at an instant when the operation mode of the system is switched from the logical operation time t to the display operation time ID. When states DC=20 and BC=4 are timed with one of the clock pulses CP at the logical operation time after completion of operations caused by instructions by the keyboard 5, the signal DISPLAY W and the signal ms- PLAY (w,,) become true and false respectively. Accordingly, the gates 6,, G, and G are closed while the gates G,, G, and G are opened.

' The scaIe-of-ZO counter 3 counts the clock pulses CP applied through the AND gate 6,, opened by the signal DIS- PLAY (W5). In this case, a time for the four counting states representative of 1, 2" 3" and 4 (hereinafter called as DC=1, DC=2, BC=3 and BC=4) of this counter 3 corresponds to the time t, for reading out a digit from one of the

registers

6, 7, 8 and 9 to the buffer register 10. A time for the next thirteen counting states representative of 5" to 17 (hereinafter called as DC=5, DC=17) of this counter 3 is the display time for generating the slope waves w, and W while a time for the last three counting states representative of 18," 19" and 20" (i.e.; DC=18, DC=l9, and DC=20) of the counter 3 corresponds to an idle time 1,. Accordingly, a

carry pulse of the counter 3 indicates the play for one digit.

The carry output of the counter 3 is applied to the AND gate G together with the signal DISPLAY (W5) and the clock pulses CP. Accordingly, the scale-of-16 counter 4 counts the number of digits displayed by counting the number of carry pulses of the counter 3. Accordingly, the count-up of the counter 4 indicates the completion of display for sixteen digits displayed in one line of the displayed pattern.

The carry output of the counter 4 is applied to the AND gate G together with the signal DISPLAY (W5), the clock pulses CP and the carry output of the counter 3. Accordingly, the scale-of-4 counter 2 counts the number of lines of the displayed pattern by counting the number of carry pulses of the counter 4. The four counting states of the counter 2 are employed for designating respectively the

registers

9, 8, 7 and 6 to be read out to the buffer register 10. Accordingly, a carry pulse of the counter 4 indicates the completion of display for four lines of the displayed pattern.

As mentioned above, the lines of displayed pattern are switched successively in response to each of the carry pulses of the counter 4. In this case, the bias potential in the vertical completion of dissignal applied from the vertical signal amplifier 25 to the cathode-ray tube 27 must be deviated, by a large deviation voltage, in response to each of successive switching of the displayed lines. In other words, a bias current flowing through the vertical deflection coil of the cathode-ray tube is deviated, by a large deviation current, in response to successive switching of the displayed lines. This deviation current has the largest value at the switching from the highest line to the lowest line of the displayed pattern. However, the step change of the bias current cannot be perfectly carried out due to transient by the time constant of the deflection circuit and the delay of change of a current flowing through the vertical deflection coil. Accordingly, numerals displayed at the beginning part of the switched line are disturbed and fluctuated by the above-mentioned transient at the switching to the next line. To eliminate these undesirable phenomena, the slope waves W and w are generated after four clock pulses from the switching instant changed to the next line of the displayed pattern. Moreover, four bits of information can be transfered to one of the

registers

6, 7, 8 and 9 to the buffer register 10 at the time t, of four clock pulses.

As mentioned above, the

counters

2, 3 and 4 and the

registers

6, 7, 8 and 9 are commonly used both for the logical operation and for the display operation in the system of this invention. Accordingly, the patterns are not at all displayed on the screen of the cathode-ray tube 27 at the keying operation of the keyboard 5 for instructing data to the calculating means illustrated in FIG. 1 by chain lines or at the logical operation in the above-mentioned calculating means. However, if the system is so designed that the logical operation time is shorter as far as possible, an operator can manipulate this system without embarrassment since the blanking time of the displayed pattern becomes very short.

Next, change of condition of this system from the logical operation time 1,, to the display time t will be described. At this time of the change of condition, if the deflection circuit (25, 26) of the cathode-ray tube 27 is constructed by amplifiers without use of direct-coupling (e.g., a capacitive coupling amplifier), complete change to the normal display condition of the entire display system is delayed due to the time constant determined in accordance with the condition of the deflection means of the cathode-ray tube 27. This delay for changing to the normal display condition of the entire display system disturbs the displayed pattern, so that eyes of the operators are fatigued with this disturbance of the displayed pattern.

To eliminate the above-mentioned disturbance of the displayed pattern at the change of condition from the logical operation time t to the display time 1 each of the adders and 22 are constructed as shown in FIG. 4A by way of example. In the following, the adder 22 is mainly described. However, the adder 20 is similar, in principle, to the adder 22.

The adder 22 comprises an ADDER-l and and ADDER-Z. The ADDER-l comprises a diode D,, resistors R, and R connected together to a common junction .1, to combine the signal DISPLAY (W8) supplied from a terminal T (connected to the inverter 21), the horizontal step wave w applied from a terminal T (connected to the horizontal step generator 18) as shown in FIG. 5A, and the horizontal slope wave w, applied from a terminal T (connected to the buffer amplifier 17). The output of the buffer amplifier 16 is applied to the common junction J 1 through a resistor. However, this connection means is not shown in FIG. 4A for simple illustration. The signal DISPLAY (W5) assumes zero volt (0 V) at the display time t and a predetermined plus voltage VV) at the logical operation time t as shown in FIG. 4B. The combined output of the ADDER-l is further combined with the signal DIS- PLAY (w supplied from a terminal T (connected to the input of the inverter 21) at the ADDER-2 which comprises a resister R and a series-connection of a diode D and a resistor R The resistor R and the series-connection are connected together to a common junction J The signal DISPLAY (w assumes zero volt (0 V) at the display time n; and a predetermined minus voltage VV) at the logical operation time 1,, respectively.

As the result of the above construction of the ADDER-l and the ADDER-Z, a wave on which the horizontal step wave w, (shown in FIG. 5A) and the horizontal slope wave w shown in FIG. 3C) are combined to each other as shown in FIG. 5C is obtained at the output of the ADDER-l at the display time t since the signal DISPLAY (W6) assumes the zero volt at this display time t On the other hand, since the signal DISPLAY (W5) assumes also the zero volt at this display time t,,, the wave shown in FIG. 5C is also obtained at the output of the ADDER-Z at this display time r If the condition of the system is changed from the display time to the logical operation time t under control of the control circuit I started in response to the keying of any key on the keyboard 5, the signal DISPLAY (w assumes the voltage +VV as shown in FIGS. 58 and 5D since the diode D becomes conductive. Accordingly, the output of the ADDER- 1 assumes the voltage +VV as shown in FIG. 5D. On the other hand, the output of the ADDER-2 assumes a constant voltage determined by the resistances of the resistors R and R as shown in FIG. 5E since voltage +VV and VV are applied to respective terminals of the resistors R and R through the diodes D and D respectively. Accordingly, if the respective resistances of the resistors R and R are so determined that the output of the ADDER-Z at this logical operation time t, is equal to the average direct-current value of voltage (Le, -AV) of the output of the ADDER-2 at the display time I as shown in FIG. 5F, disturbance of the displayed pattern caused at the changing time from the logical operation time t to the display time t can be eliminated.

What we claim is:

1. A display system for displaying an information pattern in a logical operation device, comprising:

a keyboard for generating instructions of an operation mode of a logical operation device,

counters for performing said logical operation in accordance with said instructions comprising a first counter for generating a first timing pulse train and carry pulses, a second counter for generating carry pulses and a second timing pulse train timed with each digit of the displayed pattern by stepping said carry pulses of the first counter, and a third counter for generating a third timing pulse train timed with each line of the displayed pattern by stepping said carry pulses of the second counter,

a plurality of registers for temporarily storing digital information indicative of process results of said logical operatron, means for switching the inputs of said counters, means for generating a vertical slope wave in response to the first timing pulse train, means for generating a horizontal slope wave in response to the first timing pulse train,

means for generating a vertical step wave stepped-up in time with each pulse of the third pulse train,

means for generating a horizontal step wave stepped-up in time with each pulse of the second pulse train,

a first adder for combining the vertical step wave with the vertical slope wave,

a second adder for combining the horizontal step wave with the horizontal slope wave,

means for maintaining the average voltages of the respective outputs from said first and second adders at respectively stable values irrespective of the presence of a vertical step wave, a vertical slope wave, a horizontal slope wave, or a horizontal step wave at the respective inputs to said first and second adders,

a cathode-ray tube comprising vertical deflection means, horizontal deflection means, and a brightness modulation means,

a vertical signal amplifier of a non-direct coupling type for amplifying the output of said first adder for application to the vertical deflection means of the cathode-ray tube, horizontal signal amplifier of a non-direct coupling type for amplifying the output of the second adder for application to the horizontal deflection means of the cathode-ray tube,

buffer register for temporarily storing one digit read out 25 from any of said registers within a predetermined time synchronized with pulses of the first timing pulse train, and

means for generating a blanking signal corresponding to the digit read out of said buffer register for application to the brightness-modulation means of the cathode-ray tube thereby to obtain a desired display pattern on the screen of the cathode-ray tube.

2. A display system according to claim 2, in which four of said registers are to store four lines of said displayed pattern, and the third counter is used as a scale-of-four counter.

3. A display system according to claim 1, in which the first counter is a scale-of-20 counter with which the first four counting states are employed to read out said one digit to the buffer register, the next thirteen counting states are employed for generating the vertical slope wave and the horizontal slope wave, and the last three counting states are employed as an idle time.

4. A display system according to claim 1, in which the second counter is a scale-of-n counter, so that n digits are displayed on one line of the displayed pattern.

5. In a display system for displaying on the screen of a cathode-ray tube pattern information in a logical operation device, an improvement comprising: counters and registers used in common for both a logical operation of the logical operation device and the display operation of the system, means for alternately switching said counters and registers between periods of the logical operation and the display operation, means for maintaining the average voltages of respective inputs of a vertical signal amplifier and a horizontal signal amplifier for the cathode-ray tube at stable values in both the period of logical operation and the period of the display operation, means for delaying, by a predetermined time, start of slope waves for each digit from the start of a digit display time, and means for temporarily storing digital information indicative of a just-succeeding displayed digit in said predetermined time, whereby disturbance and fluctuation of the displayed pattern at an instant when the operation mode of the system is switched from the logical operation to the display operation are effectively eliminated.

Claims

1. A display system for displaying an information pattern in a logical operation device, comprising: a keyboard for generating instructions of an operation mode of a logical operation device, counters for performing said logical operation in accordance with said instructions comprising a first counter for generating a first timing pulse train and carry pulses, a second counter for generating carry pulses and a second timing pulse train timed with each digit of the displayed pattern by stepping said carry pulses of the first counter, and a third counter for generating a third timing pulse train timed with each line of the displayed pattern by stepping said carry pulses of the second counter, a plurality of registers for temporarily storing digital information indicative of process results of said logical operation, means for switching the inputs of said counters, means for generating a vertical slope wave in response to the first timing pulse train, means for generating a horizontal slope wave in response to the first timing pulse train, means for generating a vertical step wave stepped-up in time with each pulse of the third pulse train, means for generating a horizontal step wave stepped-up in time with each pulse of the second pulse train, a first adder for combining the vertical step wave with the vertical slope wave, a second adder for combining the horizontal step wave with the horizontal slope wave, means for maintaining the average voltages of the respective outputs from said first and second adders at respectively stable values irrespective of the presence of a vertical step wave, a vertical slope wave, a horizontal slope wave, or a horizontal step wave at the respective inputs to said first and second adders, a cathode-ray tube comprising vertical deflection means, horizontal deflection means, and a brightness modulation means, a vertical signal amplifier of a non-direct coupling type for amplifying the output of said first adder for application to the vertical deflection means of the cathode-ray tube, a horizontal signal amplifier of a non-direct coupling type for amplifying the output of the second adder for application to the horizontal deflection means of the cathode-ray tube, a buffer register for temporarily storing one digit read out from any of said registers within a predetermined time synchronized with pulses of the first timing pulse train, and means for generating a blanking signal corresponding to the digit read out of said buffer register for application to the brightness-modulation means of the cathode-ray tube thereby to obtain a desired display pattern on the screen of the cathoderay tube.

4. A display system according to claim 1, in which the second counter is a scale-of-n counter, so that ''''n'''' digits are displayed on one line of the displayed pattern.