US3533102A - Code generator - Google Patents
Code generator Download PDFInfo
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- US3533102A US3533102A US677008A US3533102DA US3533102A US 3533102 A US3533102 A US 3533102A US 677008 A US677008 A US 677008A US 3533102D A US3533102D A US 3533102DA US 3533102 A US3533102 A US 3533102A
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- cores
- register
- core
- code generator
- stored
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
Definitions
- BY W 49 5 justable delay means are connected to receive control signals from the nal stage of said counter and from said clock pulse generator.
- the apparatus of claim 3 including second inhibiting gate means, means connecting said clock pulse generator to an input of said second inhibiting gate means, means connecting the output of said shift register to a second input of said second inhibiting gate means, and means connecting an output of said second inhibiting gate means to the reset input of said flipop whereby a clock pulse from said clock pulse generator will cause said ipop to reset except when inhibited by an output pulse from said shift register.
- the invention is in the field of code generators.
- various electromechanical and electronic code generators have been used. However, most of them have been complex, expensive, cumbersome, and in many cases, delicate. This resulted in a lack of portability and ruggedness, and excessive maintenance and power consumption.
- a bank of multi-position switches have their respective multiple contacts connected through different patterns of set windings to set selected cores in a magnetic core shift register so that a serial coded output peculiar to each switch position can be shifted out of the register.
- a switch position can represent a particular letter or other character and the serial register output can be in Morse or other code, to generate any desired output information.
- One obvious application is for a radio station call letter generator. Accessory gating and counting means sequence the letters and adjust the spacing between individual letters and groups of letters.
- the apparatus is constructed of solid state elements to lower the Weight and power requirements. The resultsin a compact and rugged code generator which requires little maintenance or adjustment.
- FIG. 1 shows the arrangement of the principal elements of the apparatus.
- FIG. 2 shows part of a magnetic shift register
- FIG. 3 shows the threading pattern of the core windings connected to one contact of a multi-position switch.
- FIG. 4 is a threading diagram for all the cores required to store twenty-six call letters.
- FIG. 1 The preferred embodiment of the invention is shown in FIG. 1 where three switches S1, S2, and S3, each having twenty-seven positions, are shown. In twenty-six of the s-witch positions, wipers W1, W2, and W3 will rest on one of twenty-six contacts C1, C2, C3, etc. Each wiper is connected to a driver 4 to receive a respective timed ice pulse T1, T2, or T3. The like numbered contacts of each switch are connected together as shown, i.e., C1 of S1 is connected to C1 of S2 and to C1 of S3, etc.
- Each contact is also connected through a respective line L1-L2'6 to an individual setting circuit which passes through the set windings of selected cores of a magnetic core shift register 2.
- Each of the switch contacts represents a single character such as a call letter and the setting circuit to which it is connected is designed to store binary bits representing that call letter in shift register 2.
- Register 2 is comprised of thirteen pairs of cores connected through their respective windings as shown in FIG. 2. Each pair is comprised of an A or storage core 1A, 2A, etc., and a B or temporary storage core 1B, 2B, etc.
- binary ls and Ois are stored in the A cores and when an A clock pulse is received on the A shift line, the bit stored in the A core will be shifted to the B core of that pair, and Iwhen the following B clock pulse is received at the B shift line of register 2, the bit temporarily stored in the B core will be shifted to the A core of the following pair.
- any bits stored in the A cores will move through the register, progressing through succeeding pairs of cores each time a pair of clock pulses is received at the shift inputs.
- Each A core which is set stores a binary l which in the convention chosen may represent, in one example, a dot in Morse code.
- Binary ls stored in three adjacent A cores represent a dash.
- a binary 0 represents a space and the dots and dashes are separated by a single space.
- a call letter is separated by three succeeding spaces, or three adjacent 0 storing A cores.
- a pulse T1 is received from driver i4 it is forwarded over the Wiper W1 through whatever contact W1 rests on, to the connected setting circuit through selected A cores to ground.
- the cores set thereby will represent a stored dash, dash, dash, dot, representing the letter I in Morse code, when read out of shift register 2 in reverse order. Since all cores are initially in a reset condition, the cores A4, A8, and A12 will remain in a reset condition to represent the spaces between the dashes and dot.
- Switched cores S1-S3 are respectively connected to different setting circuits similar to that shown in FIG. 3, but threaded through different combinations of A cores representing, for example, different call letters.
- any call letter or other information desired may be stored in register 2 by moving one of wipers W1-W3 to the appropriate contact C1-C26.
- T1, T2, or T3 is received at the wiper from driver 4
- the threaded cores of the selected setting circuit are set to store the desired information.
- a Variable rate clock 6 furnishes A and B pulses to the shift input terminals SA and SB of register 2 over lines 8 and 10.
- the A pulse passes through a normally open inhibiting gate 12 between clock 6 and register 2.
- Gate 12 may receive an inhibiting signal over line 14 from an adjustable one shot multi-vibrator 38 through or gate 16.
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- Nonlinear Science (AREA)
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Description
J. J. ROWE CODE GENERATOR Oct. 6, 1970 3 Sheets-Sheet 1 Filed Oct. 19, 1967 Oct. 6, 1970 J. J. Rows; 3,533,102
CODE GENERATOR Filed Oct. 19, 1967 5 Sheets-Sheet 2 Figo? Y A43 AlzAu Ano A9 A8 A7 A6 A5 A4 A3 vA2M JO/m J Rowe INVENTOR.
BY L 4265i@ J. J. ROWE CODE GENERATOR 5 sheets-sheet s Filed Oct. 19, 1967 fla Jo/m Rowe INVENTOR. BY W 49 5 justable delay means are connected to receive control signals from the nal stage of said counter and from said clock pulse generator.
4. The apparatus of claim 3 including second inhibiting gate means, means connecting said clock pulse generator to an input of said second inhibiting gate means, means connecting the output of said shift register to a second input of said second inhibiting gate means, and means connecting an output of said second inhibiting gate means to the reset input of said flipop whereby a clock pulse from said clock pulse generator will cause said ipop to reset except when inhibited by an output pulse from said shift register.
6 References Cited UNITED STATES PATENTS 2,844,815 7/1958 Winick 340-347 X 2,938,078 5/1960 Canfora et al. 340-347 X 3,003,144 10/1961 Tyrlick 340-347 3,123,809 3/1964 Brouwer.
MAYNARD R. WILBUR, Primary Examiner 10 M. K. WOLENSKY, Assistant Examiner U.S. C1. X.R. 340-174, 348
United States Patent O 3,533,102 CODE GENERATOR John J. Rowe, Bowie, Md., assignor, by mesne assignments, to the United States of America as represented by the Secretary of the Navy Filed Oct. 19, 1967, Ser. No. 677,008 Int. Cl. H03k 13/258 U.S. Cl. 340--347 4 Claims ABSTRACT F THE DISCLOSURE A bank of multi-position switches are adjustable to set selected cores in a magnetic shift register. The set windings are connected through the cores in such patterns that when the switch wipers are moved to particular positions representing particular characters such as, for example, letters or numbers, shift pulses applied to the register will produce a serial output representing the stored information.
BACKGROUND OF THE INVENTION The invention is in the field of code generators. In the prior art various electromechanical and electronic code generators have been used. However, most of them have been complex, expensive, cumbersome, and in many cases, delicate. This resulted in a lack of portability and ruggedness, and excessive maintenance and power consumption.
SUMMARY OF THE INVENTION A bank of multi-position switches have their respective multiple contacts connected through different patterns of set windings to set selected cores in a magnetic core shift register so that a serial coded output peculiar to each switch position can be shifted out of the register. A switch position can represent a particular letter or other character and the serial register output can be in Morse or other code, to generate any desired output information. One obvious application is for a radio station call letter generator. Accessory gating and counting means sequence the letters and adjust the spacing between individual letters and groups of letters. The apparatus is constructed of solid state elements to lower the Weight and power requirements. The resultsin a compact and rugged code generator which requires little maintenance or adjustment.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows the arrangement of the principal elements of the apparatus.
FIG. 2 shows part of a magnetic shift register.
FIG. 3 shows the threading pattern of the core windings connected to one contact of a multi-position switch.
FIG. 4 is a threading diagram for all the cores required to store twenty-six call letters.
DESCRIPTION OF THE PREFERRED EMBODIMENT The preferred embodiment of the invention is shown in FIG. 1 where three switches S1, S2, and S3, each having twenty-seven positions, are shown. In twenty-six of the s-witch positions, wipers W1, W2, and W3 will rest on one of twenty-six contacts C1, C2, C3, etc. Each wiper is connected to a driver 4 to receive a respective timed ice pulse T1, T2, or T3. The like numbered contacts of each switch are connected together as shown, i.e., C1 of S1 is connected to C1 of S2 and to C1 of S3, etc. Each contact is also connected through a respective line L1-L2'6 to an individual setting circuit which passes through the set windings of selected cores of a magnetic core shift register 2. Each of the switch contacts represents a single character such as a call letter and the setting circuit to which it is connected is designed to store binary bits representing that call letter in shift register 2. Register 2 is comprised of thirteen pairs of cores connected through their respective windings as shown in FIG. 2. Each pair is comprised of an A or storage core 1A, 2A, etc., and a B or temporary storage core 1B, 2B, etc. As is Well known in the art, binary ls and Ois are stored in the A cores and when an A clock pulse is received on the A shift line, the bit stored in the A core will be shifted to the B core of that pair, and Iwhen the following B clock pulse is received at the B shift line of register 2, the bit temporarily stored in the B core will be shifted to the A core of the following pair. Thus, any bits stored in the A cores will move through the register, progressing through succeeding pairs of cores each time a pair of clock pulses is received at the shift inputs. When a core stores a binary l it is` said to be set and when a binary 0 is stored the core is said to be resetf The contacts C1 of S1, S2, and S3 are connected to a setting circuit shown in FIG. 3 which is connected through the set windings of the A cores A1, A2, A3, A5, A6, A7, A9, A10, A11, and A13. Each A core which is set stores a binary l which in the convention chosen may represent, in one example, a dot in Morse code. Binary ls stored in three adjacent A cores represent a dash. A binary 0 represents a space and the dots and dashes are separated by a single space. A call letter is separated by three succeeding spaces, or three adjacent 0 storing A cores. When a pulse T1 is received from driver i4 it is forwarded over the Wiper W1 through whatever contact W1 rests on, to the connected setting circuit through selected A cores to ground. It is apparent that when a T1 pulse traverses the setting circuit connected to contact C1 in FIG. 3, the cores set thereby will represent a stored dash, dash, dash, dot, representing the letter I in Morse code, when read out of shift register 2 in reverse order. Since all cores are initially in a reset condition, the cores A4, A8, and A12 will remain in a reset condition to represent the spaces between the dashes and dot. Contacts C2C26 of switches S1-S3 are respectively connected to different setting circuits similar to that shown in FIG. 3, but threaded through different combinations of A cores representing, for example, different call letters. Thus, any call letter or other information desired may be stored in register 2 by moving one of wipers W1-W3 to the appropriate contact C1-C26. When the appropriate timed pulse T1, T2, or T3 is received at the wiper from driver 4, the threaded cores of the selected setting circuit are set to store the desired information. A Variable rate clock 6 furnishes A and B pulses to the shift input terminals SA and SB of register 2 over lines 8 and 10. The A pulse passes through a normally open inhibiting gate 12 between clock 6 and register 2. Gate 12 may receive an inhibiting signal over line 14 from an adjustable one shot multi-vibrator 38 through or gate 16. Y
Assume that the wipers of W1, W2, and W3 are resting
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US67700867A | 1967-10-19 | 1967-10-19 |
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US3533102A true US3533102A (en) | 1970-10-06 |
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US677008A Expired - Lifetime US3533102A (en) | 1967-10-19 | 1967-10-19 | Code generator |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3739354A (en) * | 1970-04-17 | 1973-06-12 | Lannionnais Electronique | Variable capacity memory |
JPS5648888B1 (en) * | 1971-06-18 | 1981-11-18 | ||
GB2298097A (en) * | 1995-02-20 | 1996-08-21 | Sony Corp | Data transfer circuit |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2844815A (en) * | 1953-01-02 | 1958-07-22 | American Mach & Foundry | Beacon coders |
US2938078A (en) * | 1956-08-10 | 1960-05-24 | Rca Corp | Electronic extensor |
US3003144A (en) * | 1959-06-04 | 1961-10-03 | Gen Dynamics Corp | Converter device |
US3123809A (en) * | 1958-06-04 | 1964-03-03 | Number testing arrangement |
-
1967
- 1967-10-19 US US677008A patent/US3533102A/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2844815A (en) * | 1953-01-02 | 1958-07-22 | American Mach & Foundry | Beacon coders |
US2938078A (en) * | 1956-08-10 | 1960-05-24 | Rca Corp | Electronic extensor |
US3123809A (en) * | 1958-06-04 | 1964-03-03 | Number testing arrangement | |
US3003144A (en) * | 1959-06-04 | 1961-10-03 | Gen Dynamics Corp | Converter device |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3739354A (en) * | 1970-04-17 | 1973-06-12 | Lannionnais Electronique | Variable capacity memory |
JPS5648888B1 (en) * | 1971-06-18 | 1981-11-18 | ||
GB2298097A (en) * | 1995-02-20 | 1996-08-21 | Sony Corp | Data transfer circuit |
US5657464A (en) * | 1995-02-20 | 1997-08-12 | Sony Corporation | Data transfer circuit for use with a base unit or a handset of a telephone system |
GB2298097B (en) * | 1995-02-20 | 1999-05-12 | Sony Corp | Data transfer circuit |
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