[go: up one dir, main page]

US20160247813A1 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
US20160247813A1
US20160247813A1 US14/629,537 US201514629537A US2016247813A1 US 20160247813 A1 US20160247813 A1 US 20160247813A1 US 201514629537 A US201514629537 A US 201514629537A US 2016247813 A1 US2016247813 A1 US 2016247813A1
Authority
US
United States
Prior art keywords
layer
dielectric layers
semiconductor device
layers
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US14/629,537
Other versions
US9437611B1 (en
Inventor
Erh-Kun Lai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Macronix International Co Ltd
Original Assignee
Macronix International Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Macronix International Co Ltd filed Critical Macronix International Co Ltd
Priority to US14/629,537 priority Critical patent/US9437611B1/en
Assigned to MACRONIX INTERNATIONAL CO., LTD. reassignment MACRONIX INTERNATIONAL CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LAI, ERH-KUN
Priority to US14/730,340 priority patent/US9576972B2/en
Priority to CN201510385424.9A priority patent/CN105914184B/en
Publication of US20160247813A1 publication Critical patent/US20160247813A1/en
Application granted granted Critical
Publication of US9437611B1 publication Critical patent/US9437611B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H01L27/11582—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H01L21/28282—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L29/04—
    • H01L29/16—
    • H01L29/4916—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0128—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/016—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • the disclosure relates in general to a semiconductor device and a manufacturing method thereof, and more particularly to a vertical channel semiconductor device and a manufacturing method thereof.
  • the disclosure is directed to a semiconductor device and a manufacturing method thereof. Part of a charge trapping structure is etched and then a landing pad layer is formed to form a thick landing pad for stably connecting with a bit line.
  • a manufacturing method of a semiconductor device includes the following steps.
  • a bottom insulating layer is formed on a substrate.
  • Two stacked structures are formed on the bottom insulating layer.
  • Each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers, a top insulating layer and a conductive mask layer.
  • the gate layers and the gate insulating layers are alternately disposed on the bottom insulating layer.
  • the top insulating layer is disposed on the gate layers and the gate insulating layers.
  • the conductive mask layer is disposed on the top insulating layer.
  • a charge trapping structure and a channel layer are formed on a lateral surface of each of the stacked structures and a top surface of the bottom insulating layer.
  • Each of the charge trapping structures includes a plurality of first dielectric layers and a plurality of second dielectric layers. Part of each of first dielectric layers is etched to expose part of each of the second dielectric layers. Part of each of second dielectric layers is etched to expose part of the channel layer.
  • a landing pad layer is formed on the conductive mask layer, the first dielectric layers and the second dielectric layers to connect the conductive mask layer and the channel layer.
  • a semiconductor device includes a substrate, a bottom insulating layer, two stacked structures, a charge trapping structure and a landing pad layer.
  • the bottom insulating layer is disposed on the substrate.
  • the stacked structures are disposed on the bottom insulating layer.
  • Each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers and a conductive mask layer.
  • the gate layers and the gate insulating layers are alternately disposed on the bottom insulating layer.
  • the top insulating layer is disposed on the gate layers and the gate insulating layers.
  • the conductive mask layer is disposed on the top insulating layer.
  • the charge trapping structure and a channel layer are disposed on a lateral surface of each of the stacked structures and a top surface of the bottom insulating layer.
  • Each of the charge trapping structures includes a plurality of first dielectric layers and a plurality of second dielectric layers.
  • a top of the channel layer is higher than a top of each of the first dielectric layers and a top of each of the second dielectric layers.
  • the landing pad layer is disposed on the conductive mask layer, the first dielectric layers and the second dielectric layers for connecting the conductive mask layer and the channel layer.
  • FIG. 1 shows a semiconductor device
  • FIGS. 2A to 2F show a flowchart of a manufacturing method of the semiconductor device according to one embodiment.
  • FIGS. 3A to 3F show a flowchart of a manufacturing method of the semiconductor device according to another embodiment.
  • the semiconductor device 100 is a three-dimensional vertical channel NAND device.
  • the semiconductor device 100 includes a substrate 110 , a bottom insulating layer 120 , at least two stacked structures 130 , a charge trapping structure 140 , a channel layer 150 , a landing pad layer 160 and a spaced insulating layer 170 .
  • Each stacked structure 130 includes a plurality of gate layers 131 , a plurality of gate insulating layers 132 , a top insulating layer 133 and a conductive mask layer 134 .
  • the charge trapping structure 140 includes a plurality of first dielectric layer 141 and a plurality of second dielectric layer 142 .
  • Each gate layer 131 is connected to a gate G, the landing pad layer 160 is connected to a source S or a drain D.
  • the landing pad layer 160 is connected to a bit line. As shown in FIG. 1 , because a thickness T 1 of a combination of the conductive mask layer 134 and the landing pad layer 160 is larger than a thickness T 2 of the channel layer 150 , a contact resistance between the bit line and the landing pad layer 160 can be reduced. Furthermore, it is easy to make a contact between the bit line and the landing pad layer 160 . It is a self-aligned process without any additional lithography process. Moreover, the connect between the channel layer 150 and the landing pad layer 160 is at the side-wall of the channel layer 150 , not at the top of the channel layer 150 . It will improve the process window and reduce the resistance. In addition, no corner edge effect will be happened in this structure. The reason is that there is no first dielectric layer 141 (SiN) at any corner edge which will be easily programmed/erased due to the electric field enhancement.
  • SiN first dielectric layer 141
  • FIGS. 2A to 2F a flowchart of a manufacturing method of the semiconductor device 100 according to one embodiment is shown.
  • the substrate 110 is provided.
  • the bottom insulating layer 120 is formed on the substrate 110 .
  • a material of the bottom insulating layer 120 is silicon oxide.
  • each gate layer 131 and the gate insulating layer 132 are alternately formed on the bottom insulating layer 120 , such that the gate layers 131 are electrically insulated with each other.
  • a material of each gate layer 131 may be N+ or P+ doping polysilicon, preferred P+ doping polysilicon, and a material of each gate insulating layer 132 is silicon oxide.
  • the top insulating layer 133 is formed on the gate layers 131 and the gate insulating layers 132 .
  • a material of the top insulating layer 133 is silicon oxide.
  • the conductive mask layer 134 is formed on the top insulating layer 133 for preventing etching the top insulating layer 133 and connecting to the landing pad layer 160 (shown in FIG. 1 ) and the channel layer 150 (shown in FIG. 1 ).
  • the insulating mask layer 135 is formed on the conductive mask layer 134 .
  • a material of the insulating mask layer 135 is silicon nitride.
  • the gate layers 131 , the gate insulating layers 132 , the top insulating layer 133 , the conductive mask layer 134 and the insulating mask layer 135 are etched to form two stacked structures 130 and a trench 130 a located therebetween.
  • the insulating mask layer 135 is used for stabilizing the stacked structures 130 during the manufacturing process.
  • the charge trapping structure 140 and the channel layer 150 are formed on a lateral surface 130 b of each stacked structure 130 and a top surface 120 a of the bottom insulating layer 120 .
  • the charge trapping structure 140 and the channel layer 150 are U shaped.
  • a material of the channel layer 150 may be an intrinsic or undoped polysilicon.
  • the charge trapping structure 140 may be an O1N1O2N2O3N3O4 structure (O1 is closer to the channel layer 150 and O4 is closer to the stacked layer 130 ).
  • the 4 different silicon oxide layer (O1, O2, O3 and O4) have different thicknesses and the 3 different silicon nitride layer (N 1 , N 2 , N 3 ) have different thicknesses.
  • the charge trapping structure 140 may be an O1N1O2N2O3 (O1 is closer to the channel layer 150 and O3 is closer to the stacked layer 130 ).
  • the 3 different silicon oxide layer (O1, O2, O3) have different thicknesses and the 2 different silicon nitride layer (N1, N2) have different thicknesses.
  • the different thicknesses are based on the purpose of tunneling (O1N1O2), trapping (N2), blocking (O3 or O3N3N4).
  • the spaced insulating layer 170 is filled in the trench 130 a formed between the stacked structures 130 .
  • a material of the spaced insulating layer 170 is silicon oxide.
  • the spaced insulating layer 170 may not be fully filled in the trench 130 a , and an air gap structure may be formed in the spaced insulating layer 170 .
  • Air can be a good insulator.
  • each first dielectric layer 141 is etched to expose part of each second dielectric layer 142 .
  • H 3 PO 4 is used for etching silicon nitride. Because H 3 PO 4 has high selectivity to polysilicon and silicon oxide, the conductive mask layer 134 , the channel layer 150 , the second dielectric layers 142 and the spaced insulating layer 170 will not be etched.
  • the insulating mask layer 135 is removed, so the surface of the conductive mask layer 134 is exposed.
  • Part of the first dielectric layer 141 is etched, so two lateral walls of at least one of the second dielectric layers 142 are partially exposed.
  • the first dielectric layers 141 will be etched with different depths under the etching loading effect.
  • each second dielectric layer 142 is etched to expose part of the channel layer 150 .
  • DHF is used for etching silicon oxide. Because DHF has high selectivity to polysilicon and silicon nitride, the conductive mask layer 134 , the channel layer 150 and the first dielectric layers 141 will not be etched.
  • each second dielectric layer 142 is etched, so two lateral walls of each first dielectric layer 141 are exposed. Furthermore, part of the spaced insulating layer 170 is also etched, so two lateral walls of the channel layer 150 are partially exposed, and a top of the channel layer 150 is higher than tops of the first dielectric layers 141 and tops of the second dielectric layer 142 .
  • the second dielectric layers 142 will be etched with different depths under the etching loading effect. Moreover, the conductive mask layer 134 can prevent the top insulating layer 133 from damage.
  • the landing pad layer 160 is formed on the conductive mask layer 134 , the first dielectric layers 141 and the second dielectric layers 142 to connect the conductive mask layer 134 and the channel layer 150 .
  • a material of the landing pad layer 160 is N type doping polysilicon.
  • the landing pad layer 160 and the channel layer 150 are also polished, such that top surfaces of the landing pad layer 160 , the channel layer 150 and spaced insulating layer 170 are located at the same level.
  • the combination of the conductive mask layer 134 and the landing pad layer 160 is used as a landing pad for connecting the bit line.
  • the thickness T 1 of the combination of the conductive mask layer 134 and the landing pad layer 160 is larger than the thickness T 2 of the channel layer 150 , such that the contact resistance between the bit line and the landing pad layer 160 can be reduced.
  • the connect between the channel layer 150 and the landing pad layer 160 is at the side-wall of the channel layer 150 , not at the top of the channel layer 150 . It will improve the process window and reduce the resistance.
  • the insulating mask layer 135 is used for stabilizing the stacked structures 130 during the manufacturing process.
  • the manufacturing method can be performed without forming the insulating mask layer 135 .
  • FIGS. 3A to 3F a flowchart of a manufacturing method of a semiconductor device 200 according to another embodiment is shown. In this embodiment, a thickness of a conductive mask layer 234 is increased, such that the conductive mask layer 234 can be used for stabilizing the stacked structure 230 .
  • the landing pad layer 160 and the conductive mask layer 234 are used as a landing pad for connecting the bit line.
  • a thickness T 3 of the conductive mask layer 234 and the landing pad layer 160 is larger than the thickness T 2 of the channel layer 150 , such that the contact resistance between the bit line and the landing pad layer 160 can be reduced. Furthermore, it is easy to make a contact between the bit line and the landing pad layer 160 .

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)

Abstract

A semiconductor device and a manufacturing method of a semiconductor device thereof are provided. The manufacturing method includes the following steps. A bottom insulating layer is formed on a substrate. Two stacked structures are formed on the bottom insulating layer. Each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers, a top insulating layer and a conductive mask layer. Each of the charge trapping structures includes a plurality of first dielectric layers and a plurality of second dielectric layers. Part of each of first dielectric layers is etched. Part of each of second dielectric layers is etched to expose part of the channel layer. A landing pad layer is formed on the conductive mask layer, the first dielectric layers and the second dielectric layers to connect the conductive mask layer and the channel layer.

Description

    BACKGROUND
  • 1. Technical Field
  • The disclosure relates in general to a semiconductor device and a manufacturing method thereof, and more particularly to a vertical channel semiconductor device and a manufacturing method thereof.
  • 2. Description of the Related Art
  • In recent years, the structures of semiconductor devices have been changed constantly, and the storage capacity of the devices has been increased continuously. Memory is used for storing varied electronic products such as MP3 files, digital images, computer documents, etc. As the application increases, the demand for the memory focuses on small size and large memory capacity. For satisfying the requirement, a memory having a high element density and a small size and the manufacturing method thereof are in need.
  • As such, it is desirable to develop a vertical channel memory to achieve greater storage capacity, a small size, and yet having excellent property and stability.
    • SUMMARY
  • The disclosure is directed to a semiconductor device and a manufacturing method thereof. Part of a charge trapping structure is etched and then a landing pad layer is formed to form a thick landing pad for stably connecting with a bit line.
  • According to a first aspect of the present disclosure, a manufacturing method of a semiconductor device is provided. The manufacturing method includes the following steps. A bottom insulating layer is formed on a substrate. Two stacked structures are formed on the bottom insulating layer. Each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers, a top insulating layer and a conductive mask layer. The gate layers and the gate insulating layers are alternately disposed on the bottom insulating layer. The top insulating layer is disposed on the gate layers and the gate insulating layers. The conductive mask layer is disposed on the top insulating layer. A charge trapping structure and a channel layer are formed on a lateral surface of each of the stacked structures and a top surface of the bottom insulating layer. Each of the charge trapping structures includes a plurality of first dielectric layers and a plurality of second dielectric layers. Part of each of first dielectric layers is etched to expose part of each of the second dielectric layers. Part of each of second dielectric layers is etched to expose part of the channel layer. A landing pad layer is formed on the conductive mask layer, the first dielectric layers and the second dielectric layers to connect the conductive mask layer and the channel layer.
  • According to a second aspect of the present disclosure, a semiconductor device is provided. The semiconductor includes a substrate, a bottom insulating layer, two stacked structures, a charge trapping structure and a landing pad layer. The bottom insulating layer is disposed on the substrate. The stacked structures are disposed on the bottom insulating layer. Each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers and a conductive mask layer. The gate layers and the gate insulating layers are alternately disposed on the bottom insulating layer. The top insulating layer is disposed on the gate layers and the gate insulating layers. The conductive mask layer is disposed on the top insulating layer. The charge trapping structure and a channel layer are disposed on a lateral surface of each of the stacked structures and a top surface of the bottom insulating layer. Each of the charge trapping structures includes a plurality of first dielectric layers and a plurality of second dielectric layers. A top of the channel layer is higher than a top of each of the first dielectric layers and a top of each of the second dielectric layers. The landing pad layer is disposed on the conductive mask layer, the first dielectric layers and the second dielectric layers for connecting the conductive mask layer and the channel layer.
  • The above and other aspects of the disclosure will become better understood with regard to the following detailed description of the non-limiting embodiment(s). The following description is made with reference to the accompanying drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows a semiconductor device.
  • FIGS. 2A to 2F show a flowchart of a manufacturing method of the semiconductor device according to one embodiment.
  • FIGS. 3A to 3F show a flowchart of a manufacturing method of the semiconductor device according to another embodiment.
    •  DETAILED DESCRIPTION
  • Preferred embodiments are disclosed below for elaborating the invention. Part of a charge trapping structure is etched and then a landing pad layer is formed to form a thick landing pad for stably connecting with a bit line. The following embodiments are for the purpose of elaboration only, not for limiting the scope of protection of the invention. Besides, secondary elements are omitted in the following embodiments to highlight the technical features of the invention.
  • Please referring FIG. 1, a semiconductor device 100 is shown. For example, the semiconductor device 100 is a three-dimensional vertical channel NAND device. The semiconductor device 100 includes a substrate 110, a bottom insulating layer 120, at least two stacked structures 130, a charge trapping structure 140, a channel layer 150, a landing pad layer 160 and a spaced insulating layer 170.
  • Each stacked structure 130 includes a plurality of gate layers 131, a plurality of gate insulating layers 132, a top insulating layer 133 and a conductive mask layer 134. The charge trapping structure 140 includes a plurality of first dielectric layer 141 and a plurality of second dielectric layer 142. Each gate layer 131 is connected to a gate G, the landing pad layer 160 is connected to a source S or a drain D.
  • The landing pad layer 160 is connected to a bit line. As shown in FIG. 1, because a thickness T1 of a combination of the conductive mask layer 134 and the landing pad layer 160 is larger than a thickness T2 of the channel layer 150, a contact resistance between the bit line and the landing pad layer 160 can be reduced. Furthermore, it is easy to make a contact between the bit line and the landing pad layer 160. It is a self-aligned process without any additional lithography process. Moreover, the connect between the channel layer 150 and the landing pad layer 160 is at the side-wall of the channel layer 150, not at the top of the channel layer 150. It will improve the process window and reduce the resistance. In addition, no corner edge effect will be happened in this structure. The reason is that there is no first dielectric layer 141 (SiN) at any corner edge which will be easily programmed/erased due to the electric field enhancement.
  • Please referring to FIGS. 2A to 2F, a flowchart of a manufacturing method of the semiconductor device 100 according to one embodiment is shown. As shown in FIG. 2A, the substrate 110 is provided. Then, as shown in FIG. 2A, the bottom insulating layer 120 is formed on the substrate 110. For example, a material of the bottom insulating layer 120 is silicon oxide.
  • Next, as shown in FIG. 2A, the gate layers 131 and the gate insulating layer 132 are alternately formed on the bottom insulating layer 120, such that the gate layers 131 are electrically insulated with each other. For example, a material of each gate layer 131 may be N+ or P+ doping polysilicon, preferred P+ doping polysilicon, and a material of each gate insulating layer 132 is silicon oxide.
  • Then, as shown in FIG. 2A, the top insulating layer 133 is formed on the gate layers 131 and the gate insulating layers 132. For example, a material of the top insulating layer 133 is silicon oxide.
  • Next, as shown in FIG. 2A, the conductive mask layer 134 is formed on the top insulating layer 133 for preventing etching the top insulating layer 133 and connecting to the landing pad layer 160 (shown in FIG. 1) and the channel layer 150 (shown in FIG. 1).
  • Then, as shown in FIG. 2A, the insulating mask layer 135 is formed on the conductive mask layer 134. For example, a material of the insulating mask layer 135 is silicon nitride.
  • Next, as shown in FIG. 2B, the gate layers 131, the gate insulating layers 132, the top insulating layer 133, the conductive mask layer 134 and the insulating mask layer 135 are etched to form two stacked structures 130 and a trench 130 a located therebetween. The insulating mask layer 135 is used for stabilizing the stacked structures 130 during the manufacturing process.
  • Then, as shown in FIG. 2C, the charge trapping structure 140 and the channel layer 150 are formed on a lateral surface 130 b of each stacked structure 130 and a top surface 120 a of the bottom insulating layer 120. The charge trapping structure 140 and the channel layer 150 are U shaped. A material of the channel layer 150 may be an intrinsic or undoped polysilicon. For example, the charge trapping structure 140 may be an O1N1O2N2O3N3O4 structure (O1 is closer to the channel layer 150 and O4 is closer to the stacked layer 130). The 4 different silicon oxide layer (O1, O2, O3 and O4) have different thicknesses and the 3 different silicon nitride layer (N1, N2, N3) have different thicknesses. Or, the charge trapping structure 140 may be an O1N1O2N2O3 (O1 is closer to the channel layer 150 and O3 is closer to the stacked layer 130). The 3 different silicon oxide layer (O1, O2, O3) have different thicknesses and the 2 different silicon nitride layer (N1, N2) have different thicknesses. The different thicknesses are based on the purpose of tunneling (O1N1O2), trapping (N2), blocking (O3 or O3N3N4).
  • Next, as shown in FIG. 2C, the spaced insulating layer 170 is filled in the trench 130 a formed between the stacked structures 130. For example, a material of the spaced insulating layer 170 is silicon oxide. In this step, the spaced insulating layer 170 may not be fully filled in the trench 130 a, and an air gap structure may be formed in the spaced insulating layer 170. Air can be a good insulator.
  • Afterwards, as shown in FIG. 2D, part of each first dielectric layer 141 is etched to expose part of each second dielectric layer 142. In this step, H3PO4 is used for etching silicon nitride. Because H3PO4 has high selectivity to polysilicon and silicon oxide, the conductive mask layer 134, the channel layer 150, the second dielectric layers 142 and the spaced insulating layer 170 will not be etched. In this step, the insulating mask layer 135 is removed, so the surface of the conductive mask layer 134 is exposed. Part of the first dielectric layer 141 is etched, so two lateral walls of at least one of the second dielectric layers 142 are partially exposed.
  • Because thicknesses of the first dielectric layers 141 are different, the first dielectric layers 141 will be etched with different depths under the etching loading effect.
  • Next, as shown in FIG. 2E, part of each second dielectric layer 142 is etched to expose part of the channel layer 150. In this step, DHF is used for etching silicon oxide. Because DHF has high selectivity to polysilicon and silicon nitride, the conductive mask layer 134, the channel layer 150 and the first dielectric layers 141 will not be etched.
  • In this step, part of each second dielectric layer 142 is etched, so two lateral walls of each first dielectric layer 141 are exposed. Furthermore, part of the spaced insulating layer 170 is also etched, so two lateral walls of the channel layer 150 are partially exposed, and a top of the channel layer 150 is higher than tops of the first dielectric layers 141 and tops of the second dielectric layer 142.
  • Because thicknesses of the second dielectric layers 142 are different, the second dielectric layers 142 will be etched with different depths under the etching loading effect. Moreover, the conductive mask layer 134 can prevent the top insulating layer 133 from damage.
  • Next, as shown in FIG. 2F, the landing pad layer 160 is formed on the conductive mask layer 134, the first dielectric layers 141 and the second dielectric layers 142 to connect the conductive mask layer 134 and the channel layer 150. For example, a material of the landing pad layer 160 is N type doping polysilicon.
  • In this step, the landing pad layer 160 and the channel layer 150 are also polished, such that top surfaces of the landing pad layer 160, the channel layer 150 and spaced insulating layer 170 are located at the same level. The combination of the conductive mask layer 134 and the landing pad layer 160 is used as a landing pad for connecting the bit line. The thickness T1 of the combination of the conductive mask layer 134 and the landing pad layer 160 is larger than the thickness T2 of the channel layer 150, such that the contact resistance between the bit line and the landing pad layer 160 can be reduced. Moreover, the connect between the channel layer 150 and the landing pad layer 160 is at the side-wall of the channel layer 150, not at the top of the channel layer 150. It will improve the process window and reduce the resistance. Furthermore, it is easy to make a contact between the bit line and the landing pad layer 160. In addition, no corner edge effect will be happened in this structure. The reason is that no first dielectric layer 141 (SiN) at corner edge which will be easily programmed/erased due to the electric field enhancement.
  • In the manufacturing method described above, the insulating mask layer 135 is used for stabilizing the stacked structures 130 during the manufacturing process. In one embodiment, the manufacturing method can be performed without forming the insulating mask layer 135. Please referring to FIGS. 3A to 3F, a flowchart of a manufacturing method of a semiconductor device 200 according to another embodiment is shown. In this embodiment, a thickness of a conductive mask layer 234 is increased, such that the conductive mask layer 234 can be used for stabilizing the stacked structure 230.
  • In FIG. 3F, the landing pad layer 160 and the conductive mask layer 234 are used as a landing pad for connecting the bit line. A thickness T3 of the conductive mask layer 234 and the landing pad layer 160 is larger than the thickness T2 of the channel layer 150, such that the contact resistance between the bit line and the landing pad layer 160 can be reduced. Furthermore, it is easy to make a contact between the bit line and the landing pad layer 160.
  • While the disclosure has been described by way of example and in terms of the exemplary embodiment(s), it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.

Claims (20)

1. A manufacturing method of a semiconductor device, comprising:
forming a bottom insulating layer on a substrate;
forming two stacked structures on the bottom insulating layer, wherein each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers, a top insulating layer and a conductive mask layer, the gate layers and the gate insulating layers are alternately disposed on the bottom insulating layer, the top insulating layer is disposed on the gate layers and the gate insulating layers, and the conductive mask layer is disposed on the top insulating layer;
forming a charge trapping structure and a channel layer on a lateral surface of each of the stacked structures and a top surface of the bottom insulating layer, wherein each of the charge trapping structures includes a plurality of first dielectric layers and a plurality of second dielectric layers;
etching part of each of first dielectric layers to expose part of each of the second dielectric layers;
etching part of each of second dielectric layers to expose part of the channel layer; and
forming a landing pad layer on the conductive mask layer, the first dielectric layers and the second dielectric layers to connect the conductive mask layer and the channel layer.
2. The manufacturing method of the semiconductor device according to claim 1, wherein each of the stacked structures further includes an insulating mask layer disposed on the conductive mask layer, in the step of etching part of each first dielectric layer, the insulating mask layer is removed.
3. The manufacturing method of the semiconductor device according to claim 2, wherein a material of each of the first dielectric layers and a material of the insulating mask layer are the same.
4. The manufacturing method of the semiconductor device according to claim 1, wherein a material of the conductive mask layer, a material of the channel layer and a material of the landing pad layer are the same.
5. The manufacturing method of the semiconductor device according to claim 1, wherein in the step of etching part of each of the first dielectric layers, the first dielectric layers are etched with different depths.
6. The manufacturing method of the semiconductor device according to claim 1, wherein in the step of etching part of each of the first dielectric layers, two lateral walls of at least one of the second dielectric layers are partially exposed.
7. The manufacturing method of the semiconductor device according to claim 1, wherein in the step of etching part of each of the second dielectric layers, the second dielectric layers are etched with different depths.
8. The manufacturing method of the semiconductor device according to claim 1, further comprising:
filling a spaced insulating layer in a trench formed between the stacked structures;
wherein in the step of etching part of each of the second dielectric layers, part of the spaced insulating layer is also etched, such that a top of the channel layer is higher than tops of the first dielectric layers and tops of the second dielectric layer.
9. The manufacturing method of the semiconductor device according to claim 1, wherein the step of etching part of each of the second dielectric layers is performed after the step of etching part of each of the first dielectric layers.
10. The manufacturing method of the semiconductor device according to claim 1, wherein a material of each of the first dielectric layers is silicon nitride, and a material of each of the second dielectric layers is silicon oxide.
11. The manufacturing method of the semiconductor device according to claim 1, wherein a material of each of the gate layers is P type doping polysilicon, and a material of each of the conductive mask layer, the channel layer and the landing pad layer is N type doping polysilicon.
12. A semiconductor device, comprising:
a substrate;
a bottom insulating layer disposed on the substrate;
two stacked structures disposed on the bottom insulating layer, wherein each of the stacked structures includes:
a plurality of gate layers and a plurality of gate insulating layers alternately disposed on the bottom insulating layer;
a top insulating layer disposed on the gate layers and the gate insulating layers; and
a conductive mask layer disposed on the top insulating layer;
a charge trapping structure and a channel layer disposed on a lateral surface of each of the stacked structures and a top surface of the bottom insulating layer, wherein each of the charge trapping structures includes a plurality of first dielectric layers and a plurality of second dielectric layers, a top of the channel layer is higher than a top of each of the first dielectric layers and a top of each of the second dielectric layers; and
a landing pad layer disposed on the conductive mask layer, the first dielectric layers and the second dielectric layers for connecting the conductive mask layer and the channel layer.
13. The semiconductor device according to claim 12, wherein a thickness of a combination of the landing pad layer and the conductive mask layer is larger than a thickness of the channel layer.
14. The semiconductor device according to claim 12, wherein a material of the conductive mask layer, a material of the channel layer and a material of the landing pad layer are the same.
15. The semiconductor device according to claim 12, wherein tops the first dielectric layers are located at different levels.
16. The semiconductor device according to claim 12, wherein two lateral walls of each of the first dielectric layers partially contact the landing pad layer.
17. The semiconductor device according to claim 12, wherein tops of the second dielectric layers are located at different levels.
18. The semiconductor device according to claim 12, wherein the charge trapping structure and the channel layer are U shaped.
19. The semiconductor device according to claim 12, wherein a material of each of the first dielectric layers is silicon nitride, and a material of each of the second dielectric layers is silicon oxide.
20. The semiconductor device according to claim 12, wherein a material of each of the gate layers is P type doping polysilicon, and a material of each of the conductive mask layer, the channel layer and the landing pad layer is N type doping polysilicon.
US14/629,537 2015-02-24 2015-02-24 Semiconductor device and manufacturing method thereof Active US9437611B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US14/629,537 US9437611B1 (en) 2015-02-24 2015-02-24 Semiconductor device and manufacturing method thereof
US14/730,340 US9576972B2 (en) 2015-02-24 2015-06-04 Semiconductor device and manufacturing method thereof
CN201510385424.9A CN105914184B (en) 2015-02-24 2015-06-30 Semiconductor device and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/629,537 US9437611B1 (en) 2015-02-24 2015-02-24 Semiconductor device and manufacturing method thereof

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14/730,340 Continuation-In-Part US9576972B2 (en) 2015-02-24 2015-06-04 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
US20160247813A1 true US20160247813A1 (en) 2016-08-25
US9437611B1 US9437611B1 (en) 2016-09-06

Family

ID=56693826

Family Applications (1)

Application Number Title Priority Date Filing Date
US14/629,537 Active US9437611B1 (en) 2015-02-24 2015-02-24 Semiconductor device and manufacturing method thereof

Country Status (2)

Country Link
US (1) US9437611B1 (en)
CN (1) CN105914184B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9923139B2 (en) * 2016-03-11 2018-03-20 Micron Technology, Inc. Conductive hard mask for memory device formation
CN110391289A (en) * 2019-06-20 2019-10-29 长江存储科技有限责任公司 A kind of semiconductor structure and its manufacturing method
CN113345911A (en) * 2021-06-02 2021-09-03 长江存储科技有限责任公司 Preparation method of semiconductor device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105990248A (en) * 2015-02-26 2016-10-05 旺宏电子股份有限公司 Semiconductor device and manufacturing method thereof
KR102373616B1 (en) * 2017-07-06 2022-03-11 삼성전자주식회사 Semiconductor device and Method for fabricating thereof
CN109346474B (en) * 2018-10-16 2020-07-10 长江存储科技有限责任公司 Three-dimensional memory and method for forming three-dimensional memory

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100155818A1 (en) * 2008-12-24 2010-06-24 Heung-Jae Cho Vertical channel type nonvolatile memory device and method for fabricating the same
US8659944B2 (en) 2010-09-01 2014-02-25 Macronix International Co., Ltd. Memory architecture of 3D array with diode in memory string
KR101857681B1 (en) * 2011-07-07 2018-05-14 삼성전자주식회사 3-dimensional semiconductor memory devices and methods for fabricating the same
KR20130044711A (en) * 2011-10-24 2013-05-03 에스케이하이닉스 주식회사 Three dimension non-volatile memory device, memory system comprising the same and method of manufacturing the same
KR101916223B1 (en) * 2012-04-13 2018-11-07 삼성전자 주식회사 Semiconductor device and manufacturing the same
KR102003526B1 (en) * 2012-07-31 2019-07-25 삼성전자주식회사 Semiconductor memory devices and methods for fabricating the same
KR102114341B1 (en) * 2013-07-08 2020-05-25 삼성전자주식회사 Vertical semiconductor devices
TWI508257B (en) 2013-10-29 2015-11-11 Macronix Int Co Ltd Three dimensional stacked semiconductor structure and method for manufacturing the same
US9305937B1 (en) * 2014-10-21 2016-04-05 Sandisk Technologies Inc. Bottom recess process for an outer blocking dielectric layer inside a memory opening
US9502429B2 (en) * 2014-11-26 2016-11-22 Sandisk Technologies Llc Set of stepped surfaces formation for a multilevel interconnect structure
US9530781B2 (en) * 2014-12-22 2016-12-27 Sandisk Technologies Llc Three dimensional NAND memory having improved connection between source line and in-hole channel material as well as reduced damage to in-hole layers

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9923139B2 (en) * 2016-03-11 2018-03-20 Micron Technology, Inc. Conductive hard mask for memory device formation
US10103326B2 (en) * 2016-03-11 2018-10-16 Micron Technology, Inc. Conductive hard mask for memory device formation
US20180358549A1 (en) * 2016-03-11 2018-12-13 Micron Technology, Inc. Conductive hard mask for memory device formation
US10741753B2 (en) * 2016-03-11 2020-08-11 Micron Technology, Inc. Conductive hard mask for memory device formation
CN110391289A (en) * 2019-06-20 2019-10-29 长江存储科技有限责任公司 A kind of semiconductor structure and its manufacturing method
CN113345911A (en) * 2021-06-02 2021-09-03 长江存储科技有限责任公司 Preparation method of semiconductor device

Also Published As

Publication number Publication date
CN105914184A (en) 2016-08-31
CN105914184B (en) 2019-03-19
US9437611B1 (en) 2016-09-06

Similar Documents

Publication Publication Date Title
US9437611B1 (en) Semiconductor device and manufacturing method thereof
US10566348B1 (en) Tilted hemi-cylindrical 3D NAND array having bottom reference conductor
CN103426824B (en) The method for manufacturing nonvolatile semiconductor memory member
US8754464B2 (en) Non-volatile memory devices including gates having reduced widths and protection spacers and methods of manufacturing the same
US8877587B2 (en) Nonvolatile memory device and method for fabricating the same
US10559584B2 (en) Semiconductor device including a dielectric layer
US8809933B2 (en) Bit line structure, semiconductor device and method of forming the same
WO2019100836A1 (en) Three-dimensional memory structure and manufacturing method thereof
US10283519B2 (en) Three dimensional NAND string memory device
KR102344876B1 (en) Semiconductor devices and methods of manufacturing the same
US9576972B2 (en) Semiconductor device and manufacturing method thereof
US20190157287A1 (en) Three-dimensional memory structure and manufacturing method thereof
US20140061759A1 (en) Nonvolatile memory device and method for fabricating the same
US9455155B2 (en) Semiconductor structure and manufacturing method for the same
US9196494B2 (en) Semiconductor device and method of manufacturing the same
JP4250616B2 (en) Semiconductor integrated circuit device and manufacturing method thereof
CN106158871B (en) Memory device and method of manufacturing the same
US9337209B1 (en) Semiconductor device and method of fabricating the same
TWI517365B (en) Memory device and method for fabricating the same
CN103367127B (en) Semiconductor structure and manufacturing method thereof
US10692875B2 (en) Memory structure
TWI569372B (en) Semiconductor device and manufacturing method thereof
CN105990248A (en) Semiconductor device and manufacturing method thereof
TWI607528B (en) Semiconductor device and manufacturing method thereof
TWI722816B (en) Three dimensional memory device

Legal Events

Date Code Title Description
AS Assignment

Owner name: MACRONIX INTERNATIONAL CO., LTD., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LAI, ERH-KUN;REEL/FRAME:035011/0733

Effective date: 20150217

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8