[go: up one dir, main page]

US20150380062A1 - Memory module and video camera - Google Patents

Memory module and video camera Download PDF

Info

Publication number
US20150380062A1
US20150380062A1 US14/850,616 US201514850616A US2015380062A1 US 20150380062 A1 US20150380062 A1 US 20150380062A1 US 201514850616 A US201514850616 A US 201514850616A US 2015380062 A1 US2015380062 A1 US 2015380062A1
Authority
US
United States
Prior art keywords
controller
connector
memories
memory module
mounting board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US14/850,616
Inventor
Yasuyuki NAGAHARA
Isao Ozawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to US14/850,616 priority Critical patent/US20150380062A1/en
Publication of US20150380062A1 publication Critical patent/US20150380062A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5602—Interface to device under test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10159—Memory
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10189—Non-printed connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10545—Related components mounted on both sides of the PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/162—Testing a finished product, e.g. heat cycle testing of solder joints
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • Embodiments described herein relate generally to a memory module and a video camera.
  • the pin pitch of a connector used for the external connection has become smaller. For this reason, when a cable for testing is frequently inserted into and removed from a connector for the purpose of testing the memory module, the connector may wear out or collect metallic particles thereon, which sometimes causes poor contact of the connector.
  • Japanese Unexamined Patent Application Publication No. 2006-302278 discloses a method for mounting a semiconductor chip for memory and a semiconductor chip for controller on a main surface of a base substrate for a semiconductor memory card and electrically connecting test pads to the semiconductor chip for memory through wiring of the base substrate.
  • FIG. 1 is a block diagram illustrating an outline configuration of a memory module according to a first embodiment.
  • FIGS. 2A to 2C are diagrams illustrating an external structure of the memory module 2 of FIG. 1 .
  • FIG. 3 is a cross sectional view illustrating an outline arrangement of internal wiring layers of the memory module 2 of FIG. 2 .
  • FIG. 4 is a diagram showing one example of names of signals transmitted to individual pins of a connector 3 of FIG. 2 .
  • FIG. 5 is a diagram showing one example of names of signals transmitted to individual test pads 4 of FIG. 2 .
  • FIG. 6 is a cross sectional view illustrating a state of the memory module 2 of FIG. 1 during a test.
  • FIG. 7 is a block diagram illustrating an outline configuration of a memory module 31 according to a second embodiment.
  • FIGS. 8A and 8B are diagrams illustrating an external structure of a memory module according to a third embodiment.
  • the memory module is provided with semiconductor memories, a controller, and a connector.
  • the semiconductor memories are mounted on both sides of a mounting board.
  • the controller is mounted on an obverse side of the mounting board or a reverse side of the mounting board and performs read/write control of the semiconductor memories.
  • the connector is mounted on the obverse side of the mounting board or the reverse side of the mounting board in a manner laterally deviated from the controller so as not to overlap the controller and transfers signals exchanged between the controller and the outside.
  • FIG. 1 is a block diagram illustrating an outline configuration of a memory module according to a first embodiment.
  • a memory module 2 is provided with a connector 3 , test pads 4 , a damping resistor 5 , a controller 6 , and NAND memories 7 a - 7 d .
  • the connector 3 is connected to the controller 6 through the damping resistor 5 , and the test pads 4 are drawn out from a connection between the connector 3 and the damping resistor 5 .
  • the controller 6 is connected to the NAND memories 7 a - 7 d.
  • NAND flash memories can be used as the NAND memories 7 a - 7 d , and it is possible to provide thereto a unit cell array, a decoder, a sense amplifier, a charge pump circuit, a page buffer, and so on.
  • the connector 3 can transfer control signals, data signals, and the like that are exchanged between the controller 6 and the outside.
  • Test pads 4 can transfer test signals that are exchanged between the controller 6 and the outside.
  • the damping resistor 5 can attenuate a spike-like waveform included in a signal input to the controller through the connector 3 or the test pads 4 .
  • a plurality of NAND flash memory chips may be stacked and contained in the NAND memories 7 a - 7 d individually. For example, by laying four NAND memory chips on top of one another and accommodating them altogether, it is possible to increase the memory capacity by four times with the occupied area almost the same as that required when one NAND flash memory chip is used.
  • the controller 6 can control writing and reading to and from the NAND memories 7 a - 7 d .
  • the controller 6 can perform, as a process specific to the NAND memories 7 a - 7 d , wear leveling or defective block processing.
  • the controller 6 may be provided with an ECC function for error detection and correction. It is also possible to provide a DRAM or the like used for writing into the NAND memories 7 a - 7 d at once by collecting a certain amount of write data so that the substantial write endurance of the NAND memories 7 a - 7 d is prolonged.
  • the test signals are input to the controller 6 via the test pads 4 .
  • the spike-like noise is attenuated by the damping resistor 5 and input to the controller 6 .
  • a response resulted from inputting the test signals to the controller 6 is obtained through the test pads 4 to thereby determine whether writing and reading to and from the NAND memories 7 a - 7 d are performed normally. This way, the memory module 2 is determined good or bad.
  • a cable 8 is inserted into the connector 3 to thereby connect between the host computer 1 and the memory module 2 .
  • the write data is sent to the controller 6 by way of the connector 3 and the damping resistor 5 and written into the NAND memories 7 a - 7 d through the controller 6 .
  • FIG. 2A is a plan view showing an external structure of the memory module 2 of FIG. 1 ;
  • FIG. 2B is a rear view showing an external structure of the memory module 2 of FIG. 1 ;
  • FIG. 2C is a cross sectional view of the memory module 2 of FIG. 1 cut along a portion of the NAND memories 7 a - 7 d.
  • NAND memory BGAs (ball grid arrays) 11 a and 11 b are mounted on the obverse side of the mounting board 9 by way of solder balls 12 a and 12 b , respectively, and, at the same time, NAND memory BGAs 11 c and 11 d are mounted on the reverse side of the mounting board 9 by way of solder balls 12 c and 12 d , respectively.
  • the NAND memory BGAs 11 a and 11 b can be mounted on one side of the mounting board 9 and the NAND memory BGAs 11 c and 11 d can be mounted on the other side of the mounting board 9 in a manner opposing each other.
  • the memories 7 a - 7 d illustrated in FIG. 1 can be mounted on the NAND memory BGAs 11 a - 11 d , respectively.
  • PCB polychlorinated biphenyl
  • the connector 3 is mounted and the test pads 4 are formed on the mounting board 9 .
  • the damping resistor 5 is also mounted on the same face where the connector 3 is mounted.
  • the surfaces of the test pads 4 be coated with gold plating.
  • the number of pins of the connector 3 is arranged at 39 or more, and the pin pitch of the connector 3 be arranged in a range from 0.3 mm to 0.5 mm.
  • a semiconductor chip 16 for controller is mounted on the reverse side of the mounting board 9 and sealed with an encapsulating resin 10 to thereby form a COB (Chip On Board). It is possible to incorporate the controller 6 illustrated in FIG. 1 into the semiconductor chip 16 for controller.
  • the semiconductor chip 16 for controller is mounted on the reverse side of the mounting board 9 beside the NAND memories 11 c and 11 d.
  • the connector 3 is mounted on the mounting board 9 in a manner laterally deviated from the semiconductor chip 16 for controller so that they do not overlap each other.
  • the test pads 4 are arranged on the mounting board 9 in a lateral direction beside the connector 3 .
  • a depth A 1 and a width B 1 of the NAND memory BGAs 11 a - 11 d may be set at 14 mm and 18 mm, respectively. It is also possible, for example, to set a depth A 2 , a width B 2 , and a thickness C 1 of the mounting board 9 at 28 mm, 39 mm, and 0.6 mm, respectively.
  • a combined thickness C 2 of the NAND memory BGAs 11 a and 11 c and the mounting board 9 may be set, for example, at 3.7 mm or smaller.
  • a capacity of the NAND memories 7 a - 7 d may be set, for example, at 128 gigabytes, and the memory module 2 may be arranged to be compatible with an SD card.
  • the cable 8 that can be inserted into and removed from the connector 3 has wiring 8 b that is retained by a carrier tape 8 a . Both ends of the carrier tape 8 a have individual external terminals 8 c connected to the wiring 8 b . It is possible to use, for example, polyimide as a material of the carrier tape 8 a , and Cu as a material of the wiring 8 b and the external terminals 8 c . Further, it is preferable that gold plating is applied to the surface of the external terminals 8 c .
  • the carrier tape 8 a may be arranged to have flexibility.
  • the semiconductor chip 16 for controller is mounted by COB technology in a manner laterally deviated from the connector 3 to prevent overlapping, and the NAND memory BGAs 11 a - 11 d are mounted on both sides and the semiconductor chip 16 for controller.
  • the NAND memory BGAs 11 a - 11 d are mounted on both sides and the semiconductor chip 16 for controller.
  • by mounting the NAND memory BGAs 11 a - 11 d on both sides of the mounting board 9 it is possible to perform a unit test on the NAND memories 7 a - 7 d shown in FIG. 1 before they are mounted on the mounting board 9 . This makes it possible to mount only the NAND memories 7 a - 7 d that have passed the test and increase manufacturing yield of the memory module 2 .
  • test pads 4 on the mounting board 9 , it is no longer necessary to insert and remove the cable 8 into and from the connector 3 when the memory module is tested. This arrangement makes it possible to prevent the connector 3 from wear and attracting metallic particles thereon, which contributes to reducing instances of poor contact even when the pin pitch of the connector 3 is narrowed.
  • FIG. 3 is a cross sectional view illustrating an outline arrangement of internal wiring layers of the memory module 2 of FIG. 2 .
  • the mounting board 9 shown in FIG. 2 can be formed of, for example, a four-layer board.
  • first and fourth layers can be used as wiring layers
  • a second layer can be used as a ground layer
  • a third layer can be used as a power supply layer.
  • connection wiring between the test pads 4 and the connector 3 can be also formed in the second layer. It is also possible to connect the damping resistor 5 and the NAND memories 7 a and 7 b to the controller 6 via through holes formed in the mounting board 9 , and connect the NAND memories 7 c and 7 d to the controller 6 via the wiring layer formed in the fourth layer.
  • connection wiring between the test pads 4 and the connector 3 By forming the connection wiring between the test pads 4 and the connector 3 in the second layer, it is possible to connect between the test pads 4 and the connector 3 using a part of the ground layer. For this reason, it is possible to prevent the wiring connecting the test pads 4 and the connector 3 to the controller 6 from becoming complicated. This makes it possible to increase the memory capacity that can be mounted on the mounting board 9 .
  • FIG. 4 is a diagram showing one example of names of signals transmitted to individual pins of the connector 3 of FIG. 2 .
  • the connector 3 shown in FIG. 2 can be provided with 41 pins, i.e., P 1 -P 41 .
  • the pins P 1 , P 2 , P 4 , P 13 , P 22 , P 25 , P 27 , P 29 , P 33 , and P 38 can be connected to the ground.
  • the pins P 40 and P 41 can be connected to the power supply.
  • Signals for controlling the operation of the system can be input to the pins P 3 , P 24 , P 26 , P 28 , P 30 , P 32 , and P 34 -P 36 .
  • Data signal can be input to the pins P 5 -P 21 .
  • FIG. 5 is a diagram showing one example of names of signals transmitted to individual test pads 4 of FIG. 2 .
  • test pad TP 1 is connected to the pin P 20 shown in FIG. 4 ; the test pad TP 2 is connected to the pin P 18 ; the test pad TP 3 is connected to the pin P 16 ; the test pad TP 4 is connected to the pin P 14 ; the test pad TP 5 is connected to the pin P 11 ; the test pad TP 6 is connected to the pin P 9 ; the test pad TP 7 is connected to the pin P 7 ; the test pad TP 8 is connected to the pin P 5 ; the test pad TP 9 is connected to the pin P 6 ; the test pad TP 10 is connected to the pin P 8 ; the test pad TP 11 is connected to the pin P 10 ; the test pad TP 12 is connected to the pin P 12 ; the test pad TP 13 is connected to the pin P 15 ; the test pad TP 14 is connected to the pin P 17
  • FIG. 6 is a cross sectional view illustrating a state of the memory module 2 of FIG. 1 during a test.
  • the semiconductor chip 16 for controller is mounted on the reverse side of the mounting board 9 .
  • the semiconductor chip 16 for controller is electrically connected to the mounting board 9 through bonding wires 13 and sealed with the encapsulating resin 10 together with the bonding wires 13 .
  • Probes 23 are provided upright on a stage 22 and connected to a tester 21 through the stage 22 .
  • the probes 23 may be arranged in a position corresponding to the test pads 4 shown in FIG. 2 .
  • test signals are input to the controller 6 from the tester 21 , and a response from the controller 6 is determined by the tester 21 .
  • the memory module 2 can be subjected to several types of test while the tester 21 is changed. For example, it is possible to perform the separate tests such as the test on the controller 6 or the test on the entirety of the NAND memories 7 a - 7 d.
  • the memory module 2 can be tested by bringing the probes 23 in contact with the test pads 4 .
  • insertion and removal of the cable 8 into and from the connector 3 will no longer be required when the memory module 2 is tested.
  • This arrangement makes it possible to prevent the connector 3 from wear and attracting metallic particles thereon, and reduce instances of poor contact even when the pin pitch of the connector 3 is narrowed.
  • FIG. 7 is a block diagram illustrating an outline configuration of a memory module 31 according to a second embodiment.
  • the memory module 31 is provided with test pads 32 formed on the mounting board 9 instead of the test pads 4 of the memory module 2 shown in FIG. 1 .
  • the test pads 32 are connected in series between the connector 3 and the damping resistor 5 . With this arrangement, it is possible to arrange the memory module 31 to cope with a high transmission speed of 100 Mbits/sec or higher even when the test pads 32 are provided on the mounting board 9 .
  • FIG. 8A is a rear view illustrating an external structure of a memory module according to a third embodiment
  • FIG. 8B is a plan view illustrating an external structure of the memory module according to the third embodiment.
  • NAND memory BGAs 51 a - 51 d are mounted on the obverse side of a mounting board 49 by way of solder balls 52 a - 52 d , respectively.
  • the NAND memory BGAs 51 a - 51 d can be arranged in a form of two rows by two columns.
  • the NAND memories 7 a - 7 d illustrated in FIG. 1 can be mounted on the NAND memory BGAs 51 a - 51 d , respectively.
  • As a material of the mounting board 49 for example, PCB (polychlorinated biphenyl) can be used.
  • a connector 43 is mounted and test pads 44 are formed on the reverse side of the mounting board 49 .
  • a damping resistor 45 is mounted on the same side where the connector 43 is mounted.
  • a semiconductor package 56 for controller is also mounted on the reverse side of the mounting board 49 .
  • the controller 6 illustrated in FIG. 1 can be mounted in the semiconductor package 56 for controller.
  • a QFP quad flat package
  • the damping resistor 45 is positioned between the connector 43 and the semiconductor package 56 for controller, and the test pads 44 are arranged in a lateral direction beside the damping resistor 45 on the mounting board 49 .
  • test pads 44 on the mounting board 49 , it is no longer necessary to insert and remove the cable 8 into and from the connector 43 when the memory module 2 is tested. This arrangement makes it possible to prevent the connector 43 from wear and attracting metallic particles thereon, which contributes to reducing instances of poor contact even when the pin pitch of the connector 43 is narrowed.
  • the memory module 2 or 31 may be used as an internal storage module of a digital video camera, a television set, a mobile information terminal, or the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Architecture (AREA)
  • Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

According to the embodiments, there are provided semiconductor memories that are mounted individually on two sides of a mounting board; a controller that is mounted either on an obverse side or a reverse side of the mounting board, and performs read and write control of the semiconductor memories; and a connector that is deviated in a lateral direction from the controller so as not to overlap the controller, is mounted either on the obverse side or the reverse side of the mounting board, and transfers a signal exchanged between the controller and outside.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is based upon and claims the benefit of priority from International Application No. PCT/JP2010/065078, filed on August 27 and Japanese Patent Application No. 2009-198373, filed on Aug. 28, 2009; the entire contents of all of which are incorporated herein by reference.
    • FIELD
  • Embodiments described herein relate generally to a memory module and a video camera.
    • BACKGROUND
  • Along with miniaturization of a memory module, the pin pitch of a connector used for the external connection has become smaller. For this reason, when a cable for testing is frequently inserted into and removed from a connector for the purpose of testing the memory module, the connector may wear out or collect metallic particles thereon, which sometimes causes poor contact of the connector.
  • For example, Japanese Unexamined Patent Application Publication No. 2006-302278 discloses a method for mounting a semiconductor chip for memory and a semiconductor chip for controller on a main surface of a base substrate for a semiconductor memory card and electrically connecting test pads to the semiconductor chip for memory through wiring of the base substrate.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a block diagram illustrating an outline configuration of a memory module according to a first embodiment.
  • FIGS. 2A to 2C are diagrams illustrating an external structure of the memory module 2 of FIG. 1.
  • FIG. 3 is a cross sectional view illustrating an outline arrangement of internal wiring layers of the memory module 2 of FIG. 2.
  • FIG. 4 is a diagram showing one example of names of signals transmitted to individual pins of a connector 3 of FIG. 2.
  • FIG. 5 is a diagram showing one example of names of signals transmitted to individual test pads 4 of FIG. 2.
  • FIG. 6 is a cross sectional view illustrating a state of the memory module 2 of FIG. 1 during a test.
  • FIG. 7 is a block diagram illustrating an outline configuration of a memory module 31 according to a second embodiment.
  • FIGS. 8A and 8B are diagrams illustrating an external structure of a memory module according to a third embodiment.
    •  DETAILED DESCRIPTION
  • In general, according to one embodiment, the memory module is provided with semiconductor memories, a controller, and a connector. The semiconductor memories are mounted on both sides of a mounting board. The controller is mounted on an obverse side of the mounting board or a reverse side of the mounting board and performs read/write control of the semiconductor memories. The connector is mounted on the obverse side of the mounting board or the reverse side of the mounting board in a manner laterally deviated from the controller so as not to overlap the controller and transfers signals exchanged between the controller and the outside.
  • Exemplary embodiments of memory module will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments.
    • First Embodiment
  • FIG. 1 is a block diagram illustrating an outline configuration of a memory module according to a first embodiment.
  • In FIG. 1, a memory module 2 is provided with a connector 3, test pads 4, a damping resistor 5, a controller 6, and NAND memories 7 a-7 d. The connector 3 is connected to the controller 6 through the damping resistor 5, and the test pads 4 are drawn out from a connection between the connector 3 and the damping resistor 5. Further, the controller 6 is connected to the NAND memories 7 a-7 d.
  • NAND flash memories can be used as the NAND memories 7 a-7 d, and it is possible to provide thereto a unit cell array, a decoder, a sense amplifier, a charge pump circuit, a page buffer, and so on. The connector 3 can transfer control signals, data signals, and the like that are exchanged between the controller 6 and the outside. Test pads 4 can transfer test signals that are exchanged between the controller 6 and the outside. The damping resistor 5 can attenuate a spike-like waveform included in a signal input to the controller through the connector 3 or the test pads 4. A plurality of NAND flash memory chips may be stacked and contained in the NAND memories 7 a-7 d individually. For example, by laying four NAND memory chips on top of one another and accommodating them altogether, it is possible to increase the memory capacity by four times with the occupied area almost the same as that required when one NAND flash memory chip is used.
  • The controller 6 can control writing and reading to and from the NAND memories 7 a-7 d. Specifically, the controller 6 can perform, as a process specific to the NAND memories 7 a-7 d, wear leveling or defective block processing. In addition, the controller 6 may be provided with an ECC function for error detection and correction. It is also possible to provide a DRAM or the like used for writing into the NAND memories 7 a-7 d at once by collecting a certain amount of write data so that the substantial write endurance of the NAND memories 7 a-7 d is prolonged.
  • When the memory module 2 is tested, the test signals are input to the controller 6 via the test pads 4. Here, when the test signals are input to the test pads, the spike-like noise is attenuated by the damping resistor 5 and input to the controller 6. Then, a response resulted from inputting the test signals to the controller 6 is obtained through the test pads 4 to thereby determine whether writing and reading to and from the NAND memories 7 a-7 d are performed normally. This way, the memory module 2 is determined good or bad.
  • On the other hand, when the memory module 2 is used as an external storage device of a host computer 1, a cable 8 is inserted into the connector 3 to thereby connect between the host computer 1 and the memory module 2. When write data is sent from the host computer 1 to the memory module 2, the write data is sent to the controller 6 by way of the connector 3 and the damping resistor 5 and written into the NAND memories 7 a-7 d through the controller 6.
  • FIG. 2A is a plan view showing an external structure of the memory module 2 of FIG. 1; FIG. 2B is a rear view showing an external structure of the memory module 2 of FIG. 1; and FIG. 2C is a cross sectional view of the memory module 2 of FIG. 1 cut along a portion of the NAND memories 7 a-7 d.
  • In FIGS. 2A to 2C, NAND memory BGAs (ball grid arrays) 11 a and 11 b are mounted on the obverse side of the mounting board 9 by way of solder balls 12 a and 12 b, respectively, and, at the same time, NAND memory BGAs 11 c and 11 d are mounted on the reverse side of the mounting board 9 by way of solder balls 12 c and 12 d, respectively. Here, the NAND memory BGAs 11 a and 11 b can be mounted on one side of the mounting board 9 and the NAND memory BGAs 11 c and 11 d can be mounted on the other side of the mounting board 9 in a manner opposing each other. The memories 7 a-7 d illustrated in FIG. 1 can be mounted on the NAND memory BGAs 11 a-11 d, respectively. As a material of the mounting board 9, for example, PCB (polychlorinated biphenyl) can be used.
  • The connector 3 is mounted and the test pads 4 are formed on the mounting board 9. The damping resistor 5 is also mounted on the same face where the connector 3 is mounted. Here, it is preferable that the surfaces of the test pads 4 be coated with gold plating. It is also preferable that the number of pins of the connector 3 is arranged at 39 or more, and the pin pitch of the connector 3 be arranged in a range from 0.3 mm to 0.5 mm. A semiconductor chip 16 for controller is mounted on the reverse side of the mounting board 9 and sealed with an encapsulating resin 10 to thereby form a COB (Chip On Board). It is possible to incorporate the controller 6 illustrated in FIG. 1 into the semiconductor chip 16 for controller. The semiconductor chip 16 for controller is mounted on the reverse side of the mounting board 9 beside the NAND memories 11 c and 11 d.
  • The connector 3 is mounted on the mounting board 9 in a manner laterally deviated from the semiconductor chip 16 for controller so that they do not overlap each other. The test pads 4 are arranged on the mounting board 9 in a lateral direction beside the connector 3.
  • For example, a depth A1 and a width B1 of the NAND memory BGAs 11 a-11 d may be set at 14 mm and 18 mm, respectively. It is also possible, for example, to set a depth A2, a width B2, and a thickness C1 of the mounting board 9 at 28 mm, 39 mm, and 0.6 mm, respectively. A combined thickness C2 of the NAND memory BGAs 11 a and 11 c and the mounting board 9 may be set, for example, at 3.7 mm or smaller. A capacity of the NAND memories 7 a-7 d may be set, for example, at 128 gigabytes, and the memory module 2 may be arranged to be compatible with an SD card.
  • The cable 8 that can be inserted into and removed from the connector 3 has wiring 8 b that is retained by a carrier tape 8 a. Both ends of the carrier tape 8 a have individual external terminals 8 c connected to the wiring 8 b. It is possible to use, for example, polyimide as a material of the carrier tape 8 a, and Cu as a material of the wiring 8 b and the external terminals 8 c. Further, it is preferable that gold plating is applied to the surface of the external terminals 8 c. The carrier tape 8 a may be arranged to have flexibility.
  • In this arrangement, the semiconductor chip 16 for controller is mounted by COB technology in a manner laterally deviated from the connector 3 to prevent overlapping, and the NAND memory BGAs 11 a-11 d are mounted on both sides and the semiconductor chip 16 for controller. With this arrangement, it is possible to increase the capacity of the memory that can be mounted on the mounting board 9 and miniaturize the memory module 2. Further, by mounting the NAND memory BGAs 11 a-11 d on both sides of the mounting board 9, it is possible to perform a unit test on the NAND memories 7 a-7 d shown in FIG. 1 before they are mounted on the mounting board 9. This makes it possible to mount only the NAND memories 7 a-7 d that have passed the test and increase manufacturing yield of the memory module 2.
  • Also, by forming the test pads 4 on the mounting board 9, it is no longer necessary to insert and remove the cable 8 into and from the connector 3 when the memory module is tested. This arrangement makes it possible to prevent the connector 3 from wear and attracting metallic particles thereon, which contributes to reducing instances of poor contact even when the pin pitch of the connector 3 is narrowed.
  • Referring to the embodiment illustrated in FIG. 2, the description was given of the method for mounting the semiconductor chip 16 for controller on a side opposite to the mounting side of the connector 3. However, it is also possible to mount the semiconductor chip 16 for controller on the same side where the connector 3 is mounted. Further, referring to the embodiment illustrated in FIG. 2, the description was given of the method for forming the test pads 4 on the same side where the connector 3 is mounted. However, it is also possible to eliminate the test pads 4. Referring to the embodiment illustrated in FIG. 2, the description was given of the method for mounting the damping resistor 5 on the same side where the connector 3 is mounted. However, it is also possible to mount the damping resistor 5 on a side opposite to the mounting side of the connector 3. Referring to the embodiment illustrated in FIG. 2, the description was given of the method for forming the BGAs to mount the NAND memories 7 a-7 d shown in FIG. 1 and mounting them on the mounting board 9. However, it is also possible to mount, by COB technology, semiconductor chips in which NAND memories 7 a-7 d shown in FIG. 1 are individually formed. Further, in the embodiment described above, the description was given of the method to mount the NAND memories 7 a-7 d on the mounting board 9. However, it is also possible to mount, on the mounting board 9, a semiconductor memory such as the ReRAM or the PCRAM instead of the NAND memories 7 a-7 d.
  • FIG. 3 is a cross sectional view illustrating an outline arrangement of internal wiring layers of the memory module 2 of FIG. 2.
  • Referring to FIG. 3, the mounting board 9 shown in FIG. 2 can be formed of, for example, a four-layer board. In such a case, first and fourth layers can be used as wiring layers, a second layer can be used as a ground layer, a third layer can be used as a power supply layer. In addition, connection wiring between the test pads 4 and the connector 3 can be also formed in the second layer. It is also possible to connect the damping resistor 5 and the NAND memories 7 a and 7 b to the controller 6 via through holes formed in the mounting board 9, and connect the NAND memories 7 c and 7 d to the controller 6 via the wiring layer formed in the fourth layer.
  • With this arrangement, by using the second layer as the ground layer and the third layer as the power supply layer, it is possible to position the ground layer and the power supply layer between the wiring layers, which makes it possible to stabilize the power potential.
  • By forming the connection wiring between the test pads 4 and the connector 3 in the second layer, it is possible to connect between the test pads 4 and the connector 3 using a part of the ground layer. For this reason, it is possible to prevent the wiring connecting the test pads 4 and the connector 3 to the controller 6 from becoming complicated. This makes it possible to increase the memory capacity that can be mounted on the mounting board 9.
  • FIG. 4 is a diagram showing one example of names of signals transmitted to individual pins of the connector 3 of FIG. 2.
  • Referring to FIG. 4, the connector 3 shown in FIG. 2 can be provided with 41 pins, i.e., P1-P41. The pins P1, P2, P4, P13, P22, P25, P27, P29, P33, and P38 can be connected to the ground. The pins P40 and P41 can be connected to the power supply. Signals for controlling the operation of the system can be input to the pins P3, P24, P26, P28, P30, P32, and P34-P36. Data signal can be input to the pins P5-P21.
  • FIG. 5 is a diagram showing one example of names of signals transmitted to individual test pads 4 of FIG. 2.
  • Referring to FIG. 5, 30 pieces of test pads, TP1-TP30, can be provided as the test pads 4 shown in FIG. 2. In this arrangement, the test pad TP1 is connected to the pin P20 shown in FIG. 4; the test pad TP2 is connected to the pin P18; the test pad TP3 is connected to the pin P16; the test pad TP4 is connected to the pin P14; the test pad TP5 is connected to the pin P11; the test pad TP6 is connected to the pin P9; the test pad TP7 is connected to the pin P7; the test pad TP8 is connected to the pin P5; the test pad TP9 is connected to the pin P6; the test pad TP10 is connected to the pin P8; the test pad TP11 is connected to the pin P10; the test pad TP12 is connected to the pin P12; the test pad TP13 is connected to the pin P15; the test pad TP14 is connected to the pin P17; the test pad TP15 is connected to the pin P19; the test pad TP16 is connected to the pin P21; the test pad TP17 is connected to the pin P34; the test pad TP18 is connected to the pin P32; the test pad TP19 is connected to the pin P35; the test pad TP20 is connected to the pin P3; the test pad TP21 is connected to the pin P26; the test pad TP22 is connected to the pin P24; the test pad TP23 is connected to the pin P36; the test pad TP24 is connected to the pin P37; the test pad TP25 is connected to the pin P30; the test pad TP26 is connected to the pin P23; the test pad TP27 is connected to the pin P31; the test pad TP28 is connected to the pin P28; the test pad TP29 is connected to the power supply; and the test pad TP30 is connected to the ground.
  • FIG. 6 is a cross sectional view illustrating a state of the memory module 2 of FIG. 1 during a test.
  • In FIG. 6, the semiconductor chip 16 for controller is mounted on the reverse side of the mounting board 9. The semiconductor chip 16 for controller is electrically connected to the mounting board 9 through bonding wires 13 and sealed with the encapsulating resin 10 together with the bonding wires 13.
  • Probes 23 are provided upright on a stage 22 and connected to a tester 21 through the stage 22. The probes 23 may be arranged in a position corresponding to the test pads 4 shown in FIG. 2.
  • When the memory module 2 is tested, the probes 23 are brought into contact with the test pads 4. Then, test signals are input to the controller 6 from the tester 21, and a response from the controller 6 is determined by the tester 21.
  • The memory module 2 can be subjected to several types of test while the tester 21 is changed. For example, it is possible to perform the separate tests such as the test on the controller 6 or the test on the entirety of the NAND memories 7 a-7 d.
  • By forming the test pads 4 on the mounting board 9, the memory module 2 can be tested by bringing the probes 23 in contact with the test pads 4. With this arrangement, insertion and removal of the cable 8 into and from the connector 3 will no longer be required when the memory module 2 is tested. This arrangement makes it possible to prevent the connector 3 from wear and attracting metallic particles thereon, and reduce instances of poor contact even when the pin pitch of the connector 3 is narrowed.
    • Second Embodiment
  • FIG. 7 is a block diagram illustrating an outline configuration of a memory module 31 according to a second embodiment.
  • Referring to FIG. 7, the memory module 31 is provided with test pads 32 formed on the mounting board 9 instead of the test pads 4 of the memory module 2 shown in FIG. 1. Here, the test pads 32 are connected in series between the connector 3 and the damping resistor 5. With this arrangement, it is possible to arrange the memory module 31 to cope with a high transmission speed of 100 Mbits/sec or higher even when the test pads 32 are provided on the mounting board 9.
    • Third Embodiment
  • FIG. 8A is a rear view illustrating an external structure of a memory module according to a third embodiment, and FIG. 8B is a plan view illustrating an external structure of the memory module according to the third embodiment.
  • Referring to FIG. 8, NAND memory BGAs 51 a-51 d are mounted on the obverse side of a mounting board 49 by way of solder balls 52 a-52 d, respectively. Here, the NAND memory BGAs 51 a-51 d can be arranged in a form of two rows by two columns. The NAND memories 7 a-7 d illustrated in FIG. 1 can be mounted on the NAND memory BGAs 51 a-51 d, respectively. As a material of the mounting board 49, for example, PCB (polychlorinated biphenyl) can be used.
  • On the other hand, a connector 43 is mounted and test pads 44 are formed on the reverse side of the mounting board 49. At the same time, a damping resistor 45 is mounted on the same side where the connector 43 is mounted. A semiconductor package 56 for controller is also mounted on the reverse side of the mounting board 49. The controller 6 illustrated in FIG. 1 can be mounted in the semiconductor package 56 for controller. A QFP (quad flat package) can be used as the semiconductor package 56 for controller. The damping resistor 45 is positioned between the connector 43 and the semiconductor package 56 for controller, and the test pads 44 are arranged in a lateral direction beside the damping resistor 45 on the mounting board 49.
  • By mounting the semiconductor package 56 for controller and the NAND memory BGAs 51 a-51 d on each side of the mounting board 49, it is possible to increase the capacity of the memory that can be mounted on the mounting board 49 and miniaturize the memory module 2. At the same time, by mounting the NAND memory BGAs 51 a-51 d on one side of the mounting board 49, it is possible to perform a unit test on the NAND memories 7 a-7 d shown in FIG. 1 before they are mounted on the mounting board 49. This makes it possible to mount only the NAND memories 7 a-7 d that have passed the test on the mounting board 49 and increase manufacturing yield of the memory module 2.
  • Also, by forming the test pads 44 on the mounting board 49, it is no longer necessary to insert and remove the cable 8 into and from the connector 43 when the memory module 2 is tested. This arrangement makes it possible to prevent the connector 43 from wear and attracting metallic particles thereon, which contributes to reducing instances of poor contact even when the pin pitch of the connector 43 is narrowed.
  • It should be noted that, although the foregoing embodiments describe examples of a method in which the memory module 2 or 31 is used as an external storage device of the host computer 1, the memory module 2 or 31 may be used as an internal storage module of a digital video camera, a television set, a mobile information terminal, or the like.
  • While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

Claims (9)

1-20. (canceled)
21. A module comprising:
a board;
a connector on the board, a longitudinal direction of the connector being a first direction;
a plurality of memories on the board, the memories being arranged in the first direction, the memories being spaced apart from the connector with a gap in a second direction, the second direction intersecting the first direction; and
a controller on the board, the controller arranged with a first area of the board in the first direction, the first area being an area between the connector and a memory in the memories, a first dimension of the controller in the second direction being greater than a second dimension of the gap in the second direction.
22. The module according to claim 21,
wherein the first dimension is a dimension between a first end and a second end, the first end being an end of the controller in the second direction, the second end being an end of the controller in the opposite direction to the second direction, and
the second dimension is a dimension between a third end and a fourth end, the third end being an end of the connector in the second direction, the fourth end being an end of the memory in an opposite direction to the second direction.
23. The module according to claim 21,
wherein the memories include a first memory on a first face of the board and a second memory on a second face of the board, the second face being opposite to the first face.
24. The module according to claim 21,
wherein the memories include a plurality of third memories on a first face of the board and a plurality of fourth memories on a second face of the board, the second face being opposite to the first face.
25. The module according to claim 24,
wherein a third memory in the third memories and a fourth memory in the fourth memories are aligned in a third direction, the third direction intersecting the first direction, the third direction intersecting the second direction.
26. A module comprising:
a board;
a connector on the board, a longitudinal direction of the connector being a first direction;
a plurality of memories on the board, the memories being spaced apart from the connector with a gap in a second direction, the second direction intersecting the first direction, the memories being arranged in a third direction, the third direction intersecting the first direction, the third direction intersecting the second direction; and
a controller on the board, the controller arranged with a first area of the board in the first direction, the first area being an area between the connector and a memory in the memories, a first dimension of the controller in the second direction being greater than a second dimension of the gap in the second direction.
27. The module according to claim 26,
wherein the first dimension is a dimension between a first end and a second end, the first end being an end of the controller in the second direction, the second end being an end of the controller in the opposite direction to the second direction, and
the second dimension is a dimension between a third end and a fourth end, the third end being an end of the connector in the second direction, the fourth end being an end of the memory in an opposite direction to the second direction.
28. A module comprising:
a board having a connector, a longitudinal direction of the connector being a first direction;
a plurality of memories on the board, the memories being arranged in the first direction, the memories being spaced apart from the connector with a gap in a second direction, the second direction intersecting the first direction; and
a controller on the board, the controller arranged with a first area of the board in the first direction, the first area being an area between the connector and one of the memories, a first dimension of the controller in the second direction being greater than a second dimension of the gap in the second direction.
US14/850,616 2009-08-28 2015-09-10 Memory module and video camera Abandoned US20150380062A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/850,616 US20150380062A1 (en) 2009-08-28 2015-09-10 Memory module and video camera

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2009198373A JP2011048756A (en) 2009-08-28 2009-08-28 Memory module
JP2009-198373 2009-08-28
PCT/JP2010/065078 WO2011025060A1 (en) 2009-08-28 2010-08-27 Memory module and video camera
US13/406,892 US9173293B2 (en) 2009-08-28 2012-02-28 Memory module and video camera
US14/850,616 US20150380062A1 (en) 2009-08-28 2015-09-10 Memory module and video camera

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US13/406,892 Continuation US9173293B2 (en) 2009-08-28 2012-02-28 Memory module and video camera

Publications (1)

Publication Number Publication Date
US20150380062A1 true US20150380062A1 (en) 2015-12-31

Family

ID=43628145

Family Applications (2)

Application Number Title Priority Date Filing Date
US13/406,892 Expired - Fee Related US9173293B2 (en) 2009-08-28 2012-02-28 Memory module and video camera
US14/850,616 Abandoned US20150380062A1 (en) 2009-08-28 2015-09-10 Memory module and video camera

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US13/406,892 Expired - Fee Related US9173293B2 (en) 2009-08-28 2012-02-28 Memory module and video camera

Country Status (4)

Country Link
US (2) US9173293B2 (en)
JP (1) JP2011048756A (en)
TW (1) TWI482153B (en)
WO (1) WO2011025060A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9460813B2 (en) 2013-03-14 2016-10-04 Kabushiki Kaisha Toshiba Memory system
JP6235423B2 (en) 2014-06-30 2017-11-22 東芝メモリ株式会社 Semiconductor device
KR102412790B1 (en) * 2018-01-30 2022-06-23 주식회사 엘지에너지솔루션 Method for manufacturing printed circuit board with test points and printed circuit board using thereof

Citations (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5663901A (en) * 1991-04-11 1997-09-02 Sandisk Corporation Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems
US20020006032A1 (en) * 2000-05-23 2002-01-17 Chris Karabatsos Low-profile registered DIMM
US20030090879A1 (en) * 2001-06-14 2003-05-15 Doblar Drew G. Dual inline memory module
US6573567B1 (en) * 1999-12-03 2003-06-03 Hitachi, Ltd. IC card
US6597062B1 (en) * 2002-08-05 2003-07-22 High Connection Density, Inc. Short channel, memory module with stacked printed circuit boards
US6661690B2 (en) * 2002-02-19 2003-12-09 High Connection Density, Inc. High capacity memory module with built-in performance enhancing features
US6683372B1 (en) * 1999-11-18 2004-01-27 Sun Microsystems, Inc. Memory expansion module with stacked memory packages and a serial storage unit
US6686663B2 (en) * 2000-01-31 2004-02-03 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same
US20050021895A1 (en) * 2003-07-23 2005-01-27 Son Chang-Il Removable memory cards including USB and other controllers, connectors, and methods of operating same
US7069370B2 (en) * 2003-01-31 2006-06-27 Toshiba Corporation USB memory storage apparatus with integrated circuit in a connector
US7252240B1 (en) * 2000-07-06 2007-08-07 Onspec Electronics, Inc. Memory module which includes a form factor connector
US20070263365A1 (en) * 2004-06-18 2007-11-15 Hiroyuki Yamada Ic Card
US7324352B2 (en) * 2004-09-03 2008-01-29 Staktek Group L.P. High capacity thin module system and method
US7352601B1 (en) * 2003-11-24 2008-04-01 Michael Paul Minneman USB flash memory device
US7352199B2 (en) * 2001-02-20 2008-04-01 Sandisk Corporation Memory card with enhanced testability and methods of making and using the same
US20080080255A1 (en) * 2006-09-29 2008-04-03 Yishai Kagan Dual Voltage Flash Memory Card
US7389937B2 (en) * 2004-12-15 2008-06-24 Kabushiki Kaisha Toshiba Card-shaped memory device incorporating IC card function
US7423885B2 (en) * 2004-09-03 2008-09-09 Entorian Technologies, Lp Die module system
US7535718B2 (en) * 2003-08-20 2009-05-19 Imation Corp. Memory card compatible with multiple connector standards
US20090210616A1 (en) * 2008-02-12 2009-08-20 Vijay Karamcheti Memory modules for two-dimensional main memory
US20110019370A1 (en) * 2009-07-27 2011-01-27 Gainteam Holdings Limited Flexible circuit module
US8037229B2 (en) * 2002-11-21 2011-10-11 Sandisk Technologies Inc. Combination non-volatile memory and input-output card with direct memory access
US8097939B2 (en) * 2007-12-26 2012-01-17 Kabushiki Kaisha Toshiba Semiconductor memory card
US8259483B1 (en) * 2009-12-30 2012-09-04 Mark Ayers Non-volatile memory module
US20150094875A1 (en) * 2013-09-30 2015-04-02 Yacov Duzly Temperature-Controlled Storage Module that Cools Memory Prior to a Data Burst

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0393308A (en) * 1989-09-06 1991-04-18 Matsushita Electric Ind Co Ltd Digital signal processing unit
JPH0898398A (en) * 1994-09-28 1996-04-12 Mitsubishi Electric Corp Semiconductor device
JP3640155B2 (en) * 1999-01-26 2005-04-20 セイコーエプソン株式会社 Flexible wiring board, film carrier, tape-like semiconductor device, semiconductor device, circuit board, and electronic device
US6757751B1 (en) * 2000-08-11 2004-06-29 Harrison Gene High-speed, multiple-bank, stacked, and PCB-mounted memory module
JP3681636B2 (en) * 2000-12-27 2005-08-10 サンユレック株式会社 Electronic component manufacturing method and apparatus
JP3943502B2 (en) 2001-04-02 2007-07-11 株式会社ルネサステクノロジ Memory card
JP2006302278A (en) 2001-04-02 2006-11-02 Renesas Technology Corp Memory card
JP2003197753A (en) * 2001-12-26 2003-07-11 Elpida Memory Inc Memory device and memory bus transmission system
JP3093308U (en) * 2002-10-08 2003-05-09 アルプス電気株式会社 Card connector structure
KR100951357B1 (en) * 2003-08-19 2010-04-08 삼성전자주식회사 Liquid crystal display
US8102657B2 (en) * 2003-12-02 2012-01-24 Super Talent Electronics, Inc. Single shot molding method for COB USB/EUSB devices with contact pad ribs
US20070086035A1 (en) 2005-10-19 2007-04-19 Wheless Thomas O Jr Printer controller apparatus implemented as a system in a package
JP2007172574A (en) * 2005-11-25 2007-07-05 Seiko Epson Corp Integrated circuit device and electronic apparatus
US20090063895A1 (en) * 2007-09-04 2009-03-05 Kurt Smith Scaleable and maintainable solid state drive
JP4372189B2 (en) * 2007-12-27 2009-11-25 株式会社東芝 Information processing apparatus and nonvolatile semiconductor memory drive
JP2009206429A (en) 2008-02-29 2009-09-10 Toshiba Corp Storage

Patent Citations (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5663901A (en) * 1991-04-11 1997-09-02 Sandisk Corporation Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems
US6683372B1 (en) * 1999-11-18 2004-01-27 Sun Microsystems, Inc. Memory expansion module with stacked memory packages and a serial storage unit
US6573567B1 (en) * 1999-12-03 2003-06-03 Hitachi, Ltd. IC card
US6686663B2 (en) * 2000-01-31 2004-02-03 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same
US20020006032A1 (en) * 2000-05-23 2002-01-17 Chris Karabatsos Low-profile registered DIMM
US7252240B1 (en) * 2000-07-06 2007-08-07 Onspec Electronics, Inc. Memory module which includes a form factor connector
US7352199B2 (en) * 2001-02-20 2008-04-01 Sandisk Corporation Memory card with enhanced testability and methods of making and using the same
US20030090879A1 (en) * 2001-06-14 2003-05-15 Doblar Drew G. Dual inline memory module
US6661690B2 (en) * 2002-02-19 2003-12-09 High Connection Density, Inc. High capacity memory module with built-in performance enhancing features
US6597062B1 (en) * 2002-08-05 2003-07-22 High Connection Density, Inc. Short channel, memory module with stacked printed circuit boards
US8037229B2 (en) * 2002-11-21 2011-10-11 Sandisk Technologies Inc. Combination non-volatile memory and input-output card with direct memory access
US7069370B2 (en) * 2003-01-31 2006-06-27 Toshiba Corporation USB memory storage apparatus with integrated circuit in a connector
US20050021895A1 (en) * 2003-07-23 2005-01-27 Son Chang-Il Removable memory cards including USB and other controllers, connectors, and methods of operating same
US7535718B2 (en) * 2003-08-20 2009-05-19 Imation Corp. Memory card compatible with multiple connector standards
US7352601B1 (en) * 2003-11-24 2008-04-01 Michael Paul Minneman USB flash memory device
US20070263365A1 (en) * 2004-06-18 2007-11-15 Hiroyuki Yamada Ic Card
US7423885B2 (en) * 2004-09-03 2008-09-09 Entorian Technologies, Lp Die module system
US7324352B2 (en) * 2004-09-03 2008-01-29 Staktek Group L.P. High capacity thin module system and method
US7389937B2 (en) * 2004-12-15 2008-06-24 Kabushiki Kaisha Toshiba Card-shaped memory device incorporating IC card function
US20080080255A1 (en) * 2006-09-29 2008-04-03 Yishai Kagan Dual Voltage Flash Memory Card
US8097939B2 (en) * 2007-12-26 2012-01-17 Kabushiki Kaisha Toshiba Semiconductor memory card
US20090210616A1 (en) * 2008-02-12 2009-08-20 Vijay Karamcheti Memory modules for two-dimensional main memory
US20110019370A1 (en) * 2009-07-27 2011-01-27 Gainteam Holdings Limited Flexible circuit module
US8259483B1 (en) * 2009-12-30 2012-09-04 Mark Ayers Non-volatile memory module
US20150094875A1 (en) * 2013-09-30 2015-04-02 Yacov Duzly Temperature-Controlled Storage Module that Cools Memory Prior to a Data Burst

Also Published As

Publication number Publication date
US9173293B2 (en) 2015-10-27
TWI482153B (en) 2015-04-21
US20120210049A1 (en) 2012-08-16
JP2011048756A (en) 2011-03-10
WO2011025060A1 (en) 2011-03-03
TW201117208A (en) 2011-05-16

Similar Documents

Publication Publication Date Title
US7806324B1 (en) Methods of making and using memory card with enhanced testability
JP4726640B2 (en) Semiconductor device
US7894230B2 (en) Stacked semiconductor devices including a master device
US9218895B2 (en) Memory card test interface
US7541680B2 (en) Semiconductor device package
US8817511B2 (en) PCB circuit modification from multiple to individual chip enable signals
US20110042467A1 (en) Semiconductor memory device and semiconductor memory card
JP2006318634A (en) Stacked semiconductor memory device
US20140264904A1 (en) Unified pcb design for ssd applications, various density configurations, and direct nand access
CN100490609C (en) Assembly and electric package
US20150380062A1 (en) Memory module and video camera
US10396001B2 (en) Offset test pads for WLCSP final test
US8586983B2 (en) Semiconductor chip embedded with a test circuit
US8159244B2 (en) Method and system for testing a semiconductor package
KR20250028784A (en) Semiconductor package
US7901957B2 (en) Disguising test pads in a semiconductor package
JP2006351664A (en) Semiconductor device
US20240407180A1 (en) Single package data storage device
US6922190B2 (en) Portable information terminal
US20240040700A1 (en) Semiconductor storage device
US8228746B2 (en) Semiconductor memory apparatus
US20240055335A1 (en) Semiconductor package
KR100665843B1 (en) Pad Arrangement Structure and Method in Semiconductor Device
KR20170042450A (en) Semiconductor device
JPH10303253A (en) Memory system

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION