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US20100276764A1 - Semiconductor structure with selectively deposited tungsten film and method for making the same - Google Patents

Semiconductor structure with selectively deposited tungsten film and method for making the same Download PDF

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Publication number
US20100276764A1
US20100276764A1 US12/434,688 US43468809A US2010276764A1 US 20100276764 A1 US20100276764 A1 US 20100276764A1 US 43468809 A US43468809 A US 43468809A US 2010276764 A1 US2010276764 A1 US 2010276764A1
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Prior art keywords
semiconductor structure
layer
conductor pattern
dielectric layer
structure according
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Abandoned
Application number
US12/434,688
Inventor
Yi-Jen Lo
Yu-Shan Chiu
Kuo-Hui Su
Chiang-Hung Lin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanya Technology Corp
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Nanya Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanya Technology Corp filed Critical Nanya Technology Corp
Priority to US12/434,688 priority Critical patent/US20100276764A1/en
Assigned to NANYA TECHNOLOGY CORP. reassignment NANYA TECHNOLOGY CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHIU, YU-SHAN, LIN, CHIANG-HUNG, LO, YI-JEN, SU, KUO-HUI
Priority to TW98120620A priority patent/TWI471938B/en
Priority to CN2009101517298A priority patent/CN101882610B/en
Priority to US12/815,407 priority patent/US8003528B2/en
Publication of US20100276764A1 publication Critical patent/US20100276764A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/671—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor having lateral variation in doping or structure
    • H10D64/01316—
    • H10D64/01318—
    • H10D64/01322—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H10P14/432—
    • H10W20/039—
    • H10W20/425—

Definitions

  • the present invention relates generally to semiconductor technology and, more particularly, to a semiconductor structure, e.g. a metal gate or a word line of a vertical-channel transistor, and a method for making the same.
  • a semiconductor structure e.g. a metal gate or a word line of a vertical-channel transistor
  • Selective deposition methods such as selective chemical vapor deposition (CVD) processes are known in the art.
  • Selective deposition may be used to deposit materials on selected surfaces of structures in the manufacture of integrated circuits, and thus obviates the need for associated lithography, etching, and resist removal steps.
  • Selective CVD processes are advantageous because they allow for self-alignment with respect to various structures, thus allowing for relatively tight design rules.
  • the prior art selective deposition methods still have some drawbacks.
  • the prior art selective deposition methods are often used to grow tungsten layer in a contact hole. Prior to the deposition or growth of the tungsten in the contact hole, a series of cleaning steps are required to ensure the silicon surface cleanness. If Reactive Ion Etching (RIE) damage layer exists on the bottom of the contact hole, the metal film formed by the selective CVD process does not grow because the RIE damage layer may work as an insulating film. Therefore, the RIE damage layer needs to be removed before growth of the metal film.
  • RIE Reactive Ion Etching
  • the prior art selective deposition methods are apparently not able to provide a selectively deposited layer such as tungsten layer, which is not only a conformal, ultra-thin (below 15 nm) film but structurally continuous, on a metallic, non-silicon base layer. Also, it is difficult to maintain sufficiently high selectivity between dielectric layer and metal base layer and to deposit such conformal, ultra-thin film at the same time.
  • a semiconductor structure includes a substrate; a dielectric layer overlying the substrate; a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and a conformal metal layer selectively deposited on the top surface and sidewalls, but without deposited on the main surface of the dielectric layer substantially.
  • a method for forming a semiconductor structure includes providing a substrate; forming a dielectric layer on the substrate; forming a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and performing a selective atomic layer deposition (ALD) process to selectively deposit a conformal metal layer onto the top surface and sidewalls of the conductor pattern, but without depositing onto the main surface of the dielectric layer substantially.
  • ALD selective atomic layer deposition
  • FIG. 1 is a schematic, cross-sectional diagram illustrating a semiconductor structure of an integrated circuit in accordance with one preferred embodiment of this invention.
  • FIG. 2 is a flow diagram of a method for making a semiconductor structure of FIG. 1 in accordance with the preferred embodiment of this invention.
  • FIG. 1 is a schematic, cross-sectional diagram illustrating a semiconductor structure of an integrated circuit in accordance with one preferred embodiment of this invention.
  • the semiconductor structure 1 comprises a semiconductor substrate 10 such as silicon substrate, a dielectric layer 12 on the semiconductor substrate 10 , a conductor pattern 14 formed on a main surface 12 a of the dielectric layer 12 , and an ultra-thin metal layer 16 selectively deposited on a top surface 14 a and sidewalls 14 b of the conductor pattern 14 .
  • the metal layer 16 is not deposited or grown directly on the main surface 12 a of the dielectric layer 12 .
  • the semiconductor structure 1 may be a metal-gated transistor device and the dielectric layer 12 is a gate dielectric layer or gate oxide layer of the metal-gated transistor device.
  • This invention is particularly suited for a metal-gated vertical-channel transistor device.
  • Such vertical-channel transistor device may be used in advanced dynamic random access memory (DRAM) technology, wherein the metal layer 16 is capable of reducing the resistance of the word lines. Further, it is often required that the metal layer 16 is ultra thin (below 15 nm) and is a continuous and conformal layer for the concern of work function of the metal-gated transistor device.
  • DRAM dynamic random access memory
  • the dielectric layer 12 comprises silicon oxide, silicon nitride or silicon oxy-nitride.
  • the conductor pattern 14 comprises titanium, titanium nitride, tantalum, tantalum nitride, aluminum, copper, gold, tungsten, silicide or any combination thereof.
  • the conductor pattern 14 is made of titanium nitride and the metal layer 16 is an atomic layer deposited tungsten layer having a thickness of less than 15 nanometers.
  • the conductor pattern 14 which may be part of a metal gate or word line, has a thickness of less than 15 nanometers, more preferably, in a range of about 6-8 nanometers.
  • FIG. 2 is a flow diagram of a method 20 for making a semiconductor structure of FIG. 1 in accordance with the preferred embodiment of this invention.
  • a semiconductor substrate such as the substrate 10 depicted in FIG. 1 is provided.
  • a dielectric layer such as the dielectric layer 12 depicted in FIG. 1 is thermally grown on the semiconductor substrate.
  • the dielectric layer comprises silicon oxide, silicon nitride or silicon oxy-nitride.
  • a metal pattern such as the conductor pattern 14 depicted in FIG. 1 is formed on the main surface of the dielectric layer.
  • the metal pattern comprises titanium, titanium nitride, tantalum, tantalum nitride, aluminum, copper, gold, tungsten, silicide or any combination thereof.
  • the metal pattern is titanium nitride and the metal pattern is defined by wet etching methods.
  • a metal layer such as a titanium nitride layer is capped with a mask layer such as a polysilicon layer.
  • the mask layer only mask a top surface of the metal layer but exposes sidewalls of the metal layer.
  • a wet etching process is then carried out to etch the sidewalls of the metal layer to define the metal pattern.
  • the mask layer is then removed to expose the top surface of the metal pattern.
  • a selective tungsten atomic layer deposition process is carried out to grow a conformal, ultra-thin tungsten layer such as the metal layer 16 depicted in FIG. 1 on the metal pattern.
  • the conformal, ultra-thin tungsten layer has a thickness of less than 15 nm and has good step coverage characteristic.
  • the selective tungsten atomic layer deposition process may involve a plurality of ALD cycles to achieve a desired thickness of the tungsten layer on the metal pattern. For the sake of simplicity, merely one of the ALD cycles (Steps 24 - 27 ) is illustrated in the flow diagram in FIG. 2 .
  • the ALD cycle includes: (1) flowing hydrogen-containing substance such as silane or hydrogen gas into a chamber for a period of time to adsorb hydrogen radicals on the main surface of the dielectric layer and on the metal pattern (Step 24 ); (2) pumping down the chamber while stopping all gas flow to selectively remove the hydrogen radicals merely from the main surface of the dielectric layer (Step 25 ); (3) flowing tungsten precursor such as tungsten hexafluoride (WF 6 ) into the chamber at a low pressure (below 5 torr) and low temperature (below 300° C.) to react with the remanent hydrogen radicals adsorbed merely on the metal pattern, thereby selectively depositing a tungsten layer thereto (Step 26 ); and ( 4 ) purging the chamber with inert gas such as argen to remove by-products (Step 27 ). It is understood that the desired thickness of the tungsten layer can be achieved by repeating the ALD cycle (Step 28 ).
  • hydrogen-containing substance such as silane

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  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate; a dielectric layer overlying the substrate; a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and a conformal metal layer selectively deposited on the top surface and sidewalls, but without deposited on the main surface of the dielectric layer substantially.

Description

    BACKGROUND
  • 1. Field of the Invention
  • The present invention relates generally to semiconductor technology and, more particularly, to a semiconductor structure, e.g. a metal gate or a word line of a vertical-channel transistor, and a method for making the same.
  • 2. Description of the Prior Art
  • As circuit integration increases, the need for greater uniformity and process control regarding layer thickness rises. Various technologies have been developed to deposit layers on substrates in a cost-effective manner, while maintaining control over the characteristics of the layer.
  • Selective deposition methods such as selective chemical vapor deposition (CVD) processes are known in the art. Selective deposition may be used to deposit materials on selected surfaces of structures in the manufacture of integrated circuits, and thus obviates the need for associated lithography, etching, and resist removal steps. Selective CVD processes are advantageous because they allow for self-alignment with respect to various structures, thus allowing for relatively tight design rules.
  • However, the prior art selective deposition methods still have some drawbacks. For example, the prior art selective deposition methods are often used to grow tungsten layer in a contact hole. Prior to the deposition or growth of the tungsten in the contact hole, a series of cleaning steps are required to ensure the silicon surface cleanness. If Reactive Ion Etching (RIE) damage layer exists on the bottom of the contact hole, the metal film formed by the selective CVD process does not grow because the RIE damage layer may work as an insulating film. Therefore, the RIE damage layer needs to be removed before growth of the metal film.
  • In addition, the prior art selective deposition methods are apparently not able to provide a selectively deposited layer such as tungsten layer, which is not only a conformal, ultra-thin (below 15 nm) film but structurally continuous, on a metallic, non-silicon base layer. Also, it is difficult to maintain sufficiently high selectivity between dielectric layer and metal base layer and to deposit such conformal, ultra-thin film at the same time.
  • In light of the above, there is a need in this industry to provide an improved semiconductor structure and method for making the same, where a conformal, ultra-thin film is desired and the conformal, ultra-thin film can be selectively deposited on a metallic, non-silicon base layer with high selectivity between dielectric layer and metal base layer. It is also desirable to provide a method for making such conformal, ultra-thin film with higher throughput.
    • SUMMARY OF THE INVENTION
  • It is one objective of this invention to provide an improved semiconductor structure, e.g. a metal gate or a word line of a vertical-channel transistor, and a method for making the same in order to solve the above-mentioned prior art problems.
  • According to one aspect of this invention, a semiconductor structure is provided. The semiconductor structure includes a substrate; a dielectric layer overlying the substrate; a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and a conformal metal layer selectively deposited on the top surface and sidewalls, but without deposited on the main surface of the dielectric layer substantially.
  • According to another aspect of this invention, a method for forming a semiconductor structure is provided. The method includes providing a substrate; forming a dielectric layer on the substrate; forming a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and performing a selective atomic layer deposition (ALD) process to selectively deposit a conformal metal layer onto the top surface and sidewalls of the conductor pattern, but without depositing onto the main surface of the dielectric layer substantially.
  • These and other objectives of the present invention will no doubt come obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic, cross-sectional diagram illustrating a semiconductor structure of an integrated circuit in accordance with one preferred embodiment of this invention.
  • FIG. 2 is a flow diagram of a method for making a semiconductor structure of FIG. 1 in accordance with the preferred embodiment of this invention.
    •  DETAILED DESCRIPTION
  • FIG. 1 is a schematic, cross-sectional diagram illustrating a semiconductor structure of an integrated circuit in accordance with one preferred embodiment of this invention. As shown in FIG. 1, the semiconductor structure 1 comprises a semiconductor substrate 10 such as silicon substrate, a dielectric layer 12 on the semiconductor substrate 10, a conductor pattern 14 formed on a main surface 12 a of the dielectric layer 12, and an ultra-thin metal layer 16 selectively deposited on a top surface 14 a and sidewalls 14 b of the conductor pattern 14. Substantially, the metal layer 16 is not deposited or grown directly on the main surface 12 a of the dielectric layer 12.
  • According to this invention, the semiconductor structure 1 may be a metal-gated transistor device and the dielectric layer 12 is a gate dielectric layer or gate oxide layer of the metal-gated transistor device. This invention is particularly suited for a metal-gated vertical-channel transistor device. Such vertical-channel transistor device may be used in advanced dynamic random access memory (DRAM) technology, wherein the metal layer 16 is capable of reducing the resistance of the word lines. Further, it is often required that the metal layer 16 is ultra thin (below 15 nm) and is a continuous and conformal layer for the concern of work function of the metal-gated transistor device.
  • In accordance with the preferred embodiment of this invention, the dielectric layer 12 comprises silicon oxide, silicon nitride or silicon oxy-nitride. The conductor pattern 14 comprises titanium, titanium nitride, tantalum, tantalum nitride, aluminum, copper, gold, tungsten, silicide or any combination thereof. Preferably, the conductor pattern 14 is made of titanium nitride and the metal layer 16 is an atomic layer deposited tungsten layer having a thickness of less than 15 nanometers. Preferably, the conductor pattern 14, which may be part of a metal gate or word line, has a thickness of less than 15 nanometers, more preferably, in a range of about 6-8 nanometers.
  • Please refer to FIG. 2. FIG. 2 is a flow diagram of a method 20 for making a semiconductor structure of FIG. 1 in accordance with the preferred embodiment of this invention. As shown in FIG. 2, in Step 21, a semiconductor substrate such as the substrate 10 depicted in FIG. 1 is provided. In Step 22, a dielectric layer such as the dielectric layer 12 depicted in FIG. 1 is thermally grown on the semiconductor substrate. The dielectric layer comprises silicon oxide, silicon nitride or silicon oxy-nitride.
  • In Step 23, a metal pattern such as the conductor pattern 14 depicted in FIG. 1 is formed on the main surface of the dielectric layer. The metal pattern comprises titanium, titanium nitride, tantalum, tantalum nitride, aluminum, copper, gold, tungsten, silicide or any combination thereof. Preferably, the metal pattern is titanium nitride and the metal pattern is defined by wet etching methods. For example, a metal layer such as a titanium nitride layer is capped with a mask layer such as a polysilicon layer. The mask layer only mask a top surface of the metal layer but exposes sidewalls of the metal layer. A wet etching process is then carried out to etch the sidewalls of the metal layer to define the metal pattern. The mask layer is then removed to expose the top surface of the metal pattern.
  • After the formation of the metal pattern, a selective tungsten atomic layer deposition process is carried out to grow a conformal, ultra-thin tungsten layer such as the metal layer 16 depicted in FIG. 1 on the metal pattern. According to this invention, the conformal, ultra-thin tungsten layer has a thickness of less than 15 nm and has good step coverage characteristic. The selective tungsten atomic layer deposition process may involve a plurality of ALD cycles to achieve a desired thickness of the tungsten layer on the metal pattern. For the sake of simplicity, merely one of the ALD cycles (Steps 24-27) is illustrated in the flow diagram in FIG. 2.
  • According to the preferred embodiment of this invention, the ALD cycle includes: (1) flowing hydrogen-containing substance such as silane or hydrogen gas into a chamber for a period of time to adsorb hydrogen radicals on the main surface of the dielectric layer and on the metal pattern (Step 24); (2) pumping down the chamber while stopping all gas flow to selectively remove the hydrogen radicals merely from the main surface of the dielectric layer (Step 25); (3) flowing tungsten precursor such as tungsten hexafluoride (WF6) into the chamber at a low pressure (below 5 torr) and low temperature (below 300° C.) to react with the remanent hydrogen radicals adsorbed merely on the metal pattern, thereby selectively depositing a tungsten layer thereto (Step 26); and (4) purging the chamber with inert gas such as argen to remove by-products (Step 27). It is understood that the desired thickness of the tungsten layer can be achieved by repeating the ALD cycle (Step 28).
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.

Claims (11)

1. A semiconductor structure, comprising:
a substrate;
a dielectric layer overlying the substrate;
a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and
a tungsten metal layer encompassing the conductor pattern including the top surface and the sidewalls, while leaving the main surface of the dielectric layer substantially free of the tungsten metal layer.
2. The semiconductor structure according to claim 1 wherein the dielectric layer comprises silicon oxide, silicon nitride or silicon oxy-nitride.
3. The semiconductor structure according to claim 1 wherein the conductor pattern comprises titanium, titanium nitride, tantalum, tantalum nitride, aluminum, copper, gold, tungsten, silicide or any combination thereof.
4. (canceled)
5. The semiconductor structure according to claim 1 wherein the conductor pattern is made of titanium nitride.
6. The semiconductor structure according to claim 5 wherein the metal layer is a tungsten layer.
7. The semiconductor structure according to claim 6 wherein the tungsten layer has a thickness of less than 15 nanometers.
8. The semiconductor structure according to claim 1 wherein the dielectric layer is a gate dielectric layer of a vertical-channel transistor.
9. The semiconductor structure according to claim 8 wherein the conductor pattern is part of a metal gate or a word line.
10. The semiconductor structure according to claim 9 wherein the conductor pattern has a thickness of less than 15 nanometers.
11. The semiconductor structure according to claim 9 wherein the conductor pattern has a thickness of about 6-8 nanometers.
US12/434,688 2009-05-04 2009-05-04 Semiconductor structure with selectively deposited tungsten film and method for making the same Abandoned US20100276764A1 (en)

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US12/434,688 US20100276764A1 (en) 2009-05-04 2009-05-04 Semiconductor structure with selectively deposited tungsten film and method for making the same
TW98120620A TWI471938B (en) 2009-05-04 2009-06-19 Method of fabricating a semiconductor structure
CN2009101517298A CN101882610B (en) 2009-05-04 2009-07-13 Semiconductor structure and manufacturing method thereof
US12/815,407 US8003528B2 (en) 2009-05-04 2010-06-15 Semiconductor structure and method for making the same

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US20200006274A1 (en) * 2018-06-29 2020-01-02 Powertech Technology Inc. Semiconductor package and manufacturing method thereof

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CN101882610B (en) 2012-01-18
US8003528B2 (en) 2011-08-23

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