[go: up one dir, main page]

US20050184338A1 - High voltage LDMOS transistor having an isolated structure - Google Patents

High voltage LDMOS transistor having an isolated structure Download PDF

Info

Publication number
US20050184338A1
US20050184338A1 US10/786,703 US78670304A US2005184338A1 US 20050184338 A1 US20050184338 A1 US 20050184338A1 US 78670304 A US78670304 A US 78670304A US 2005184338 A1 US2005184338 A1 US 2005184338A1
Authority
US
United States
Prior art keywords
region
diffusion region
drain
source
well
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US10/786,703
Other versions
US6995428B2 (en
Inventor
Chih-Feng Huang
Ta-Yung Yang
Jenn-yu Lin
Tuo-Hsin Chien
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Components Industries LLC
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Assigned to SYSTEM GENERAL CORP. reassignment SYSTEM GENERAL CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHIEN, TUO-HSIN, HUANG, CHIH-FENG, LIN, JENN-YU, YANG, TA-YUNG
Priority to US10/786,703 priority Critical patent/US6995428B2/en
Priority to PCT/CN2004/000731 priority patent/WO2005081321A1/en
Priority to CNA2004800259330A priority patent/CN1849710A/en
Priority to TW093123257A priority patent/TWI235492B/en
Priority to CNB2004100551833A priority patent/CN100388504C/en
Publication of US20050184338A1 publication Critical patent/US20050184338A1/en
Publication of US6995428B2 publication Critical patent/US6995428B2/en
Application granted granted Critical
Assigned to FAIRCHILD (TAIWAN) CORPORATION reassignment FAIRCHILD (TAIWAN) CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: SYSTEM GENERAL CORP.
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC reassignment SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FAIRCHILD (TAIWAN) CORPORATION (FORMERLY SYSTEM GENERAL CORPORATION)
Assigned to DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT reassignment DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT PATENT SECURITY AGREEMENT Assignors: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Assigned to FAIRCHILD SEMICONDUCTOR CORPORATION, SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC reassignment FAIRCHILD SEMICONDUCTOR CORPORATION RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT RECORDED AT REEL 046410, FRAME 0933 Assignors: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/159—Shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform

Definitions

  • the present invention relates to semiconductor devices, and more particularly to a lateral power MOSFET.
  • the development of single chip processes for integrating power switches with control circuitry is a major trend in the field of power IC development.
  • the LDMOS (lateral double diffusion MOS) process in particular is currently being applied to manufacture monolithic ICs.
  • the LDMOS process involves performing planar diffusion on the surface of a semiconductor substrate to form a main current path oriented in the lateral direction. Since the lateral MOSFET is manufactured using a typical IC process, the control circuit and the lateral power MOSFET can be integrated onto a monolithic power IC.
  • FIG. 1 shows a block diagram of a power converter.
  • a transformer 200 is the load of a monolithic power IC 500 .
  • a LDMOS transistor 100 having a drain electrode 10 , a source electrode 20 and a polysilicon gate electrode 40 is used to switch the transformer 200 .
  • a resistor 400 is utilized to sense a switching current Is of the LDMOS transistor 100 for power control.
  • a controller 300 generates a control signal to drive the LDMOS transistor 100 for power conversion. In order to reduce the cost and optimize switching performance, the controller 300 and the LDMOS transistor 100 are implemented on the same substrate.
  • the LDMOS process employing a reduced surface electric field (RESURF) technique using low thickness of EPI or N-well can achieve a high voltage with low on-resistance.
  • RESURF reduced surface electric field
  • LDMOS transistors have been proposed by Klas H. Eklund, in U.S. Pat. No. 4,811,075 entitled “High Voltage MOS Transistors”; by Vladimir Rumennik and Robert W. Busse, in U.S. Pat. No. 5,258,636 entitled “Narrow Radius Tips for High Voltage Semiconductor Devices with Interdigitated Source and Drain Electrodes”;
  • the drawback of theses prior arts are that aforementioned LDMOS transistor have higher on-resistance.
  • High voltage and low on-resistance LDMOS transistor, for example, are proposed by Klas H. Eklind, in U.S. Pat. No.
  • the present invention proposes a LDMOS structure to achieve a high breakdown voltage, low on-resistance and isolated transistor for the monolithic integration.
  • An isolated high voltage LDMOS transistor includes a P-substrate.
  • the LDMOS transistor also includes a first diffusion region and a second diffusion region having N conductivity-type ions to form an N-well in the P-substrate.
  • the first diffusion region further comprises an extended drain region.
  • a drain diffusion region having N+ conductivity-type ions forms a drain region.
  • the drain region is formed in the extended drain region.
  • a third diffusion region containing P conductivity-type ions forms a P-field and a plurality of divided P-fields located in the extended drain region. The divided P-fields are located nearer to the drain region than the P-field.
  • a source diffusion region having N+ conductivity-type ions forms a source region.
  • a contact diffusion region containing P+conductivity-type ions forms a contact region.
  • a fourth diffusion region containing P conductivity-type ions forms an isolated P-well for preventing from breakdown.
  • the isolated P-well located in the second diffusion region encloses the source region and the contact region.
  • the P-field and the divided P-fields located in the extended drain region of the N-well form junction-fields in the N-well to deplete a drift region.
  • a channel is thus developed between the source region and the drain region extending through the N-well.
  • the divided P-fields reduce the on-resistance of the channel.
  • a polysilicon gate electrode is disposed above the channel to control a current flow in the channel. Furthermore, the portion of the N-well generated by the second diffusion region provides a low-impedance path for the source region to restrict the current flow in between the drain region and the source region.
  • FIG. 1 shows a block schematic of a power converter.
  • FIG. 2 is a cross-sectional view of a LDMOS transistor according to a preferred embodiment of the present invention.
  • FIG. 3 shows a top view of the LDMOS transistor shown in FIG. 2 .
  • FIG. 4 shows the electrical field distribution when a 650V voltage is applied to a drain region of the LDMOS transistor according to a preferred embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of an LDMOS transistor 100 .
  • the LDMOS transistor 100 includes a P-substrate 90 .
  • the LDMOS transistor 100 further includes a first diffusion region 33 and a second diffusion region 37 containing N conductivity-type ions to form an N-well 30 in the P-substrate 90 .
  • the first diffusion region 33 further comprises an extended drain region 50 .
  • a drain diffusion region 53 having N+ conductivity-type ions in the N-well 30 formed by the first diffusion region 33 develops a drain region 52 in the extended drain region 50 .
  • a third diffusion region containing P conductivity-type ions forms a P-field 60 , divided P-fields 61 and 62 located in the extended drain region 50 .
  • the divided P-fields 61 and 62 are nearer to the drain region 52 than the P-field 60 .
  • a source diffusion region 55 having N+ conductivity-type ions in the N-well 30 formed by the second diffusion region 37 develops a source region 56 .
  • a contact diffusion region 57 containing P+ conductivity-type ions in the N-well 30 formed by the second diffusion region 37 develops a contact region 58 .
  • a fourth diffusion region 67 containing P conductivity-type ions in the N-well 30 formed by the second diffusion region 37 develops an isolated P-well 65 for preventing from breakdown.
  • the isolated P-well 65 encloses the source region 56 and the contact region 58 .
  • the P-field 60 , the divided P-fields 61 and 62 form junction-fields in the N-well 30 to deplete a drift region.
  • a channel is developed between the source region 56 and the drain region 52 extending through the N-well 30 .
  • the divided P-fields 61 and 62 are further capable of reducing the on-resistance of the channel.
  • a thin gate oxide 81 and a thick field oxide 87 are formed over the P-substrate 90 .
  • a polysilicon gate electrode 40 is disposed above the portion of the gate oxide 81 and the field oxide 87 to control a current flow in the channel.
  • a drain-gap 71 is formed between the drain diffusion region 53 and the field oxide 87 to maintain a space between the drain diffusion region 53 and the field oxide 87 .
  • a source-gap 72 is formed between the field oxide 87 and the isolated P-well 65 to maintain a space between the field oxide 87 and the isolated P-well 65 .
  • Proper placement of the drain-gap 71 and the source-gap 72 can substantially increase the breakdown voltage of the LDMOS transistor 100 .
  • the drain-gap 71 can further reduce the on-resistance of the channel.
  • Insulation layers 85 and 86 cover the polysilicon gate 40 , the field oxide 87 and a field oxide 88 .
  • the insulation layers 85 and 86 are, for example, made of silicon dioxide.
  • a drain metal contact 15 is a metal electrode for contacting with the drain diffusion region 53 .
  • a source metal contact 25 is a metal electrode for contacting with the source diffusion region 55 and the contact diffusion region 57 .
  • FIG. 3 is a top view of proposed LDMOS transistor 100 shown in FIG. 2 .
  • the LDMOS transistor 100 includes a drain electrode 10 , a source electrode 20 , the polysilicon gate electrode 40 , a bonding pad 12 for the drain electrode 10 , a bonding pad 22 for the source electrode 20 , a bonding pad 42 for the polysilicon gate electrode 40 .
  • the extended drain region 50 and the drain diffusion region 53 forms the drain electrode 10 .
  • the isolated P-well 65 , the source diffusion region 55 and the contact diffusion region 57 form the source electrode 20 .
  • the bonding pad 12 is connected to the drain metal contact 15 for the drain electrode 10 .
  • the bonding pad 22 is connected to the source metal contact 25 for the source electrode 20 .
  • the bonding pad 42 is connected to the polysilicon gate electrode 40 .
  • the N-well 30 beneath the P-field 60 and divided P-fields 61 and 62 are connected from the drain electrode 10 to the source electrode 20 .
  • the portion of the N-well 30 in between the divided P-fields 61 and 62 reduces the on-resistance of the channel.
  • the P-field 60 and the divided P-fields 61 and 62 located in the -extended drain region 50 form a junction-field in the N-well 30 .
  • the N-well 30 , the P-field 60 , and the divided P-fields 61 and 62 deplete the drift region, which build the electrical field in the N-well 30 and help to increase the breakdown voltage.
  • the extended drain region 50 In order to get a high breakdown voltage the extended drain region 50 must be fully depleted before breakdown occurs.
  • the N-well 30 , P-fields 60 , and divided P-fields 61 and 62 enable the extended drain region 50 to be depleted before breakdown occurs even though the doping density of the drift region is high. This allows the drift region to have higher doping density and accomplish low resistance.
  • FIG. 4 shows the electrical field distribution when a 650 V voltage is applied to the drain region 52 of the LDMOS transistor 100 .
  • the bold dotted lines respectively indicate the potential voltages of 0V, 100V, 200V, 300V, 400V, 500V, 550V, 600V and 650V.
  • the portion of the N-well 30 generated by the second diffusion region 37 provides a low-impedance path for the source region 56 , which restricts the transistor current flow from flowing in between the drain region 52 and the source region 56 .
  • the LDMOS transistor 100 of the present invention uses a simple structure to implement high breakdown voltage, low on-resistance and isolated performance. Furthermore, the cost is reduced and the production yield can be greatly raised.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A high voltage LDMOS transistor according to the present invention includes a P-field and divided P-fields in an extended drain region of a N-well. The P-field and divided P-fields form junction-fields in the N-well, in which a drift region is fully depleted before breakdown occurs. Therefore, a higher breakdown voltage is achieved and a higher doping density of the N-well is allowed. Higher doping density can effectively reduce the on-resistance of the LDMOS transistor. Furthermore, the N-well generated beneath a source diffusion region provides a low-impedance path for a source region, which restrict the transistor current flow in between a drain region and a source region.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of Invention
  • The present invention relates to semiconductor devices, and more particularly to a lateral power MOSFET.
  • 2. Description of Related Art
  • The development of single chip processes for integrating power switches with control circuitry is a major trend in the field of power IC development. The LDMOS (lateral double diffusion MOS) process in particular is currently being applied to manufacture monolithic ICs. The LDMOS process involves performing planar diffusion on the surface of a semiconductor substrate to form a main current path oriented in the lateral direction. Since the lateral MOSFET is manufactured using a typical IC process, the control circuit and the lateral power MOSFET can be integrated onto a monolithic power IC.
  • FIG. 1 shows a block diagram of a power converter. A transformer 200 is the load of a monolithic power IC 500. A LDMOS transistor 100 having a drain electrode 10, a source electrode 20 and a polysilicon gate electrode 40 is used to switch the transformer 200. A resistor 400 is utilized to sense a switching current Is of the LDMOS transistor 100 for power control. A controller 300 generates a control signal to drive the LDMOS transistor 100 for power conversion. In order to reduce the cost and optimize switching performance, the controller 300 and the LDMOS transistor 100 are implemented on the same substrate. The LDMOS process employing a reduced surface electric field (RESURF) technique using low thickness of EPI or N-well can achieve a high voltage with low on-resistance.
  • Recently, development of high-voltage LDMOS transistors have been proposed by Klas H. Eklund, in U.S. Pat. No. 4,811,075 entitled “High Voltage MOS Transistors”; by Vladimir Rumennik and Robert W. Busse, in U.S. Pat. No. 5,258,636 entitled “Narrow Radius Tips for High Voltage Semiconductor Devices with Interdigitated Source and Drain Electrodes”; However, the drawback of theses prior arts are that aforementioned LDMOS transistor have higher on-resistance. High voltage and low on-resistance LDMOS transistor, for example, are proposed by Klas H. Eklind, in U.S. Pat. No. 5,313,082 entitled “High Voltage MOS Transistor with a Low On-Resistance”; by Gen Tada, Akio Kitamura, Masaru Saito, and Naoto Fujishima, in U.S. Pat. No. 6,525,390 B2 entitled “MIS Semicondiictor Device with Low On Resistance and High Breakdown Voltage”; by Vladimir Rumennik, Donald R. Disney, and Janardhanan S. Ajit, in U.S. Pat. No. 6,570,219 B1 entitled “High-voltage Transistor with Multi-layer Conductor Region”; by Masaaki Noda, in U.S. Pat. No. 6,617,652 B2 entitled “High Breakdown Voltage Semiconductor Device”. Although a high voltage and low on-resistance LDMOS transistor can be manufactured, the complexity of the production processes increases the production cost and/or reduces the production yield. Another disadvantage of these proposed transistors is none-isolated source structure. A none-isolated transistor current could flow around the substrate. This may generate noise interference in the control circuit 300. Besides, the switching current Is of the LDMOS transistor 100 can generate a ground bounce to disturb the control circuit 300. Furthermore, only an isolated LDMOS transistor can restrict the current flow. Therefore the switching current Is through the resistor 400 can be accurately measured. In order to solve these problems, the present invention proposes a LDMOS structure to achieve a high breakdown voltage, low on-resistance and isolated transistor for the monolithic integration.
    • SUMMARY OF THE INVENTION
  • An isolated high voltage LDMOS transistor according to the present invention includes a P-substrate. The LDMOS transistor also includes a first diffusion region and a second diffusion region having N conductivity-type ions to form an N-well in the P-substrate. The first diffusion region further comprises an extended drain region. A drain diffusion region having N+ conductivity-type ions forms a drain region. The drain region is formed in the extended drain region. A third diffusion region containing P conductivity-type ions forms a P-field and a plurality of divided P-fields located in the extended drain region. The divided P-fields are located nearer to the drain region than the P-field. A source diffusion region having N+ conductivity-type ions forms a source region. A contact diffusion region containing P+conductivity-type ions forms a contact region. A fourth diffusion region containing P conductivity-type ions forms an isolated P-well for preventing from breakdown. The isolated P-well located in the second diffusion region encloses the source region and the contact region. The P-field and the divided P-fields located in the extended drain region of the N-well form junction-fields in the N-well to deplete a drift region. A channel is thus developed between the source region and the drain region extending through the N-well. The divided P-fields reduce the on-resistance of the channel. A polysilicon gate electrode is disposed above the channel to control a current flow in the channel. Furthermore, the portion of the N-well generated by the second diffusion region provides a low-impedance path for the source region to restrict the current flow in between the drain region and the source region.
  • It is to be understood that both the foregoing general descriptions and the following detailed descriptions are exemplary, and are intended to provide further explanation of the invention as claimed. Still further objects and advantages will become apparent from a consideration of the ensuing description and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
  • FIG. 1 shows a block schematic of a power converter.
  • FIG. 2 is a cross-sectional view of a LDMOS transistor according to a preferred embodiment of the present invention.
  • FIG. 3 shows a top view of the LDMOS transistor shown in FIG. 2.
  • FIG. 4 shows the electrical field distribution when a 650V voltage is applied to a drain region of the LDMOS transistor according to a preferred embodiment of the present invention.
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • FIG. 2 is a cross-sectional view of an LDMOS transistor 100. The LDMOS transistor 100 includes a P-substrate 90. The LDMOS transistor 100 further includes a first diffusion region 33 and a second diffusion region 37 containing N conductivity-type ions to form an N-well 30 in the P-substrate 90. The first diffusion region 33 further comprises an extended drain region 50. A drain diffusion region 53 having N+ conductivity-type ions in the N-well 30 formed by the first diffusion region 33, develops a drain region 52 in the extended drain region 50. A third diffusion region containing P conductivity-type ions forms a P-field 60, divided P- fields 61 and 62 located in the extended drain region 50. The divided P- fields 61 and 62 are nearer to the drain region 52 than the P-field 60. A source diffusion region 55 having N+ conductivity-type ions in the N-well 30 formed by the second diffusion region 37, develops a source region 56. A contact diffusion region 57 containing P+ conductivity-type ions in the N-well 30 formed by the second diffusion region 37, develops a contact region 58. A fourth diffusion region 67 containing P conductivity-type ions in the N-well 30 formed by the second diffusion region 37, develops an isolated P-well 65 for preventing from breakdown. The isolated P-well 65 encloses the source region 56 and the contact region 58. The P-field 60, the divided P- fields 61 and 62 form junction-fields in the N-well 30 to deplete a drift region.
  • A channel is developed between the source region 56 and the drain region 52 extending through the N-well 30. The divided P- fields 61 and 62 are further capable of reducing the on-resistance of the channel. A thin gate oxide 81 and a thick field oxide 87 are formed over the P-substrate 90. A polysilicon gate electrode 40 is disposed above the portion of the gate oxide 81 and the field oxide 87 to control a current flow in the channel. A drain-gap 71 is formed between the drain diffusion region 53 and the field oxide 87 to maintain a space between the drain diffusion region 53 and the field oxide 87. A source-gap 72 is formed between the field oxide 87 and the isolated P-well 65 to maintain a space between the field oxide 87 and the isolated P-well 65. Proper placement of the drain-gap 71 and the source-gap 72 can substantially increase the breakdown voltage of the LDMOS transistor 100. The drain-gap 71 can further reduce the on-resistance of the channel.
  • Insulation layers 85 and 86 cover the polysilicon gate 40, the field oxide 87 and a field oxide 88. The insulation layers 85 and 86 are, for example, made of silicon dioxide. A drain metal contact 15 is a metal electrode for contacting with the drain diffusion region 53. A source metal contact 25 is a metal electrode for contacting with the source diffusion region 55 and the contact diffusion region 57.
  • FIG. 3 is a top view of proposed LDMOS transistor 100 shown in FIG. 2. The LDMOS transistor 100 includes a drain electrode 10, a source electrode 20, the polysilicon gate electrode 40, a bonding pad 12 for the drain electrode 10, a bonding pad 22 for the source electrode 20, a bonding pad 42 for the polysilicon gate electrode 40.
  • Referring to FIG. 2 and FIG. 3, the extended drain region 50 and the drain diffusion region 53 forms the drain electrode 10. The isolated P-well 65, the source diffusion region 55 and the contact diffusion region 57 form the source electrode 20. The bonding pad 12 is connected to the drain metal contact 15 for the drain electrode 10. The bonding pad 22 is connected to the source metal contact 25 for the source electrode 20. The bonding pad 42 is connected to the polysilicon gate electrode 40. The N-well 30 beneath the P-field 60 and divided P- fields 61 and 62 are connected from the drain electrode 10 to the source electrode 20. The portion of the N-well 30 in between the divided P- fields 61 and 62 reduces the on-resistance of the channel.
  • The P-field 60 and the divided P- fields 61 and 62 located in the -extended drain region 50 form a junction-field in the N-well 30. The N-well 30, the P-field 60, and the divided P- fields 61 and 62 deplete the drift region, which build the electrical field in the N-well 30 and help to increase the breakdown voltage. In order to get a high breakdown voltage the extended drain region 50 must be fully depleted before breakdown occurs. The N-well 30, P-fields 60, and divided P- fields 61 and 62 enable the extended drain region 50 to be depleted before breakdown occurs even though the doping density of the drift region is high. This allows the drift region to have higher doping density and accomplish low resistance.
  • FIG. 4 shows the electrical field distribution when a 650V voltage is applied to the drain region 52 of the LDMOS transistor 100. The bold dotted lines respectively indicate the potential voltages of 0V, 100V, 200V, 300V, 400V, 500V, 550V, 600V and 650V.
  • Furthermore, the portion of the N-well 30 generated by the second diffusion region 37 provides a low-impedance path for the source region 56, which restricts the transistor current flow from flowing in between the drain region 52 and the source region 56.
  • The LDMOS transistor 100 of the present invention uses a simple structure to implement high breakdown voltage, low on-resistance and isolated performance. Furthermore, the cost is reduced and the production yield can be greatly raised.
  • It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims (5)

1. A transistor comprising:
a P-substrate;
a first diffusion region and a second diffusion region formed in said P-substrate; wherein said first diffusion region and said second diffusion containing N conductivity-type ions form an N-well in said P-substrate; wherein said first diffusion region comprises an extended drain region;
a drain diffusion region containing N+conductivity-type ions, forming a drain region in said extended drain region;
a third diffusion region containing P conductivity-type ions, comprising a P-field and divided P-fields formed in said extended drain region; wherein said divided P-fields are located nearer to said drain region compared to said P-field, and wherein said P-field and said divided P-fields generate junction fields;
a fourth diffusion region containing P conductivity-type ions, forming a source region in said N-well formed by said second diffusion region for preventing from breakdown, wherein a left edge of the first diffusion region touches a right edge of the second diffusion region.
a source diffusion region having N+ conductivity-type ions, forming a source region in said P-well formed in said second diffusion region;
a channel, formed between said source region and said drain region;
a polysilicon gate electrode, formed over said channel to control a current flow in said channel; and
a contact diffusion region containing P+ conductivity-type ions, forming a contact region in said P-well formed in said second diffusion region.
2. The transitor of claim 1, wherein said N-well formed by said second diffusion region provides a low-impedence path for said source region and restricts a transistor current flow in between said drain region ans said source region.
3. The tranistor of claim 1, further comprising:
a thin gate oxide layer, formed over said channel;
a thick field oxide, formed laterally adjacent to said thin gate oxide layer;
a drain-gap, formed between said drain diffusion region and said thick field oxide to maintain a space between said drain diffusion region and said thick field oxide;
a source-gap, formed between said thick field oxide and said isolated P-well to maintain a
space between said thick field oxide and said isolated P-well;
an insulation layer, covering said polysilicon gate electrode and said thick field oxide;
a drain metal contact, having a first metal electrode for contacting with said drain diffusion region; and
a source metal contact, having a second metal electrode for contacting with said source diffusion region and said contact diffusion region.
4. The transistor of claim 3, further comprising:
a drain bonding pad, for connecting to said drain metal contact for a drain electrode;
a source bonding pad, for connecting to said source metal contact for a source electrode;
and
a gate bonding pad, for connecting to said polysilicon gate electrode.
5. The transistor of claim 1, wherein said P-field and said divided P-fields form junction-fields in said N-well to deplete a drift region.
US10/786,703 2004-02-24 2004-02-24 High voltage LDMOS transistor having an isolated structure Expired - Lifetime US6995428B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US10/786,703 US6995428B2 (en) 2004-02-24 2004-02-24 High voltage LDMOS transistor having an isolated structure
PCT/CN2004/000731 WO2005081321A1 (en) 2004-02-24 2004-07-02 High voltage ldmos transistor having an isolated structure
CNA2004800259330A CN1849710A (en) 2004-02-24 2004-07-02 High Voltage LDMOS Transistor with an Isolation Structure
TW093123257A TWI235492B (en) 2004-02-24 2004-08-03 High voltage LDMOS transistor having an isolated structure
CNB2004100551833A CN100388504C (en) 2004-02-24 2004-08-12 High voltage LDMOS transistor with isolation structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/786,703 US6995428B2 (en) 2004-02-24 2004-02-24 High voltage LDMOS transistor having an isolated structure

Publications (2)

Publication Number Publication Date
US20050184338A1 true US20050184338A1 (en) 2005-08-25
US6995428B2 US6995428B2 (en) 2006-02-07

Family

ID=34861815

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/786,703 Expired - Lifetime US6995428B2 (en) 2004-02-24 2004-02-24 High voltage LDMOS transistor having an isolated structure

Country Status (4)

Country Link
US (1) US6995428B2 (en)
CN (2) CN1849710A (en)
TW (1) TWI235492B (en)
WO (1) WO2005081321A1 (en)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070262390A1 (en) * 2006-05-10 2007-11-15 Sanyo Electric Co., Ltd. Insulated gate semiconductor device
US20080237631A1 (en) * 2007-03-27 2008-10-02 Atsuo Watanabe High breakdown voltage semiconductor circuit device and method of manufacturing the same
US20090124068A1 (en) * 2004-04-26 2009-05-14 Texas Instruments Incorporated Non-Uniformly Doped High Voltage Drain-Extended Transistor and Method of Manufacture Thereof
US20090321822A1 (en) * 2006-05-05 2009-12-31 Austriamicrosystems Ag High-voltage transistor with improved high stride performance
CN102623509A (en) * 2012-04-19 2012-08-01 成都芯源系统有限公司 High voltage switching device and manufacturing method thereof
US20120280280A1 (en) * 2009-09-07 2012-11-08 Naiqian Zhang Semiconductor device and fabrication method thereof
US8786021B2 (en) * 2012-09-04 2014-07-22 Macronix International Co., Ltd. Semiconductor structure having an active device and method for manufacturing and manipulating the same
KR20150018735A (en) * 2013-08-09 2015-02-24 매그나칩 반도체 유한회사 A semicondcutor device
US20160126350A1 (en) * 2010-04-09 2016-05-05 X-Fab Semiconductor Foundries Ag Ldmos transistors for cmos technologies and an associated production method
US20160293758A1 (en) * 2015-04-03 2016-10-06 Magnachip Semiconductor, Ltd. Semiconductor structure having a junction field effect transistor and a high voltage transistor and method for manufacturing the same
EP3144974A1 (en) * 2015-09-18 2017-03-22 Ampleon Netherlands B.V. Semiconductor device and method of making a semiconductor device
US10084079B2 (en) * 2015-06-16 2018-09-25 Samsung Electronics Co., Ltd. Semiconductor device having a drift region with non-uniform impurity concentration profile
US20190006514A1 (en) * 2016-12-29 2019-01-03 Texas Instruments Incorporated Laterally Diffused Metal Oxide Semiconductor with Gate Poly Contact within Source Window
US20190013403A1 (en) * 2015-04-03 2019-01-10 Magnachip Semiconductor, Ltd. Semiconductor device with high voltage field effect transistor and junction field effect transistor
CN113871456A (en) * 2021-10-09 2021-12-31 上海华虹宏力半导体制造有限公司 LDMOS device and forming method thereof
CN114220841A (en) * 2021-12-13 2022-03-22 上海华虹宏力半导体制造有限公司 An integrated structure for increasing the current of a boost diode integrated in a high voltage loop

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7141860B2 (en) * 2004-06-23 2006-11-28 Freescale Semiconductor, Inc. LDMOS transistor
US7535057B2 (en) * 2005-05-24 2009-05-19 Robert Kuo-Chang Yang DMOS transistor with a poly-filled deep trench for improved performance
US8598659B2 (en) * 2005-10-26 2013-12-03 Hewlett-Packard Development Company, L.P. Single finger gate transistor
CN100438032C (en) * 2006-02-22 2008-11-26 崇贸科技股份有限公司 High voltage and low on-resistance transistor with radiating structure and isolation effect
US7615976B2 (en) 2006-04-19 2009-11-10 System General Corp. Switching circuit of power converter having voltage-clipping device to improve efficiency
US8080848B2 (en) 2006-05-11 2011-12-20 Fairchild Semiconductor Corporation High voltage semiconductor device with lateral series capacitive structure
CN101075790B (en) * 2006-05-15 2010-05-12 崇贸科技股份有限公司 Switching circuit for power converter with voltage clipping device for improved efficiency
CN100454579C (en) * 2006-07-03 2009-01-21 崇贸科技股份有限公司 Self-driven LDMOS transistor
US8247870B2 (en) * 2006-09-26 2012-08-21 O2Micro, Inc. Power MOSFET integration
US20080296636A1 (en) * 2007-05-31 2008-12-04 Darwish Mohamed N Devices and integrated circuits including lateral floating capacitively coupled structures
KR101630734B1 (en) 2007-09-21 2016-06-16 페어차일드 세미컨덕터 코포레이션 Power device
US8278712B2 (en) * 2007-09-25 2012-10-02 O2Micro Inc. Power MOSFET integration
US7977715B2 (en) * 2008-03-17 2011-07-12 Fairchild Semiconductor Corporation LDMOS devices with improved architectures
US8193565B2 (en) 2008-04-18 2012-06-05 Fairchild Semiconductor Corporation Multi-level lateral floating coupled capacitor transistor structures
CN101673763B (en) * 2008-09-09 2011-06-22 上海华虹Nec电子有限公司 Ldmos transistor and preparation method thereof
US8482065B2 (en) * 2008-11-25 2013-07-09 Newport Fab, Llc MOS transistor with a reduced on-resistance and area product
KR101578931B1 (en) * 2008-12-05 2015-12-21 주식회사 동부하이텍 Semiconductor device and method of manufacturing semiconductor device
US8174067B2 (en) 2008-12-08 2012-05-08 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
CN102130167B (en) * 2010-01-20 2012-11-07 上海华虹Nec电子有限公司 Double diffused drain metal oxide semiconductor (DDDMOS) device and method for manufacturing same
US8624302B2 (en) * 2010-02-05 2014-01-07 Fairchild Semiconductor Corporation Structure and method for post oxidation silicon trench bottom shaping
CN101834207A (en) * 2010-04-27 2010-09-15 上海北京大学微电子研究院 Double-diffusion metal oxide semiconductor field effect tube structure and manufacturing method thereof
CN101916728B (en) * 2010-07-20 2012-05-30 中国科学院上海微系统与信息技术研究所 Fabrication process of SOI superjunction LDMOS structure that can completely eliminate substrate-assisted depletion effect
CN101916779B (en) * 2010-07-20 2012-10-03 中国科学院上海微系统与信息技术研究所 SOI super junction LDMOS structure capable of completely eliminating substrate-assisted depletion effect
CN102130012B (en) * 2010-12-31 2012-06-27 中国科学院上海微系统与信息技术研究所 LDD, LDS and buffer layer integrated manufacturing method for SOI super-junction LDMOS device
TWI449159B (en) 2011-04-18 2014-08-11 Episil Technologies Inc Power lateral double diffused MOS device
CN103050512A (en) * 2011-10-13 2013-04-17 上海华虹Nec电子有限公司 Non-epitaxial high-voltage insulating N-type LDMOS (Laterally Diffused Metal Oxide Semiconductor) device structure
US8872278B2 (en) 2011-10-25 2014-10-28 Fairchild Semiconductor Corporation Integrated gate runner and field implant termination for trench devices
CN103123929B (en) * 2011-11-21 2015-10-14 上海华虹宏力半导体制造有限公司 The domain structure of the high withstand voltage field effect transistor of isolated form
CN103633083B (en) * 2012-08-15 2016-06-08 上海华虹宏力半导体制造有限公司 Form the domain structure of the resistance to compressive resistance of superelevation
CN103681777B (en) * 2012-08-31 2016-11-02 上海华虹宏力半导体制造有限公司 Junction Field Effect Transistor
US9059278B2 (en) 2013-08-06 2015-06-16 International Business Machines Corporation High voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) having a deep fully depleted drain drift region
CN105097924A (en) * 2014-05-22 2015-11-25 上海北京大学微电子研究院 Power device structure
US9460926B2 (en) 2014-06-30 2016-10-04 Alpha And Omega Semiconductor Incorporated Forming JFET and LDMOS transistor in monolithic power integrated circuit using deep diffusion regions
CN104201207A (en) * 2014-09-16 2014-12-10 电子科技大学 High-voltage MOS (metal oxide semiconductor) device with adaptive bias field plates
KR102164721B1 (en) 2014-11-19 2020-10-13 삼성전자 주식회사 Semiconductor device
US10627442B2 (en) * 2017-12-07 2020-04-21 Nanya Technology Corporation Method for estimating resistances of a source contact and a drain contact of a MOS transistor
TWI659539B (en) * 2018-06-28 2019-05-11 立錡科技股份有限公司 High voltage component and method of manufacturing same
TWI748239B (en) * 2019-08-30 2021-12-01 新唐科技股份有限公司 High voltage integrated circuit and semiconductor structure thereof
CN112993021B (en) * 2019-12-18 2023-07-07 东南大学 Lateral double-diffusion metal oxide semiconductor field effect transistor
CN113078217A (en) * 2020-01-06 2021-07-06 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6448625B1 (en) * 2001-03-16 2002-09-10 Semiconductor Components Industries Llc High voltage metal oxide device with enhanced well region

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW218424B (en) * 1992-05-21 1994-01-01 Philips Nv
JPH07135307A (en) * 1993-06-30 1995-05-23 Shindengen Electric Mfg Co Ltd Semiconductor device
JPH0974190A (en) * 1995-09-06 1997-03-18 Denso Corp Semiconductor device
JP3142057B2 (en) * 1997-11-13 2001-03-07 日本電気株式会社 Semiconductor device, manufacturing method thereof, and driving device
JP2000164876A (en) * 1998-11-27 2000-06-16 Matsushita Electric Works Ltd Semiconductor device and its manufacture
US6211552B1 (en) * 1999-05-27 2001-04-03 Texas Instruments Incorporated Resurf LDMOS device with deep drain region
JP4357127B2 (en) * 2000-03-03 2009-11-04 株式会社東芝 Semiconductor device
KR100360416B1 (en) * 2000-04-12 2002-11-13 페어차일드코리아반도체 주식회사 Power semiconductor device having high breakdown voltage and method for fabricating the same
US6475870B1 (en) * 2001-07-23 2002-11-05 Taiwan Semiconductor Manufacturing Company P-type LDMOS device with buried layer to solve punch-through problems and process for its manufacture

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6448625B1 (en) * 2001-03-16 2002-09-10 Semiconductor Components Industries Llc High voltage metal oxide device with enhanced well region

Cited By (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090124068A1 (en) * 2004-04-26 2009-05-14 Texas Instruments Incorporated Non-Uniformly Doped High Voltage Drain-Extended Transistor and Method of Manufacture Thereof
US7618870B2 (en) * 2004-04-26 2009-11-17 Texas Instruments Incorporated Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof
US20090321822A1 (en) * 2006-05-05 2009-12-31 Austriamicrosystems Ag High-voltage transistor with improved high stride performance
US8212318B2 (en) * 2006-05-05 2012-07-03 Austriamicrosystems Ag High-voltage transistor with improved high stride performance
US7692240B2 (en) * 2006-05-10 2010-04-06 Sanyo Electric Co., Ltd. Insulated gate semiconductor device
US20070262390A1 (en) * 2006-05-10 2007-11-15 Sanyo Electric Co., Ltd. Insulated gate semiconductor device
US20080237631A1 (en) * 2007-03-27 2008-10-02 Atsuo Watanabe High breakdown voltage semiconductor circuit device and method of manufacturing the same
US8134207B2 (en) * 2007-03-27 2012-03-13 Hitachi, Ltd. High breakdown voltage semiconductor circuit device
US8637905B2 (en) * 2009-09-07 2014-01-28 Dynax Semiconductor, Inc. Semiconductor device and fabrication method thereof
US20120280280A1 (en) * 2009-09-07 2012-11-08 Naiqian Zhang Semiconductor device and fabrication method thereof
US20160126350A1 (en) * 2010-04-09 2016-05-05 X-Fab Semiconductor Foundries Ag Ldmos transistors for cmos technologies and an associated production method
CN102623509A (en) * 2012-04-19 2012-08-01 成都芯源系统有限公司 High voltage switching device and manufacturing method thereof
US9054026B2 (en) 2012-09-04 2015-06-09 Macronix International Co., Ltd. Methods for manufacturing and manipulating semiconductor structure having active device
US8786021B2 (en) * 2012-09-04 2014-07-22 Macronix International Co., Ltd. Semiconductor structure having an active device and method for manufacturing and manipulating the same
KR101941295B1 (en) * 2013-08-09 2019-01-23 매그나칩 반도체 유한회사 A semicondcutor device
KR20150018735A (en) * 2013-08-09 2015-02-24 매그나칩 반도체 유한회사 A semicondcutor device
US20160293758A1 (en) * 2015-04-03 2016-10-06 Magnachip Semiconductor, Ltd. Semiconductor structure having a junction field effect transistor and a high voltage transistor and method for manufacturing the same
US9947786B2 (en) * 2015-04-03 2018-04-17 Magnachip Semiconductor, Ltd. Semiconductor structure having a junction field effect transistor and a high voltage transistor and method for manufacturing the same
US20180197991A1 (en) * 2015-04-03 2018-07-12 Magnachip Semiconductor, Ltd. Semiconductor structure having a junction field effect transistor and a high voltage transistor and method for manufacturing the same
US10096707B2 (en) * 2015-04-03 2018-10-09 Magnachip Semiconductor, Ltd. Semiconductor structure having a junction field effect transistor and a high voltage transistor and method for manufacturing the same
US20190013403A1 (en) * 2015-04-03 2019-01-10 Magnachip Semiconductor, Ltd. Semiconductor device with high voltage field effect transistor and junction field effect transistor
US10784372B2 (en) * 2015-04-03 2020-09-22 Magnachip Semiconductor, Ltd. Semiconductor device with high voltage field effect transistor and junction field effect transistor
US10084079B2 (en) * 2015-06-16 2018-09-25 Samsung Electronics Co., Ltd. Semiconductor device having a drift region with non-uniform impurity concentration profile
EP3144974A1 (en) * 2015-09-18 2017-03-22 Ampleon Netherlands B.V. Semiconductor device and method of making a semiconductor device
US20190006514A1 (en) * 2016-12-29 2019-01-03 Texas Instruments Incorporated Laterally Diffused Metal Oxide Semiconductor with Gate Poly Contact within Source Window
US10957774B2 (en) * 2016-12-29 2021-03-23 Texas Instruments Incorporated Laterally diffused metal oxide semiconductor with gate poly contact within source window
US11721738B2 (en) 2016-12-29 2023-08-08 Texas Instmments Incorporated Laterally diffused metal oxide semiconductor with gate poly contact within source window
CN113871456A (en) * 2021-10-09 2021-12-31 上海华虹宏力半导体制造有限公司 LDMOS device and forming method thereof
CN114220841A (en) * 2021-12-13 2022-03-22 上海华虹宏力半导体制造有限公司 An integrated structure for increasing the current of a boost diode integrated in a high voltage loop

Also Published As

Publication number Publication date
WO2005081321A1 (en) 2005-09-01
CN100388504C (en) 2008-05-14
TWI235492B (en) 2005-07-01
CN1661812A (en) 2005-08-31
TW200529429A (en) 2005-09-01
US6995428B2 (en) 2006-02-07
CN1849710A (en) 2006-10-18

Similar Documents

Publication Publication Date Title
US6995428B2 (en) High voltage LDMOS transistor having an isolated structure
US6873011B1 (en) High voltage and low on-resistance LDMOS transistor having equalized capacitance
US6903421B1 (en) Isolated high-voltage LDMOS transistor having a split well structure
CN103329268B (en) Semiconductor device and the method manufacturing it
US9543451B2 (en) High voltage junction field effect transistor
WO2008085795A1 (en) Integrated complementary low voltage rf-ldmos
CN102148251A (en) Semiconductor on insulator (SOI) lateral metal-oxide-semiconductor field-effect-transistor (MOSFET) device and integrated circuit
CN102097474B (en) The low grid electric charge (Silicon-on-insulator) MOSFET lateral of CMOS compatible
CN110176454A (en) Multiple transistor device
US5633525A (en) Lateral field effect transistor
US10269951B2 (en) Semiconductor device layout and method for forming same
US5889310A (en) Semiconductor device with high breakdown voltage island region
US20120126314A1 (en) Vertical dmos-field effect transistor
US20180076201A1 (en) Semiconductor device
US5874767A (en) Semiconductor device including a lateral power device
KR101505313B1 (en) Semiconductor device and semiconductor integrated circuit device using the same
US20040201078A1 (en) Field plate structure for high voltage devices
US7554157B2 (en) Lateral SOI component having a reduced on resistance
CN105097936A (en) Silicon-on-insulator lateral double-diffused metal-oxide-semiconductor (LDMOS) power device
JP2004031519A (en) Semiconductor device
KR20000059529A (en) High voltage devicd and method for manufacturing the same
EP4184590B1 (en) Semiconductor device
US11916116B2 (en) Semiconductor device
KR100479426B1 (en) High-Voltage Device Structure and It's Fabrication Process
JPH01207977A (en) Semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: SYSTEM GENERAL CORP., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HUANG, CHIH-FENG;YANG, TA-YUNG;LIN, JENN-YU;AND OTHERS;REEL/FRAME:015030/0444

Effective date: 20040202

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAT HOLDER NO LONGER CLAIMS SMALL ENTITY STATUS, ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: STOL); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: FAIRCHILD (TAIWAN) CORPORATION, TAIWAN

Free format text: CHANGE OF NAME;ASSIGNOR:SYSTEM GENERAL CORP.;REEL/FRAME:038906/0030

Effective date: 20140620

AS Assignment

Owner name: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, ARIZONA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FAIRCHILD (TAIWAN) CORPORATION (FORMERLY SYSTEM GENERAL CORPORATION);REEL/FRAME:042328/0318

Effective date: 20161221

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT, NEW YORK

Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC;REEL/FRAME:046410/0933

Effective date: 20170210

Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AG

Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC;REEL/FRAME:046410/0933

Effective date: 20170210

AS Assignment

Owner name: FAIRCHILD SEMICONDUCTOR CORPORATION, ARIZONA

Free format text: RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT RECORDED AT REEL 046410, FRAME 0933;ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:064072/0001

Effective date: 20230622

Owner name: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, ARIZONA

Free format text: RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT RECORDED AT REEL 046410, FRAME 0933;ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:064072/0001

Effective date: 20230622