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US20050136688A1 - Method of inhibiting degradation of gate oxide film - Google Patents

Method of inhibiting degradation of gate oxide film Download PDF

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US20050136688A1
US20050136688A1 US10/878,364 US87836404A US2005136688A1 US 20050136688 A1 US20050136688 A1 US 20050136688A1 US 87836404 A US87836404 A US 87836404A US 2005136688 A1 US2005136688 A1 US 2005136688A1
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oxide film
impurity
gate
gate oxide
hdp
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US10/878,364
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Kyung Yoo
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SK Hynix Inc
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Hynix Semiconductor Inc
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Assigned to HYNIX SENICONDUCTOR INC. reassignment HYNIX SENICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YOO, KYUNG DONG
Publication of US20050136688A1 publication Critical patent/US20050136688A1/en
Priority to US11/293,124 priority Critical patent/US7138324B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

Definitions

  • the present invention generally relates to a method of inhibiting degradation of a transistor gate oxide film due to ultraviolet rays in a High Density Plasma (hereinafter, referred to as “HDP”) process, and more specifically, to a method for effectively preventing ultraviolet rays from permeating a gate insulating oxide film by injecting impurity into the surface of an interlayer insulating film so as to change a surface characteristic of the interlayer insulating film.
  • HDP High Density Plasma
  • a HDP process utilizes high power plasma, which generates ultraviolet rays (UV).
  • the UV is known to have a predetermined wavelength ranging from about 200 to 800 nm.
  • the UV having a wavelength ranging from 200 to 800 nm has an energy ranging from about 5 eV to 1.5 eV If such energy reaches a silicon substrate, an Electron-Hole Pair is formed.
  • the formation of the Electron-Hole Pair is generally occurs when an energy larger than the Band-Gap energy of 1.1 eV in the silicon is injected thereto. The electron is again trapped in a gate oxide film, thereby degrading characteristics of the oxide film.
  • a Plasma Induced Damage (hereinafter, referred to as “PID”) or a Plasma Induced Radiation Damage (hereinafter, referred to as “PIRD”) of the HDP cannot be controlled in the conventional process.
  • a method of inhibiting the use of HDP or reducing power of plasma to reduce the PID has been proposed. However, the method reduces the uniform deposition ability which is an advantage in using HDP, resulting in short circuits in a subsequent process.
  • a method for manufacturing a semiconductor device comprises steps of forming a gate oxide film and a gate electrode on a semiconductor substrate, forming an interlayer oxide film on the semiconductor substrate including the gate electrode, injecting an impurity into a surface of the interlayer oxide film to form a layer for preventing UV (ultraviolet rays) generated by high density plasma from penetrating the interlayer oxide film, and forming a HDP oxide film on the interlayer oxide film.
  • UV ultraviolet
  • the impurity is selected from a group consisting of As, P, B, BF 2 , BF, Si and Ge.
  • a concentration of the impurity ranges from 1 e 17 /cm 3 to 1 e 22 /cm 3 .
  • the impurity is injected to a depth of less than 1000 ⁇ .
  • the step of injecting an impurity is performed immediately after the formation of the interlayer oxide film or prior to the formation of the HDP oxide film, thereby obtaining the effect of the present invention.
  • the surface characteristics of the oxide film are changed so that UV rays generated from the HDP process do not permeate into the gate oxide film deposited on the semiconductor substrate.
  • FIG. 1 is a mimetic diagram illustrating a principle according to an embodiment of the present invention.
  • FIG. 2 is a graph illustrating a measurement result of an antenna test pattern of a gate oxide film according to a conventional process.
  • FIG. 3 is a graph illustrating a measurement result of an antenna test pattern of a gate oxide film according to an embodiment of the present invention.
  • FIG. 1 is a mimetic diagram illustrating a principle according to an embodiment of the present invention.
  • a plurality of gate electrodes 12 having a stacked structure of suicides such as polysilicon and tungsten silicide are formed on a substrate 10 having various elements thereon. Then, a gate oxide film (not shown) is formed at an interface of the substrate 10 and the gate electrode 12 , and a hard mask insulating film 14 is formed on the gate electrode 12 for preventing a damage of the gate electrode in a subsequent self-alignment etching process.
  • a spacer such as a nitride film is formed on a side wall of the gate electrode 12 , and then an oxide film 16 which is an interlayer insulating film is deposited on the resulting structure.
  • the impurity in the oxide film 18 scatters UV rays generated from the HDP process to inhibit the UV from permeating into the oxide film 16 .
  • FIGS. 2 and 3 show graphs illustrating measurement results of antenna test patterns.
  • An antenna Ratio (“A.R”) which refers to a ratio of an area of the gate oxide film to that of gate that receives PID, and test patterns (“Ref”) having no separate antenna gate from 13000 times are shown in FIGS. 2 and 3 .
  • the measurement was done by applying a voltage of 3V to the gate to measure a leakage current flowing into the silicon substrate.
  • the thickness of the gate oxide film is 37 ⁇ , which is a thickness sensitive to PID.
  • the oxide film 16 is deposited by using a low pressure chemical vapor deposition method which does not generate a PID.
  • the leakage current is measured after the deposition of a HDP oxide film on the oxide film 16 and various wiring process for test patterns.
  • the amount of leakage current flowing through the oxide film increases proportional to the antenna ratio.
  • the leakage current of less than 1.0 pA is generated under the Ref condition and an A.R condition of 333 times, and the leakage current of 10 nA is generated under an A.R condition of 13000 times (see FIG. 2 ).
  • leakage current of less than 1.0 pA is generated in all cumulative distribution regardless of A.R in accordance with the present invention (see FIG. 3 ). This is because injected impurity forms a layer for inhibiting UV from permeating into the surface of the insulating oxide film.
  • the degradation phenomenon of the gate oxide film by PID is prevented even in high antenna ratio in accordance with the present invention. Accordingly, yield may be improved in an integrated circuit fabrication process, and degradation of reliability such as HCD (Hot Carrier Degradation) by degradation of the gate oxide film can be prevented.
  • HCD Hot Carrier Degradation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Plasma & Fusion (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method of inhibiting degradation of a transistor gate oxide film by high density plasma is disclosed. After a gate electrode is formed, impurity is injected on the surface of an interlayer insulating film, thereby changing surface characteristics of the interlayer insulating film to scatter ultraviolet rays which are factors of degradation of the interlayer insulating film. Accordingly, the ultraviolet rays are prevented from being permeated into a gate insulating oxide film.

Description

    CORRESPONDING RELATED APPLICATIONS
  • The present invention claims the benefit of and priority to Korean Patent Application No. 10-2003-0095301, filed on Dec. 23, 2003.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention generally relates to a method of inhibiting degradation of a transistor gate oxide film due to ultraviolet rays in a High Density Plasma (hereinafter, referred to as “HDP”) process, and more specifically, to a method for effectively preventing ultraviolet rays from permeating a gate insulating oxide film by injecting impurity into the surface of an interlayer insulating film so as to change a surface characteristic of the interlayer insulating film.
  • 2. Description of the Prior Art
  • A HDP process utilizes high power plasma, which generates ultraviolet rays (UV). The UV is known to have a predetermined wavelength ranging from about 200 to 800 nm. According to the Plank's Law on wavelength of light and its energy, the energy E is proportional to frequency (E=hv; h=Plank's constant, v=frequency of light). Since the frequency v is inversely proportional to the wavelength of light, E becomes larger as the wavelength of light becomes shorter. Accordingly, the UV having a wavelength ranging from 200 to 800 nm has an energy ranging from about 5 eV to 1.5 eV If such energy reaches a silicon substrate, an Electron-Hole Pair is formed. The formation of the Electron-Hole Pair is generally occurs when an energy larger than the Band-Gap energy of 1.1 eV in the silicon is injected thereto. The electron is again trapped in a gate oxide film, thereby degrading characteristics of the oxide film.
  • A Plasma Induced Damage (hereinafter, referred to as “PID”) or a Plasma Induced Radiation Damage (hereinafter, referred to as “PIRD”) of the HDP cannot be controlled in the conventional process. A method of inhibiting the use of HDP or reducing power of plasma to reduce the PID has been proposed. However, the method reduces the uniform deposition ability which is an advantage in using HDP, resulting in short circuits in a subsequent process.
  • Recently, a method of depositing an amorphous silicon film after formation of a transistor has been proposed to inhibit degradation of a gate oxide film by PID or PIRD. In accordance with the method, a formation process of contact for connecting wires cannot be performed by a single etching process. In addition, a possibility of a short circuit between wires by the amorphous silicon film exists.
    • SUMMARY OF THE INVENTION
  • It is an object of the present invention to provide a method of inhibiting degradation of a transistor gate oxide film by HDP.
  • In an embodiment, a method for manufacturing a semiconductor device is provided. The method comprises steps of forming a gate oxide film and a gate electrode on a semiconductor substrate, forming an interlayer oxide film on the semiconductor substrate including the gate electrode, injecting an impurity into a surface of the interlayer oxide film to form a layer for preventing UV (ultraviolet rays) generated by high density plasma from penetrating the interlayer oxide film, and forming a HDP oxide film on the interlayer oxide film.
  • The impurity is selected from a group consisting of As, P, B, BF2, BF, Si and Ge. A concentration of the impurity ranges from 1 e17/cm3 to 1 e22/cm3. The impurity is injected to a depth of less than 1000 Å.
  • The step of injecting an impurity is performed immediately after the formation of the interlayer oxide film or prior to the formation of the HDP oxide film, thereby obtaining the effect of the present invention.
  • According to the method of the present invention, the surface characteristics of the oxide film are changed so that UV rays generated from the HDP process do not permeate into the gate oxide film deposited on the semiconductor substrate.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a mimetic diagram illustrating a principle according to an embodiment of the present invention.
  • FIG. 2 is a graph illustrating a measurement result of an antenna test pattern of a gate oxide film according to a conventional process.
  • FIG. 3 is a graph illustrating a measurement result of an antenna test pattern of a gate oxide film according to an embodiment of the present invention.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The present invention will be described in detail with reference to the accompanying drawings.
  • FIG. 1 is a mimetic diagram illustrating a principle according to an embodiment of the present invention.
  • A plurality of gate electrodes 12 having a stacked structure of suicides such as polysilicon and tungsten silicide are formed on a substrate 10 having various elements thereon. Then, a gate oxide film (not shown) is formed at an interface of the substrate 10 and the gate electrode 12, and a hard mask insulating film 14 is formed on the gate electrode 12 for preventing a damage of the gate electrode in a subsequent self-alignment etching process.
  • Thereafter, a spacer (not shown) such as a nitride film is formed on a side wall of the gate electrode 12, and then an oxide film 16 which is an interlayer insulating film is deposited on the resulting structure.
  • Next, an impurity is injected into a surface of the oxide film 16 to change the chemical state of the surface of the oxide film 16, thereby oxide film 18 having the impurity therein is formed.
  • Here, the impurity in the oxide film 18 scatters UV rays generated from the HDP process to inhibit the UV from permeating into the oxide film 16.
  • In order to compare the effect of the present invention with that of the conventional method, FIGS. 2 and 3 show graphs illustrating measurement results of antenna test patterns. An antenna Ratio (“A.R”) which refers to a ratio of an area of the gate oxide film to that of gate that receives PID, and test patterns (“Ref”) having no separate antenna gate from 13000 times are shown in FIGS. 2 and 3.
  • The measurement was done by applying a voltage of 3V to the gate to measure a leakage current flowing into the silicon substrate. The thickness of the gate oxide film is 37 Å, which is a thickness sensitive to PID. After the formation of the gate electrode, the oxide film 16 is deposited by using a low pressure chemical vapor deposition method which does not generate a PID. The leakage current is measured after the deposition of a HDP oxide film on the oxide film 16 and various wiring process for test patterns.
  • As seen in the measurement results, the amount of leakage current flowing through the oxide film increases proportional to the antenna ratio. In 50% cumulative distribution, the leakage current of less than 1.0 pA is generated under the Ref condition and an A.R condition of 333 times, and the leakage current of 10 nA is generated under an A.R condition of 13000 times (see FIG. 2).
  • Contrary to the conventional method, leakage current of less than 1.0 pA is generated in all cumulative distribution regardless of A.R in accordance with the present invention (see FIG. 3). This is because injected impurity forms a layer for inhibiting UV from permeating into the surface of the insulating oxide film.
  • As discussed earlier, the degradation phenomenon of the gate oxide film by PID is prevented even in high antenna ratio in accordance with the present invention. Accordingly, yield may be improved in an integrated circuit fabrication process, and degradation of reliability such as HCD (Hot Carrier Degradation) by degradation of the gate oxide film can be prevented.

Claims (7)

1. A method for manufacturing a semiconductor device, comprising the steps of:
forming a gate oxide film and a gate electrode on a semiconductor substrate;
forming an interlayer oxide film on the semiconductor substrate including the gate electrode;
injecting an impurity into a surface of the interlayer oxide film to form a layer for preventing UV (Ultraviolet rays) generated by high density plasma from penetrating the interlayer oxide film; and
forming a HDP oxide film on the interlayer oxide film.
2. (canceled)
3. The method according to claim 1, wherein the impurity is selected from a group consisting of As, P, B, BF2, BF, Si and Ge.
4. The method according to claim 1, wherein a concentration of the impurity ranges from 1 e17/cm3 to 1 e22/cm3.
5. (canceled)
6. The method according to claim 1, wherein the step of injecting the impurity is performed immediately after the formation of the interlayer oxide film or prior to the formation of the HDP oxide film.
7. The method according to claim 1, wherein the impurity is injected to a depth of less than 1000 Å.
US10/878,364 2003-12-23 2004-06-29 Method of inhibiting degradation of gate oxide film Abandoned US20050136688A1 (en)

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KR2003-0095301 2003-12-23

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