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US20030155635A1 - Semiconductor device, method for designing the same and recording medium that can be read by computer in which program for designing semiconductor device is recorded - Google Patents

Semiconductor device, method for designing the same and recording medium that can be read by computer in which program for designing semiconductor device is recorded Download PDF

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Publication number
US20030155635A1
US20030155635A1 US10/369,718 US36971803A US2003155635A1 US 20030155635 A1 US20030155635 A1 US 20030155635A1 US 36971803 A US36971803 A US 36971803A US 2003155635 A1 US2003155635 A1 US 2003155635A1
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Prior art keywords
semiconductor chip
semiconductor
internal circuit
conductive pad
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US10/369,718
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English (en)
Inventor
Yasuhiro Ishiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Assigned to MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. reassignment MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ISHIYAMA, YASUHIRO
Publication of US20030155635A1 publication Critical patent/US20030155635A1/en
Priority to US11/412,749 priority Critical patent/US7250686B2/en
Abandoned legal-status Critical Current

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Definitions

  • the present invention relates to a semiconductor device that a plurality of semiconductor chips are integrally structured and in particular to, facilitation of design for the semiconductor device.
  • a semiconductor device with a plurality of semiconductor chips being integrally structured therein is conventionally designed so that pads for the semiconductor chips are connected together by utilizing wire bonding connection or flip chip connection.
  • FIG. 27 is a view showing the structure of a conventional semiconductor device with a plurality of semiconductor chips being integrally structured therein.
  • FIG. 28 is a cross-sectional view taken along a line X-X shown in FIG. 27.
  • a semiconductor device 1000 comprises a semiconductor chip B, a semiconductor chip A which is adhered on the semiconductor chip B with an adhered portion being interposed therebetween and wires 11 , 12 , 13 , 14 , 15 , 16 , 21 , 22 , 23 , 24 , 25 and 26 extended from pads for the semiconductor chips A and B by wire bonding.
  • the wires 13 , 15 , 23 and 25 connect the pads for the chip A to the pad for the chip B.
  • the wires 12 , 14 , 22 and 24 connect the pads for the chip A to electrodes outside the semiconductor device 1000 (e.g., lead frame, electrode pad for printed wiring board and the like).
  • the wires 11 , 16 , 21 and 26 connect the pad for the chip B to external of the semiconductor device 1000 .
  • a maximum distance h from the wire 12 or 22 to the upper surface of the semiconductor chip B is extremely long. Further, portions of the wires 12 and 22 that are not connected to pads are long. For this reason, the wires 12 and 22 are easily bent by an external stress. Consequently, when the wires are provided and then the semiconductor device 1000 is to be worked, the wires 12 and 22 and the wires 11 and 21 may be shorted. As a result, yield rates for products obtained by working the semiconductor device 1000 may be decreased.
  • wires for connecting the semiconductor A to the semiconductor B may have different lengths.
  • wires may have various delay values.
  • the semiconductor chip B does not have marks for fixing the semiconductor A thereon. Thus, when the conventional semiconductor device 1000 is manufactured, it is difficult to adhere the semiconductor chip A on the semiconductor chip B so that the semiconductor chip A is securely fixed on a predetermined position of the semiconductor chip B.
  • the semiconductor chip A is provided with only pads for wire bonding. Thus, the semiconductor chip A is connected to the semiconductor chip B only by wire bonding.
  • EMI Electro Magnetic Interference
  • the present invention was developed in light of the above-described drawbacks and an object of the present invention is to provide a semiconductor device which is easily designed and manufactured and in which a plurality of semiconductor chips are integrally structured.
  • a semiconductor device of the present invention comprises a first semiconductor chip that includes a first internal circuit and at least one first conductive pad which is provided on its upper surface and is not connected to the first internal circuit; a second semiconductor chip provided on the first semiconductor chip that includes a second internal circuit and at least one second conductive pad which is provided on its upper surface and connected to the second internal circuit; at least one first connecting member for connecting the at least one first conductive pad to the at least one second conductive pad; and at least one second connecting member led from the at least one first conductive pad.
  • bent of connecting members occurred in a conventional semiconductor device can be suppressed. Accordingly, when the connecting members are provided and then a semiconductor device is worked, short of the connecting members can be prevented.
  • the at least one first connecting member may contact the point on the at least one first conductive pad which is different from the point the at least one second connecting member contacts.
  • a plurality of the at least one first conductive pads are provided, a plurality of the at least one second conductive pads are provided, a plurality of the at least one first connecting member are provided, a plurality of the at least one second connecting member are provided, and two of the plurality of first connecting members have the same length.
  • a skew generated because of the difference in length between the first connecting members can be reduced.
  • a semiconductor device of the present invention comprises a first semiconductor chip that includes a plurality of first conductive pads provided on its upper surface; a second semiconductor chip that is provided on the first semiconductor chip and includes a plurality of second conductive pads provided on its upper surface; and a plurality of first connecting members for connecting the plurality of first conductive pads to the plurality of second conductive pads, wherein at least one of the plurality of first connecting members has a resistance value per unit length different from those of the other first connecting members.
  • a delay value can be adjusted for each of the first connecting members.
  • At least one of the plurality of first connecting members may be made of a material different from those of the other first connecting members.
  • the number of wires for at least one of the plurality of first connecting members may be different from those of the other first connecting members.
  • a semiconductor device of the present invention comprises a first semiconductor chip; and a second semiconductor chip provided on the first semiconductor chip, wherein fixing means for disposing the second semiconductor chip is provided on the first semiconductor chip.
  • the fixing means may be a first convex portion with which the second semiconductor chip can engage.
  • a second convex portion on which the second semiconductor chip can slide is formed at areas on the first semiconductor chip other than the area that the second semiconductor chip is to be disposed.
  • the second semiconductor chip slides on the second convex portions and is fixed on the area defined by the first convex portions.
  • a semiconductor device of the present invention comprises a first semiconductor chip; and a second semiconductor chip provided on the first semiconductor chip, wherein the first semiconductor chip has a first engagement portion, the second semiconductor chip has a second engagement portion, and the first engagement portion is fitted into the second engagement portion.
  • the second semiconductor chip when being fixed on the first semiconductor chip, the second semiconductor chip is securely fixed on the first semiconductor chip without misalignment.
  • the semiconductor device may further comprise a third semiconductor chip provided on the first semiconductor chip, wherein the third semiconductor chip has a third engagement portion, the first semiconductor chip has a fourth engagement portion, the third engagement is fitted into the fourth engagement portion and the first engagement portion has different configuration from the third engagement portion.
  • a semiconductor device of the present invention comprises a first semiconductor chip; and a second semiconductor chip provided on the first semiconductor chip, wherein a first mark indicating the area the second semiconductor chip is to be disposed is provided on the first semiconductor chip.
  • the semiconductor device may further comprise a third semiconductor chip provided on the first semiconductor chip, wherein a second mark indicating the area the third semiconductor chip is to be disposed is provided on the first semiconductor chip, the first mark is different from the second mark.
  • a semiconductor device of the present invention comprises an internal circuit; a wire bonding conductive pad connected to the internal circuit; and a bump connection pad connected to the internal circuit in parallel with the wire bond conductive pad.
  • connection method for structuring a semiconductor device can be selected.
  • the semiconductor device may comprise a first surface; and a second surface opposing the first surface, wherein the wire bonding conductive pad and the bump connection pad are provided on the first surface.
  • a semiconductor device of the present invention comprises a first semiconductor chip that includes a plurality of first conductive pads provided on it upper surface; a second semiconductor chip provided on the first semiconductor chip that includes a plurality of second conductive pads provided on its upper surface; a plurality of first connecting members for connecting the plurality of first conductive pads to the plurality of second conductive pads; and a plurality of second connecting members led from the plurality of second conductive pads, with a ground potential beings supplied thereto.
  • a method for designing semiconductor device which comprises a first semiconductor chip that includes a first internal circuit, a first conductive pad which is provided on its upper surface and is connected to the first internal circuit and a wire bond island serving as a conductive pad which is provided on its upper surface and is not connected to the first internal circuit; and a second semiconductor chip provided on the first semiconductor chip that includes a second internal circuit and a second conductive pad which is provided on its upper surface and is connected to the second internal circuit, wherein the first conductive pad is connected to the second conductive pad, and the first conductive pad is connected to externals, the method comprising the steps of: (a) determining a connection path which can be connected by wire bonding from the connection relationship between the internal circuits and the externals and the positions of the conductive pads; and (b) calculating, with respect to the connection path, the position of the wire bond island provided on the first semiconductor chip.
  • a method for designing semiconductor device which comprises a first semiconductor chip that includes a first internal circuit, at least one first conductive pad which is provided on its upper surface and is connected to the first internal circuit and at least one wire bond island serving as a conductive pad which is provided on its upper surface and is not connected to the first internal circuit; and a second semiconductor chip provided on the first semiconductor chip that includes a second internal circuit and a second conductive pad which is provided on its upper surface and is connected to the second internal circuit, wherein the at least one first conductive pad is connected to the second conductive pad, and the at least one first conductive pad is connected to externals, the method comprising the steps of: (a) determining whether or not at least one connection path determined from the connection relationship between the internal circuits and the externals and the positions of the at least one first conductive pad and the second conductive pad can be connected by wire bonding; (b) calculating the position of the at least one wire bond island provided on the first semiconductor chip if it is determined in the step (a) that the at least one connection path can
  • a plurality of the at least one first conductive pads are provided, the plurality of at least one connection paths are determined in the step (a), a plurality of the positions of the at least one wire bond islands are obtained in the step (b) or (c), the method preferably further comprises the step of: (d) with respect to two of the plurality of connection paths, changing the positions of the wire bond islands so that the distances between the first conductive pads and the wire bond islands are equal.
  • a semiconductor device that a skew generated at two connection paths by the difference between distances from the first conductive pad to a wire bond island is reduced can be obtained.
  • a method for designing semiconductor device which comprises a first semiconductor chip that includes a first internal circuit and a first conductive pad which is provided on its upper surface and is connected to the first internal circuit; and a second semiconductor chip provided on the first semiconductor chip that includes a second internal circuit and a second conductive pad which is provided on its upper surface and is connected to the second internal circuit, wherein the first conductive pad is connected to the second conductive pad, and the first conductive pad is connected to externals
  • the method comprising the steps of: (a) determining a connection path from the connection relationship between the internal circuits and the externals and the positions of the conductive pads; (b) when the connection path is connected by a connecting member, determining whether or not a delay value of the connection path is within a tolerance; and (c) if it is determined in the step (b) that the delay value of the connection path is not within a tolerance, changing the connecting member so that the delay value of the connection path is within a tolerance.
  • a delay value can be adjusted for each of the connection paths.
  • step (c) materials for the connecting member are changed so that the delay value of the connection path is within a tolerance.
  • step (c) the number of wires structuring the connecting member is changed so that the delay value of the connection path is within a tolerance.
  • a method for designing semiconductor device which comprises a first semiconductor chip and a second semiconductor chip provided on the first semiconductor chip, comprising the steps of: (a) determining the area on the first semiconductor chip that the second semiconductor chip is to be disposed from the arrangement relationship between the first semiconductor chip and the second semiconductor chip and configurations of the first semiconductor chip and second semiconductor chip; and (b) in order to form a first convex portion with which the second semiconductor chip engages, determining the arrangement of the first convex portion on the first semiconductor chip and the configuration of the first convex portion.
  • the method for designing semiconductor device further comprises the step of: (c) in order to form a second convex portion on which the second semiconductor chip can slide, determining the arrangement of the second convex portion on the first semiconductor chip and the configuration of the second convex portion.
  • the second semiconductor chip Even if the second semiconductor chip is disposed at positions other than the area that the second semiconductor chip should be originally disposed when being fixed on the first semiconductor chip, the second semiconductor chip slides on the second convex portions and then is fixed on the area defined by the first convex portions.
  • a method for designing semiconductor device which comprises a first semiconductor chip and at least one second semiconductor chip provided on the first semiconductor chip, comprising the steps of: (a) determining the area on the first semiconductor chip that the at least one second semiconductor chip is to be disposed from the arrangement relationship between the first semiconductor chip and the at least one second semiconductor chip and configurations of the first semiconductor chip and the at least one second semiconductor chip; (b) detecting the number of the at least one second semiconductor chips; (c) if the number of the at least one second semiconductor chips is 1 in the step (b), determining the positions of a first engagement portion on the first semiconductor chip and a second engagement portion on the second semiconductor chip which is fitted into the first engagement portion and the configurations of the first engagement portion and the second engagement portion; and (d) if the number of the at least one second semiconductor chips is a plural number, determining the positions of the first engagement portions on the first semiconductor chip and the second engagement portions on the second semiconductor chips fitted into the first engagement portions and the configurations of the first engagement portions and
  • the second semiconductor chip when fixed on the first semiconductor chip, the second semiconductor chip is securely fixed on the first semiconductor chip without misalignment. If a second semiconductor chip is mistaken for another second semiconductor chip, the respective second semiconductor chips cannot be fixed on the first semiconductor chip. Thus, it is possible to prevent a mistake among a plurality of second semiconductor chips.
  • a method for designing semiconductor device which comprises a first semiconductor chip and at least one second semiconductor chip provided on the first semiconductor chip, comprising the steps of: (a) determining the area on the first semiconductor chip that the at least one second semiconductor chip is to be disposed from the arrangement relationship between the first semiconductor chip and the at least one second semiconductor chip and the configurations of the first semiconductor chip and the at least one second semiconductor chip; (b) detecting the number of the at least one second semiconductor chips; (c) if the number of the at least one second semiconductor chips is 1 in the step (b), determining the configuration of a mark indicating the position on the first semiconductor chip that the second semiconductor chip is to be provided; and (d) if the number of the at least one second semiconductor chips is a plural number in the step (b), determining the configuration of marks indicating the positions on the first semiconductor chip that the second semiconductor chips are to be provided.
  • the second semiconductor chip when fixed on the first semiconductor chip, the second semiconductor chip can be prevented from mistaken for other semiconductor chips. Further, when a plurality of second semiconductor chips are fixed on the first semiconductor chip, a mistake among the plurality of second semiconductor chips can be prevented.
  • a method for designing semiconductor device which comprises an internal circuit, comprising the step of determining, from a netlist and the configuration of semiconductor chip, the positions of wire bonding pad provided on the semiconductor chip and connected to the internal circuit and bump connection pad connected to the internal circuit in parallel with the wire bonding pad.
  • a method for designing semiconductor device which comprises a first semiconductor chip that includes a first internal circuit and a plurality of first conductive pad provided on its upper surface; and a second semiconductor chip provided on the first semiconductor chip that includes a second internal circuit and a plurality of conductive pads provided on it upper surface, wherein the first conductive pads are connected to the second conductive pads, and a ground potential is supplied to at least one of the plurality of first conductive pads, the method comprising the step of selecting a first conductive pad and a second conductive pad with a ground potential being applied thereto from the connection relationship between the internal circuits and the positions of the conductive pads.
  • a semiconductor device that by connecting selected first and second conductive pads to a ground potential by wire bonding, the space between the first semiconductor chip and the second semiconductor chip is substantially electrically shielded and EMI (Electro Magnetic Interference) is suppressed and prevented can be obtained.
  • EMI Electro Magnetic Interference
  • a computer readable recording medium incorporated into a computer used for designing a semiconductor device which comprises a first semiconductor chip that includes a first internal circuit and a first conductive pad which is provided on it upper surface and is connected to the first internal circuit and a second semiconductor chip provided on the first semiconductor chip that includes a second internal circuit and a second conductive pad which is provided on its upper surface and is connected to the second internal circuit, wherein the first conductive pad is connected to the second conductive pad and the first conductive pad is connected to externals
  • recorded in the recording medium is the program for a computer to perform the steps of: (a) determining a connection path from the connection relationship between the internal circuits and the externals and the positions of the conductive pads; (b) when the connection path is connected by a connecting member, determining whether or not a delay value of the connection path is within a tolerance; and (c) if it is determined in the step (b) that the delay value of the connection path is not within a tolerance, changing the connecting member so
  • a computer readable recording medium incorporated into a computer used for designing a semiconductor device which comprises a first semiconductor chip and a second semiconductor chip provided on the first semiconductor chip, recorded in the recording medium is the program for a computer to perform the steps of: (a) determining the area on the first semiconductor chip that the second semiconductor chip is to be mounted from the arrangement relationship between the first semiconductor chip and the second semiconductor chip and the configurations of the first semiconductor chip and the second semiconductor chip; and (b) determining the arrangement of a first convex portion on the first semiconductor chip and the configuration of the first convex portion in order to form the first convex portion the second semiconductor chip engages with.
  • a computer readable recording medium incorporated into a computer used for designing a semiconductor device which comprises a first semiconductor chip and at least one second semiconductor chip provided on the first semiconductor chip, recorded in the recording medium is the program for a computer to perform the steps of: (a) determining the area on the first semiconductor chip that the at least one second semiconductor chip is to be disposed from the arrangement relationship between the first semiconductor chip and the at least one second semiconductor chip and the configurations of the first semiconductor chip and the at least one second semiconductor chip; (b) detecting the number of the at least one second semiconductor chips; (c) if the number of the at least one second semiconductor chips is 1 in the step (b), determining the positions of a first engagement portion on the first semiconductor chip and a second engagement portion on the second semiconductor chip fitted into the first engagement portion and the configurations of the first engagement portion and the second engagement portion; and (d) if the number of the at least one second semiconductor chips is a plural number in the step (b), determining the positions of the first engagement portions on the
  • a computer readable recording medium incorporated into a computer used for designing a semiconductor device which comprises a first semiconductor chip and at least one second semiconductor chip provided on the first semiconductor chip, recorded in the recording medium is the program for a computer to perform the steps of: (a) determining the area on the first semiconductor chip that the at least one second semiconductor chip is to be disposed from the arrangement relationship between the first semiconductor chip and the at least one second semiconductor chip and the configurations of the first semiconductor chip and the at least one second semiconductor chip; (b) detecting the number of the at least one second semiconductor chips; (c) if the number of the at least one second semiconductor chips is 1 in the step (b), determining the configuration of a mark indicating the position on the first semiconductor chip that the second semiconductor chip is to be provided; and (d) if the number of the at least one second semiconductor chips is a plural number in the step (b), determining the configuration of marks indicating the positions on the first semiconductor chip that the second semiconductor chips are to be provided.
  • a computer readable recording medium incorporated into a computer used for designing a semiconductor device with an internal circuit, recorded in the recording medium is the program for a computer to perform the step of determining, from a netlist and the configuration of a semiconductor chip, the positions of wire bonding pad provided on the semiconductor chip and connected to the internal circuit and bump connection pad connected to the internal circuit in parallel with the wire bonding pad.
  • a computer readable recording medium incorporated into a computer used for designing a semiconductor device which comprises a first semiconductor chip that includes a first internal circuit and a plurality of first conductive pads provided on its upper surface and a second semiconductor chip provided on the first semiconductor chip that includes a second internal circuit and a plurality of second conductive pads provided on its upper surface, wherein the first conductive pads are connected to the second conductive pads and a ground potential is supplied to at least one of the plurality of first conductive pads, recorded in the recording medium is the program for a computer to perform the step of selecting a first conductive pad and a second conductive pad with the ground potential being applied thereto from the connection relationship between the internal circuits and the positions of the conductive pads.
  • FIGS. 1A and 1B are perspective view illustrating the structure of a semiconductor device of embodiment 1.
  • FIG. 2 is a cross-sectional view taken along a line I-I shown in FIG. 1.
  • FIG. 3 is a perspective view illustrating the structure of a semiconductor device of embodiment 2.
  • FIG. 4 is a perspective view illustrating the structure of a semiconductor device of embodiment 3.
  • FIG. 5 is a perspective view illustrating the structure of a semiconductor device of embodiment 4.
  • FIG. 6 is a perspective view illustrating the structure of a semiconductor device of embodiment 5.
  • FIG. 7 is a cross-sectional view taken along a line II-II shown in FIG. 6.
  • FIG. 8 is a perspective view illustrating the structure of a semiconductor device of embodiment 6.
  • FIG. 9 is a cross-sectional view taken along a line III-III shown in FIG. 8.
  • FIG. 10 is a typical view illustrating the structure of a semiconductor device of embodiment 7.
  • FIG. 11 is a typical view illustrating another structure of the semiconductor device of embodiment 7.
  • FIG. 12 is a view illustrating a circuit structure.
  • FIG. 13 is a perspective view illustrating the structure of a semiconductor device of embodiment 8.
  • FIG. 14 is a cross-sectional view taken along a line V-V shown in FIG. 13.
  • FIG. 15 is a block diagram illustrating the structure of a design device of the present invention.
  • FIG. 16 is a flowchart illustrating operations of the design device in accordance with embodiment 9.
  • FIG. 17 is a flowchart illustrating operations of the design device in accordance with embodiment 10.
  • FIG. 18 is a flowchart illustrating operations of the design device in accordance with embodiment 11.
  • FIG. 19 is a flowchart illustrating operations of the design device in accordance with embodiment 12.
  • FIG. 20 is a flowchart illustrating operations of the design device in accordance with embodiment 13.
  • FIG. 21 is a flowchart illustrating operations of the design device in accordance with embodiment 14.
  • FIG. 22 is a flowchart illustrating operations of the design device in accordance with embodiment 15.
  • FIG. 23 is a flowchart illustrating operations of the design device in accordance with embodiment 16.
  • FIG. 24 is a flowchart illustrating operations of the design device in accordance with embodiment 17.
  • FIG. 25 is a flowchart illustrating operations of the design device in accordance with embodiment 18.
  • FIG. 26 is a flowchart illustrating operations of the design device in accordance with embodiment 19.
  • FIG. 27 is a view illustrating the structure of a conventional semiconductor device.
  • FIG. 28 is a cross-sectional view taken along a line X-X shown in FIG. 27.
  • connection means “electrically connect” unless otherwise mentioned.
  • FIGS. 1A and 1B are perspective views showing structures of semiconductor devices relating to this embodiment.
  • FIG. 2 is a cross-sectional view taken along a line I-I shown in FIG. 1A.
  • a semiconductor device 100 a of this embodiment has a semiconductor chip B 1 which has an internal circuit (not shown) and a plurality of pads 10 connected to the internal circuit and a semiconductor chip A 1 which has an internal circuit (not shown) and a plurality of pads 20 connected to the internal circuit and which is adhered on the semiconductor chip B 1 .
  • the semiconductor chip A 1 is fixed on the semiconductor chip B 1 with an adhered portion being interposed therebetween.
  • the semiconductor chip B 1 is provided with the plurality of pads 10 connected to its internal circuit and a plurality of wire bond islands 31 .
  • the wire bond island 31 refers to as a conductive pad which is not connected to the internal circuit of the semiconductor chip B 1 .
  • the semiconductor device 100 a of this embodiment further includes wires 13 , 15 , 23 and 25 connecting the pads 10 for the semiconductor B 1 to the pads 20 for the semiconductor chip A 1 , wires 11 , 16 , 21 and 26 connecting the pads 10 for the semiconductor chip B 1 to electrodes outside the semiconductor device 100 a (e.g., leads of lead frame and electrodes for printed wiring board) and wires 12 a , 12 b , 14 a , 14 b , 17 a , 17 b , 22 a , 22 b , 24 a and 24 b connecting the pads 20 for the semiconductor chip A 1 via the wire bond islands 31 to external electrodes.
  • wires 13 , 15 , 23 and 25 connecting the pads 10 for the semiconductor B 1 to the pads 20 for the semiconductor chip A 1 , wires 11 , 16 , 21 and 26 connecting the pads 10 for the semiconductor chip B 1 to electrodes outside the semiconductor device 100 a (e.g., leads of lead frame and electrodes for printed wiring board) and wires 12 a ,
  • the semiconductor device 100 a of this embodiment suppose that the maximum distance from the wires 12 a and 12 b connecting a pad 20 of the semiconductor A 1 to an electrode outside the semiconductor device 100 a to the upper surface of the semiconductor chip B 1 is indicated by h 1 . Then, h 1 ⁇ h . This is applicable to the wires 14 a and 14 b , the wires 17 a and 17 b and the wires 22 a and 22 b . Bent of wires as in the conventional semiconductor device 1000 is suppressed in the semiconductor device 100 a of this embodiment. Accordingly, when wires are provided and then the semiconductor device 100 a is to be worked, short of the wires can be prevented. Thus, yield rates for products obtained by working the semiconductor device 100 a are improved.
  • the wire 12 a may be as long as the wire 17 a
  • the wire 12 b may be as long as the wire 17 b .
  • skew caused by differences between the lengths of the wires is reduced.
  • wirings for structuring synchronous circuits are easily designed.
  • the wires between the semiconductor chips A 1 and B 1 may be the same length and wiring delay values may also be the same value.
  • the semiconductor device 100 a ′ shown in FIG. 1B will be described. As shown in FIG. 1B, the semiconductor device 100 a ′ has substantially same structure as that of the above-described semiconductor device 100 a .
  • the semiconductor device 100 a ′ is different from the semiconductor device 100 a only in that the semiconductor chip B 1 has the wire bond islands 31 that are not used for wire bonding connection.
  • the semiconductor chip B 1 when the semiconductor chip B 1 has a plurality of wire bond islands 31 regardless of being used for wire bonding connection, a semiconductor chip which is different from the semiconductor chip A 1 may be mounted by using appropriate wire bond islands 31 . Namely, the semiconductor B 1 may be widely used.
  • FIG. 3 is a perspective view illustrating the structure of a semiconductor device of this embodiment.
  • a semiconductor device 100 b of this embodiment has a semiconductor chip B 2 which includes an internal circuit (not shown) and a plurality of pads 10 connected to the internal circuit and a semiconductor chip A 2 which includes an internal circuit (not shown) and a plurality of pads 20 connected to the internal circuit and is adhered on the semiconductor chip B 2 .
  • the semiconductor chip B 2 is provided with the plurality of pads 10 connected to the internal circuit and wire bond islands 31 and 32 .
  • the wire bond island refers to as a conductive pad which is not connected to the internal circuit of the semiconductor chip B 2 .
  • the wire bond islands 32 are formed in an elliptical configuration.
  • the semiconductor device 100 b of this embodiment includes wires 13 , 15 , 23 and 25 connecting the pads 10 for the semiconductor chip B 2 to the pads 20 for the semiconductor chip A 2 , wires 11 , 16 , 21 and 26 connecting the pads 10 for the semiconductor chip B 2 to external electrodes (e.g., leads of lead frame, electrodes for printed wiring board and the like) and wires 12 a , 12 b , 17 a , 17 b , 14 a , 14 b , 22 a , 22 b , 24 a and 24 b connecting the pads 20 for the semiconductor chip A 2 via the wire bond islands 31 to external electrodes.
  • external electrodes e.g., leads of lead frame, electrodes for printed wiring board and the like
  • the wire bond islands 32 are formed in an elliptical configuration. As shown in FIG. 3, the wire 24 b is connected to the wire bond island 32 at a portion which is different from that the wire 24 a is connected. For this reason, for example, when other component which becomes an obstacle when an external pad to be connected to the wire 24 b is linearly connected to the position the wire 24 a is connected exists, the wire 24 b does not contact the other component. Namely, by changing the configuration of the wire bond islands, a degree of freedom in wiring design is improved.
  • the configuration of the wire bond islands 32 is not limited to an elliptical configuration and preferably, is appropriately changed to configurations enabling wires to be provided most efficiently.
  • the wires may have the same length.
  • skew caused by differences between the lengths of the wires is reduced.
  • wirings for structuring synchronous circuits are easily designed.
  • the wires between the semiconductor chips A 1 and B 1 may have the same length and wiring delay values may also have the same value.
  • FIG. 4 is a perspective view illustrating the structure of a semiconductor device of this embodiment.
  • a semiconductor device 100 c of this embodiment has a semiconductor chip B 3 which includes an internal circuit (not shown) and a plurality of pads 10 connected to the internal circuit and a semiconductor chip A 3 which includes an internal circuit (not shown) and a plurality of pads 20 connected to the internal circuit and is adhered on the semiconductor chip B 3 .
  • the semiconductor device 100 c of this embodiment has wires 13 , 15 , 23 and 25 connecting the pads 10 for the semiconductor chip B 3 to the pads 20 for the semiconductor chip A 3 , wires 11 , 16 , 21 and 26 connecting the pads 10 for the semiconductor chip B 3 to external electrodes (e.g., leads of lead frame, electrodes for printed wiring board and the like) and wires 12 , 14 , 22 and 24 connecting the pads 20 for the semiconductor chip A 3 to external electrodes.
  • the wire 13 is especially made of gold and is different from other wires made of aluminum.
  • the wire 13 is made of gold whose resistance is different from those of the other wires made of aluminum.
  • a delay value may be adjusted for each of the wires.
  • aluminum and gold are used for forming wires in this embodiment, the present invention does not limit such materials.
  • silver, copper, platinum may be used.
  • FIG. 5 is a perspective view illustrating the structure of a semiconductor device of this embodiment.
  • a semiconductor device 100 d of this embodiment has a semiconductor chip B 4 which includes an internal circuit (not shown) and a plurality of pads 10 connected to the internal circuit and a semiconductor chip A 4 which includes an internal circuit (not shown) and a plurality of pads 20 connected to the internal circuit and is adhered on the semiconductor chip B 4 .
  • the semiconductor device 100 d of this embodiment has wires 13 , 15 , 23 and 25 connecting the pads 10 for the semiconductor chip B 4 to the pads 20 for the semiconductor chip A 4 , wires 11 , 16 , 21 and 26 connecting the pads 10 for the semiconductor chip B 4 to external electrodes (e.g., leads of lead frame, electrodes for printed wiring board and the like) and wires 12 , 14 , 22 and 24 connecting the pads 20 for the semiconductor chip A 4 to external electrodes.
  • the wire 25 is made of two wires.
  • a wiring resistance can be reduced. Namely, by adjusting the number of wires for each of the wires, a delay value may be adjusted for each of the wires.
  • a semiconductor device which is easily designed and manufactured and in which a plurality of semiconductor chips are integrally structured is obtained.
  • a semiconductor device which is suitable for, in particular, high speed operation is obtained.
  • FIG. 6 is a perspective view illustrating the structure of a semiconductor device of this embodiment.
  • FIG. 7 is a cross-sectional view taken along a line 11 - 11 shown in FIG. 6. In this embodiment, wires are not shown in order to eliminate complicated descriptions.
  • a semiconductor device 200 of this embodiment has a semiconductor chip B 5 which includes an internal circuit (not shown) and a plurality of pads 10 connected to the internal circuit and a semiconductor chip A 5 which includes an internal circuit (not shown) and a plurality of pads 20 connected to the internal circuit and is adhered on the semiconductor chip B 5 with an adhered portion being interposed therebetween.
  • the semiconductor chip B 5 further has convex portions 41 and convex portions 40 for sliding.
  • the convex portions 41 are provided at corners of an area on the upper surface of the semiconductor chip B 5 where the semiconductor chip A 5 is to be adhered so as to define the area where the semiconductor chip A 5 is to be adhered.
  • a large number of the convex portions 40 for sliding are provided on the area on the upper surface of the semiconductor chip B 5 other than the area the semiconductor chip A 5 is to be adhered.
  • the convex portions 40 for sliding are disposed so that areas with sufficient size and configuration for the semiconductor chip A 5 to be adhered thereon are not formed between the convex portions 40 for sliding.
  • the convex portions 41 are provided on the upper surface of the semiconductor chip B 5 so as to define the area the semiconductor chip A 5 is to be adhered.
  • the semiconductor chip A 5 is reliably fixed without misalignment.
  • the convex portions 40 for sliding disposed so that areas with sufficient size and configuration for the semiconductor chip A 5 to be adhered thereon are not formed are provided on the upper surface of the semiconductor chip B 5 . For this reason, even if the semiconductor chip A 5 is placed on a position other than the area where the semiconductor A 5 should be originally adhered when being adhered on the semiconductor B 5 in the process for manufacturing the semiconductor device 200 , the semiconductor chip A 5 slides on the convex portions 40 for sliding and is surely adhered on the area defined by the convex portions 41 .
  • the semiconductor chip A 5 needs not to be aligned with the semiconductor chip B 5 when being adhered thereon.
  • the semiconductor chip A 5 can be easily adhered on the semiconductor chip B 5 .
  • FIG. 8 is a perspective view illustrating the structure of a semiconductor device of this embodiment.
  • FIG. 9 is a cross-sectional view taken along a line 111 - 111 shown in FIG. 8.
  • a semiconductor device 300 of this embodiment has a semiconductor chip B 6 which includes an internal circuit (not shown) and a plurality of pads connected to the internal circuit and semiconductor chips A 6 and A 6 ′ each of which includes an internal circuit (not shown) and a plurality of pads connected to the internal circuit and is provided on the semiconductor chip B 6 . Wires and pads are not shown in this embodiment in order to eliminate complicated descriptions.
  • the semiconductor chip B 6 has circular openings 42 a and rectangular openings 42 b .
  • the semiconductor chip A 6 has convex portions 43 a with circular cross-sectional configuration and the semiconductor chip A 6 ′ has convex portions 43 b with rectangular cross-sectional configuration.
  • the semiconductor chip A 6 ′ is adhered to the semiconductor chip B 6 with an adhered portion being interposed therebetween.
  • the convex portions 43 b of the semiconductor chip A 6 ′ are fitted into the openings 42 b of the semiconductor chip B 6 .
  • the semiconductor chip A 6 is also adhered to the semiconductor chip B 6 with an adhered portion being interposed therebetween.
  • the convex portions 43 a of the semiconductor chip A 6 are fitted into the openings 42 a of the semiconductor chip B 6 .
  • a mark 44 a for chip arrangement is printed on an area 45 a of the upper surface of the semiconductor chip B 6 that the semiconductor chip A 6 is adhered.
  • a mark 44 b for chip arrangement is printed on an area 45 b that the semiconductor chip A 6 ′ is adhered.
  • the semiconductor chip A 6 is provided with the convex portions 43 a
  • the semiconductor chip A 6 ′ is provided with the convex portions 43 b
  • the semiconductor chip B 6 is provided with the openings 42 b and the openings 42 a , so that when the semiconductor chips A 6 and A 6 ′ are adhered to the semiconductor chip B 6 , the convex portions 43 a are fitted into the openings 42 a and the convex portions 43 b are fitted into the openings 42 b .
  • the semiconductor chip A 6 is securely fixed on the semiconductor chip B 6 without misalignment.
  • the convex portions 43 a and the openings 42 a have a cylindrical configuration, and the convex portions 43 b and the openings 42 b have a square pole configuration. For this reason, if the semiconductor chip A 6 is mistaken for the semiconductor chip A 6 ′, the semiconductor chips A 6 and A 6 ′ cannot be adhered on the semiconductor chip B 6 . Thus, it is possible to prevent a semiconductor device from being structured with the semiconductor A 6 being mistaken for the semiconductor chip A 6 ′.
  • the convex portions 43 a and the openings 42 a have a cylindrical configuration and the convex portions 43 b and the openings 42 b have a square pole configuration in this embodiment, the present invention is not limited such case.
  • the convex portions 43 a and the openings 42 a may have any configurations including a star-shaped pole configuration, a triangle pole configuration and the like.
  • the area 45 a on the semiconductor chip B 6 the semiconductor chip A 6 is adhered is provided with the mark 44 a for chip arrangement serving as a mark for fixing the semiconductor chip A 6 .
  • the area 45 b on the semiconductor chip B 6 the semiconductor chip A 6 ′ is adhered is provided with the mark 44 b for chip arrangement serving as a mark for fixing the semiconductor chip A 6 ′.
  • the semiconductor chips A 6 and A 6 ′ are electrically connected to the semiconductor chip B 6 by wire bonding. Nevertheless, the present invention is not limited to such case.
  • the semiconductor chips A 6 and A 6 ′ may be electrically connected to the semiconductor chip B 6 by bumps. Further, wire bonding and bump connection may be used together.
  • FIGS. 10 and 11 are typical views illustrating the structure of a semiconductor device of this embodiment.
  • a semiconductor device 400 of this embodiment has a semiconductor chip B 7 which includes an internal circuit (not shown) and a plurality of pads 10 connected to the internal circuit and a semiconductor chip A 7 which includes an internal circuit (not shown) and a plurality of pads 20 for wire bonding connected to the internal circuit and is adhered on the semiconductor chip B 7 .
  • the semiconductor chip A 7 is connected to the semiconductor chip B 7 by wires 11 connecting the pads 10 for the semiconductor chip B 7 to the pads 20 for the semiconductor chip A 7 .
  • a semiconductor device 400 ′ of this embodiment has a semiconductor chip A 7 which includes an internal circuit (not shown) and a plurality of bump connection pads 30 connected to the internal circuit and a semiconductor chip C 7 which includes an internal circuit (not shown) and a plurality of bump connection pads (not shown) provided on the lower surface thereof and connected to the internal circuit and which is provided on the semiconductor chip A 7 .
  • the pads 30 for the semiconductor chip A 7 are connected to the bump connection pads of the semiconductor chip C 7 by bump connection.
  • the semiconductor chip A 7 is used in the semiconductor devices 400 and 400 ′ of this embodiment.
  • the wire bonding pads 20 and the bump connection pads 30 are provided on the upper surface of the semiconductor chip A 7 .
  • the semiconductor chip C 7 when the semiconductor chip C 7 with, on its lower surface, wires (not shown) enabling bump connection to the bump pads 30 of the semiconductor chip A 7 is prepared, the semiconductor chip C 7 can be bump-connected by fillip chip bonding.
  • the semiconductor chip A 7 of this embodiment includes the bump connection pads 30 on its upper surface with the plurality of pads 20 being provided thereat and an circuit shown in FIG. 12.
  • FIG. 12 shows the structure of the circuit for the semiconductor chip A 7 of this embodiment.
  • a wire bonding pad 20 and a bump connection pad 30 are connected to the internal circuit in the semiconductor chip A 7 .
  • the semiconductor chip A 7 can be connected to the semiconductor chip B 7 by wire bonding and to the semiconductor chip C 7 by bump connection.
  • both of the semiconductor device 400 shown in FIG. 10 and the semiconductor device 400 ′ shown in FIG. 11 can be manufactured.
  • the wire bonding connection is cheaper than the bump connection.
  • the bump connection is easier.
  • the wire bonding pads may be provided at 80 ⁇ m of minimum intervals therebetween.
  • the bump connection pads may be provided at 5 ⁇ m of minimum intervals therebetween.
  • an optimal connection method for structuring a semiconductor device can be selected depending on manufacturing costs, sizes of the semiconductor chips A 7 , B 7 and C 7 , wiring rules and the like. Namely, a degree of freedom in designing a semiconductor chip and a semiconductor device may be significantly improved.
  • FIG. 13 is a perspective view illustrating a semiconductor device of this embodiment.
  • FIG. 14 is a cross-sectional view taken along a line V-V shown in FIG. 13.
  • a semiconductor device 500 of this embodiment has a semiconductor chip B 8 which includes a plurality of pads 10 and a semiconductor chip A 8 which includes a plurality of pads 20 and is adhered on the semiconductor chip B 8 .
  • the semiconductor device 500 of this embodiment has wires 60 connecting the pads 10 for the semiconductor chip B 8 to the pads 20 for the semiconductor chip A 8 and wires 61 connecting the pads 10 for the semiconductor chip B 8 to externals (group potential Vss).
  • bump connection pads (not shown) connected to an internal circuit are provided on the lower surface of the semiconductor chip A 8 .
  • Bump connection pads (not shown) connected to an internal circuit (not shown) are also provided on the upper and the lower surfaces of the semiconductor chip B 8 .
  • the internal circuit for the semiconductor chip A 8 is connected to the internal circuit for the semiconductor chip B 8 by bump connection.
  • the internal circuit for the semiconductor chip B 8 is bump-connected to externals by using the bump connection pads provided on the lower surface of the semiconductor chip B 8 .
  • FIG. 15 is a block diagram illustrating the structure of design device used for manufacturing the semiconductor devices 100 a to 100 d and 200 to 500 .
  • a design device 600 of this embodiment comprises an input section 71 data is inputted, a CPU 72 which treats the data inputted to the input section 71 , a database 73 which stores the data, an output section 74 which outputs results of treatment in the CPU 72 , a wire bond island forming section 80 for forming wire bond islands, a wire bond island configuration changing section 81 for changing configurations and materials for wire bond islands determined by the wire bond island forming section 80 , an equal length path determining section 82 for determining connection paths whose lengths should be equal, a delay determining section 83 for determining a delay, a wire material changing section 84 changing to wire materials with delay values within a range determined by the delay determining section 83 , a number-of-wires changing section 85 for changing to the number of wires in order to obtain a delay value within a range determined by the delay determining section 83 , a convex portion forming section 86 for forming convex portions defining an area a
  • a method for designing semiconductor device will be described in the following embodiments with reference to FIGS. 16 to 26 .
  • Design methods represented by flowcharts shown in FIGS. 16 to 26 are used in order to design a semiconductor device by the design device 600 .
  • FIG. 16 is a flowchart illustrating operations of the design device 600 when the semiconductor device 100 a of the embodiment 1 is designed.
  • step St 1 circuit structure data, inter-circuit connection data and pad position data are inputted to the input section 71 .
  • the circuit structure data refers to as data representing structures of internal circuits provided within the semiconductor chips A 1 and B 1 and an external circuit the semiconductor device 100 a is to be connected.
  • the inter-circuit connection data refers to as data representing the connection relationship between the internal circuit for the semiconductor chip A 1 , the internal circuit for the semiconductor chip B 1 and the external circuit.
  • the pad position data refers to as data representing the positions of the pads 20 for the semiconductor chip A 1 , the pads 10 for the semiconductor chip B 1 and external pads for the external circuit (leads of lead frame).
  • Such data are inputted to the input section 71 and then the CPU 72 selects the data and stores the same in the database 73 .
  • step St 2 the CPU 72 searches, on a basis of the respective data, connection paths formed between the pads 10 , the pads 20 and the external pads so as to satisfy the inter-circuit connection data.
  • step St 3 the CPU 72 determines whether or not all of the connection paths obtained by step St 2 can be connected by wire bonding. If wire bonding is possible, the CPU 72 activates the wire bond island forming section 80 and the process proceeds to step St 4 . If at least one of the connection paths obtained in step St 2 cannot be connected by wire bonding, the process returns to step St 2 and the CPU 72 searches other connection paths that satisfy the inter-circuit connection data. Then, in step St 3 , it is determined whether or not all of the connection path searched again can be connected by wire bonding. Steps St 2 and St 3 are repeated until all of connection paths obtained by step St 2 can be connected by wire bonding. If all connection paths can be connected by wire bonding, the CPU 72 activates the wire bond island forming section 80 and the process proceed to step St 4 .
  • step St 4 the wire bond island forming section 80 calculates the positions on the semiconductor chip B 1 that the wire bond islands 31 are formed (wire bond island position data) with respect to connection path connecting the pads 10 to the external pads among the searched connection paths.
  • the wire bond island forming section 80 makes reference to wire bond island configuration data (circular configuration data herein) set as a default stored in advance from the database 73 .
  • step St 5 the CPU 72 produces wire bonding performing data for a wire bonding device to perform wire bonding from the wire bond island position data obtained in step St 4 and the wire bond island configuration data.
  • step St 6 the output section 74 outputs the wire bonding performing data.
  • the semiconductor device 100 a is designed.
  • the semiconductor device 100 a that bent of wires connecting semiconductor chips is prevented is obtained.
  • FIG. 17 is a flowchart illustrating operations of the design device 600 when the semiconductor device 100 b of the embodiment 2 is designed.
  • step St 11 circuit structure data, data inter-circuit connection and pad position data are inputted to the input section 71 .
  • the circuit structure data refers to data representing structures of the internal circuits provided within the semiconductor chips A 2 and B 2 and external circuit the semiconductor device 100 b is connected.
  • the inter-circuit connection data refers to as data representing the connection relationship between the internal circuit for the semiconductor chip A 2 , the internal circuit for the semiconductor chip B 2 and the internal circuit.
  • the pad position data refers to data representing the positions of the pads 20 for the semiconductor chip A 2 , the pads 10 for the semiconductor chip B 2 and external pads (leads of lead frame) for the external circuit.
  • the CPU 72 selects the data and stores the same in the database 73 .
  • step St 12 the CPU 72 searches, on a basis of the respective data, connection paths formed between the pads 10 , the pads 20 and the external pads so as to satisfy the inter-circuit connection data.
  • the CPU 72 determines in step St 13 whether or not all of the connection paths obtained in step St 12 can be connected by wire bonding. If connection by wire bonding is possible, the CPU 72 activates the wire bond island forming section 80 and the process proceeds to St 14 a . If at least one of the connection paths obtained in step St 12 cannot be connected by wire bonding, the CPU 72 activates the wire bond island forming section 80 and the process proceeds to step St 14 b.
  • step St 14 a the wire bond island forming section 80 calculates the positions on the semiconductor chip B 2 that the wire bond islands 31 are to be formed (wire bond island position data) for connection paths connecting the pads 10 to the external pads of the searched connection paths.
  • the wire bond island forming section 80 makes reference to, from the database 73 , wire bond island configuration data (circular configuration data herein) set as a default stored in advance. Then, the process proceeds to step St 15 .
  • step St 14 b the wire bond island forming section 80 calculates the positions on the semiconductor chip B 2 that the wire bond islands 32 are to be formed (wire bond island position data) for connection paths connecting the pads 10 to the external pads of the searched connection paths.
  • the wire bond island forming section 80 makes reference to, from the database 73 , wire bond island configuration data (circular configuration data herein) set as a default stored in advance. Then, the process proceeds to step St 14 c.
  • step St 14 c the wire bond island configuration changing section 81 changes the configuration of the wire bond islands 32 by substituting the wire bond island configuration data (herein by substituting the circular configuration data set as a default by elliptical configuration data). If a delay value is extremely varied by substitution of the wire bond island configuration data, the wire bond island configuration changing section 81 may optimize materials for the wire bond islands and configurations thereof in order to suppress such variation in the delay value. Then, the process proceeds to step St 15 .
  • step St 15 the CPU 72 produces wire bonding performing data for a wire bonding device to perform wire bonding from the wire bond island position data obtained in step St 14 a and the wire bond island configuration data obtained in step St 14 c.
  • step St 16 the output section 74 outputs the wire bonding performing data.
  • the semiconductor device 100 b is designed.
  • the semiconductor device 100 b that bent of the wires connecting the semiconductor chips is prevented can be obtained.
  • a degree of freedom in wire bonding connection between the semiconductor chips is improved.
  • FIG. 18 is a flowchart illustrating operations of a device for designing semiconductor when the semiconductor device 100 b of the embodiment 2 is designed.
  • step St 21 circuit structure data, inter-circuit connection data and pad position data are inputted to the input section 71 .
  • the circuit structure data refers to data representing structures of the internal circuits provided within the semiconductor chips A 2 and B 2 and external circuit the semiconductor device 100 b is connected.
  • the inter-circuit connection data refers to as data representing the connection relationship between the internal circuit for the semiconductor chip A 2 , the internal circuit for the semiconductor chip B 2 and the internal circuit.
  • the pad position data refers to data representing the positions of the pads 20 for the semiconductor chip A 2 , the pads 10 for the semiconductor chip B 2 and external pads (leads of lead frame) for the external circuit.
  • the CPU 72 selects the data and stores the same in the database 73 .
  • step St 22 the CPU 72 searches, on a basis of the respective data, connection paths formed between the pads 10 , the pads 20 and the external pads so as to satisfy the inter-circuit connection data.
  • the CPU 72 determines in step St 23 whether or not all of the connection paths obtained in step St 22 can be connected by wire bonding. If connection by wire bonding is possible, the CPU 72 activates the wire bond island forming section 80 and the process proceeds to St 24 a . If at least one of the connection paths obtained in step St 22 cannot be connected by wire bonding, the CPU 72 activates the wire bond island forming section 80 and the process proceeds to step St 24 b.
  • step St 24 a the wire bond island forming section 80 calculates the positions on the semiconductor chip B 2 that the wire bond islands 31 are to be formed (wire bond island position data) for connection paths connecting the pads 10 to the external pads determined in step St 23 to be connected by wire bonding.
  • the wire bond island forming section 80 makes reference to, from the database 73 , wire bond island configuration data (circular configuration data herein) set as a default stored in advance. Then, the process proceeds to step St 25 .
  • step St 24 b the wire bond island forming section 80 calculates the positions on the semiconductor chip B 2 that the wire bond islands 32 are to be formed (wire bond island position data) for connection paths connecting the pads 10 to the external pads determined in step St 23 to be connected by wire bonding.
  • the wire bond island forming section 80 makes reference to, from the database 73 , wire bond island configuration data (circular configuration data herein) set as a default stored in advance. Then, the process proceeds to step St 24 c.
  • step St 24 c the wire bond island configuration changing section 81 changes the configuration of the wire bond islands 32 by substituting the wire bond island configuration data (herein by substituting the circular configuration data set as a default by elliptical configuration data) so that the connection paths connecting the pads 10 to the external pads determined in step St 23 not to be connected by wire bonding can be connected and the process proceeds to step St 25 . If a delay value is extremely varied by substitution of the wire bond island configuration data in this step St 24 , the wire bond island configuration changing section 81 may optimize materials for the wire bond islands and configurations thereof in order to suppress such variation in the delay value.
  • step St 25 the CPU 72 activates the equal length path determining section 82 .
  • the equal length path determining section 82 determines connection paths that should be have the same length. Specifically, the equal length path determining section 82 selects connection paths that must be have the equal length by making reference to the circuit structure data and the inter-circuit connection data stored in the database 73 in step St 21 . Then, the equal length path determining section 82 makes reference to the wire bond island position data and the wire bond island configuration data obtained in steps St 24 a , St 24 b and St 24 c and then adjusts the wire bond island position data so that selected connection path have the same length.
  • step St 26 the CPU 72 produces wire bonding performing data for a wire bonding device to perform wire bonding from the wire bond island position data obtained in step St 25 and the wire bond island configuration data obtained in steps St 24 a and St 24 c.
  • step St 27 the output section 74 outputs the wire bonding performing data.
  • the semiconductor device 100 b is designed.
  • the semiconductor device 100 b that specified wires have the same length can be obtained.
  • a skew generated by the difference in length of wires is reduced in the wires with the same length.
  • the method of this embodiment is especially preferable when synchronous circuits must be structured in the semiconductor device 100 b.
  • the wires between the semiconductor chip A 1 and the semiconductor chip B 1 may have the same length and wire delay values may be also the same value.
  • FIG. 19 is a flowchart illustrating operations of the design device 600 when the semiconductor device 100 c of the embodiment 3 is designed.
  • step St 31 circuit structure data, inter-circuit connection data, pad position data and connection delay tolerant data are inputted to the input section 71 .
  • the circuit structure data refers to data representing structures of the internal circuits provided within the semiconductor chips A 3 and B 3 and external circuit the semiconductor device 100 c is connected.
  • the inter-circuit connection data refers to as data representing the connection relationship between the internal circuit for the semiconductor chip A 3 , the internal circuit for the semiconductor chip B 3 and the internal circuit.
  • the pad position data refers to data representing the positions of the pads 20 for the semiconductor chip A 3 , the pads 10 for the semiconductor chip B 3 and external pads (leads of lead frame) for the external circuit.
  • the connection delay tolerant data refers to data representing the tolerance of a delay value set for every connection between the internal circuit for the semiconductor chip A 3 , the internal circuit for the semiconductor chip B 3 and the external circuit. The tolerance of the delay value may be set, depending on specifications of semiconductor devices, only for a specified connection or may be set for all connections.
  • the CPU 72 selects the data and stores the same in the database 73 .
  • step St 32 the CPU 72 searches, on a basis of the respective data, connection paths formed between the pads 10 , the pads 20 and the external pads so as to satisfy the inter-circuit connection data.
  • step St 33 the CPU 72 activates the delay determining section 83 .
  • the delay determining section 83 calculates, on a basis of data about resistance values for wire materials stored in the database 73 serving as a default, a delay value for connection paths obtained in step St 32 and then determines whether or not the calculated delay value is within a tolerance on a basis of the connection delay tolerant data. If the calculated delay value is within a tolerance, the CPU 72 proceeds to step St 35 . If the delay value calculated in the connection paths obtained in step St 32 is out of tolerance, the CPU 72 activates the wire material changing section 84 and the process proceeds to step St 34 .
  • step St 34 the wire material changing section 84 changes materials for wires for connection paths that the delay value obtained in step St 33 is out of tolerance. Specifically, the wire material changing section 84 selects materials for wires that a delay value is within a tolerance while making reference to data about resistance for various materials stored in advance in the database 73 . Then, the process proceeds to step St 35 .
  • step St 35 the CPU 72 produces, on a basis of the connection paths obtained in step St 33 , wire bonding performing data for a wire bonding device to perform wire bonding. If the connection paths that wire materials were changed in step St 34 are provided, wire bonding performing data is produced on a basis of obtained materials for wires.
  • step St 36 the output section 74 outputs the wire bonding performing data.
  • the semiconductor device 100 c is designed.
  • wire materials may be changed. For this reason, a delay value may be adjusted for each of the connection paths between the semiconductor chips.
  • FIG. 20 is a flowchart illustrating operations of a device for designing semiconductor when the semiconductor device 100 d of the embodiment 4 is designed.
  • step St 41 circuit structure data, inter-circuit connection data, pad position data and connection delay tolerant data are inputted to the input section 71 .
  • the circuit structure data refers to data representing structures of the internal circuits provided within the semiconductor chips A 4 and B 4 and external circuit the semiconductor device 100 d is connected.
  • the inter-circuit connection data refers to as data representing the connection relationship between the internal circuit for the semiconductor chip A 4 , the internal circuit for the semiconductor chip B 4 and the internal circuit.
  • the pad position data refers to data representing the positions of the pads 20 for the semiconductor chip A 4 , the pads 10 for the semiconductor chip B 4 and external pads (leads of lead frame) for the external circuit.
  • the connection delay tolerant data refers to data representing the tolerance of a delay value set for every connection between the internal circuit for the semiconductor chip A 4 , the internal circuit for the semiconductor chip B 4 and the external circuit. The tolerance of the delay value may be set, depending on specifications of semiconductor devices, only for a specified connection or may be set for all connections.
  • the CPU 72 selects the data and stores the same in the database 73 .
  • step St 42 the CPU 72 searches, on a basis of the respective data, connection paths formed between the pads 10 , the pads 20 and the external pads so as to satisfy the inter-circuit connection data.
  • step St 43 the CPU 72 calculates, on a basis of data about resistance values for wire materials stored in the database 73 serving as a default, a delay value for connection paths obtained in step St 42 and then determines whether or not the calculated delay value is within a tolerance on a basis of the connection delay tolerant data. If the calculated delay value is within a tolerance, the CPU 72 proceeds to step St 45 . If the delay value calculated in the connection paths obtained in step St 42 is out of tolerance, the CPU 72 activates the number-of-wires changing section 85 and the process proceeds to step St 44 .
  • step St 44 the number-of-wires changing section 85 changes the number of wires for the connection paths that the delay value obtained in step St 43 is out of tolerance. Specifically, the number-of-wires changing section 85 makes reference to data about resistance values for wire materials stored as a default in advance in the database 73 and then selects the number of wires that a delay value is within the tolerance. Then, the process proceeds to step St 45 .
  • step St 45 the CPU 72 produces, on a basis of the connection paths obtained in step St 43 , wire bonding performing data for a wire bonding device to perform wire bonding. If there may be included connection paths with the number of wires having been changed in step St 44 , wire bonding performing data is produced on a basis of the obtained number of wires.
  • step St 46 the output section 74 outputs the wire bonding performing data.
  • the semiconductor device 100 d is designed.
  • a delay value may be adjusted for each of the connection paths between the semiconductor chips by changing the number of wires.
  • FIG. 21 shows a flowchart illustrating operations of the design device 600 when the semiconductor device 200 of the embodiment 5 without the convex portions 40 for sliding being provided thereat is designed.
  • step St 51 semiconductor chip arrangement data and semiconductor chip configuration data are inputted to the input section 71 .
  • the semiconductor chip arrangement data refers to data representing an arrangement relationship when the semiconductor chip A 5 is adhered on the semiconductor chip B 5 .
  • the semiconductor chip configuration data refers to data representing configurations of the semiconductor chips A 5 and B 5 .
  • the CPU 72 selects the data and stores the same in the database 73 .
  • step St 52 the CPU 72 determines, from the respective data, the area on the semiconductor chip B 5 that the semiconductor chip A 5 is to be disposed.
  • step St 53 the CPU 72 activates the convex portion forming section 86 .
  • the convex portion forming section 86 calculates convex portion forming data (coordinates and configurations) for forming the convex portions 41 confining the area that the semiconductor chip A 5 is to be disposed obtained in step St 52 on the upper surface of the semiconductor chip B 2 .
  • the convex portion forming section 86 makes reference to various convex portion forming data already stored in the database 73 and selects optimum convex portion forming data.
  • step St 54 the CPU 72 produces, on a basis of the convex portion forming data obtained in step St 53 , semiconductor chip configuration data representing the configuration of the semiconductor chip B 5 .
  • step St 55 the output section 74 outputs the semiconductor chip configuration data.
  • the semiconductor device 200 is designed.
  • the convex portions 41 for confining the area that the semiconductor chip A 5 is to be adhered are designed on the upper surface of the semiconductor chip B 5 .
  • the semiconductor chip A 5 is securely fixed on the semiconductor chip B 5 without misalignment.
  • FIG. 22 shows a flowchart illustrating operations of the design device 600 when the semiconductor device 200 of the embodiment 5 is designed.
  • step St 61 semiconductor chip arrangement data and semiconductor chip configuration data are inputted to the input section 71 .
  • the semiconductor chip arrangement data refers to data representing an arrangement relationship when the semiconductor chip A 5 is adhered on the semiconductor chip B 5 .
  • the semiconductor chip configuration data refers to data representing configurations of the semiconductor chips A 5 and B 5 .
  • the CPU 72 selects the data and stores the same in the database 73 .
  • step St 62 the CPU 72 determines, from the respective data, the areas that the semiconductor chip A 5 the semiconductor chip B 5 are to be disposed.
  • step St 63 the CPU 72 activates the convex portion forming section 86 .
  • the convex portion forming section 86 calculates convex portion forming data (coordinates and configurations) for forming the convex portions 41 confining the area that the semiconductor chip A 5 is to be disposed obtained in step St 62 .
  • the convex portion forming section 86 makes reference to various convex portion forming data already stored in the database 73 and selects optimum convex portion forming data.
  • step St 64 the CPU 72 activates the convex-portion-for-sliding forming section 87 .
  • the convex-portion-for-sliding forming section 87 calculates convex-portion-for-sliding forming data (coordinates and configurations) for forming the convex portion 40 for sliding at areas other than the area obtained in step St 62 that the semiconductor chip A 5 is to be disposed.
  • the convex portions 40 for sliding are formed so that an area with sufficient size and configuration for the semiconductor chip A 5 to be adhered is not formed.
  • the convex-portion-for-sliding forming section 87 makes reference to various convex-portion-for-sliding forming data already stored in the database 73 and then selects optimum convex-portion-for-sliding forming data.
  • step St 65 the CPU 72 produces, on a basis of the convex portion forming data and the convex-portion-for-sliding forming data, semiconductor chip configuration data representing the configuration of the semiconductor chip B 5 .
  • step St 66 the output section 74 outputs the semiconductor chip configuration data.
  • the semiconductor device 200 is designed.
  • the convex portions 40 for sliding disposed so that an area with sufficient size and configuration for the semiconductor chip A 5 to be adhered is not formed are designed on the upper surface of the semiconductor chip B 5 .
  • the semiconductor chip A 5 slides on the convex portions 40 for sliding and then is reliably adhered at the area confined by the convex portions 41 .
  • the semiconductor chip A 5 when the semiconductor chip A 5 is adhered on the semiconductor chip B 5 , their alignment needs not to be performed. Accordingly, in accordance with this embodiment, the semiconductor chip A 5 can be easily adhered on the semiconductor chip B 5 .
  • FIG. 23 is a flowchart illustrating operations of the design device 600 when the semiconductor device 300 of the embodiment 6 without the marks 44 a and 44 b for chip arrangement being provided thereat is designed.
  • FIG. 23 is a flowchart illustrating operations of the design device 600 when the semiconductor device 300 of the embodiment 6 is designed.
  • step St 71 semiconductor chip arrangement data and semiconductor chip configuration data are inputted to the input section 71 .
  • the semiconductor chip arrangement data refers to data representing an arrangement relationship when the semiconductor chips A 6 and A 6 ′ are adhered on the semiconductor chip B 6 .
  • the semiconductor chip configuration data refers to data representing the configurations of the semiconductor chips A 6 , A 6 ′ and B 6 .
  • the CPU 72 selects the data and stores the same in the database 73 .
  • step St 72 the CPU 72 searches, from the respective data, the positions that the semiconductor chips A 6 , B 6 and C 6 are to be disposed.
  • step St 73 it is determined whether or not a plurality of semiconductor chips are to be mounted on a semiconductor chip (multi-chip mounting). In a case of the multi-chip mounting as in this embodiment, the process proceeds to step St 74 b . Otherwise, the step proceeds to step St 74 a.
  • step St 74 a the CPU 72 activates the fitting configuration forming section 88 .
  • the fitting configuration forming section 88 determines fitting configuration forming data (coordinates and configurations) used for forming configurations fitting with each other (e.g., the convex portion 43 a and the opening 42 a shown in FIG. 8) at two semiconductor chips when the two semiconductor chips are to be adhered with each other.
  • the fitting configuration forming section 88 makes reference to fitting configuration forming data (in this embodiment, cylindrical convex portion and cylindrical opening) already stored as a default in the database 73 . Then, the process proceeds to step St 75 .
  • step St 74 b the CPU 72 activates the fitting configuration forming section 88 .
  • the fitting configuration forming section 88 calculates fitting configuration data (coordinates and configurations) used for forming configurations fitting with each other (the convex portion 43 a and the opening 42 a , and the convex portion 43 b and the opening 42 b ) on the semiconductor chips when the semiconductor chips are adhered with each other.
  • the fitting configuration forming section 88 makes reference to fitting configuration forming data already stored as a default in the database 73 (in this embodiment, the cylindrical convex portion 43 a and 43 b , and the cylindrical convex portion and the opening portion 42 a and 42 b ). Then, the process proceeds to step St 74 c.
  • step St 74 c the CPU 72 activates the fitting configuration changing section 89 .
  • the fitting configuration changing section 89 changes the fitting configuration forming data obtained in step St 74 b so that mounted semiconductor chips have different configurations.
  • the configuration of fitted portions of the semiconductor chips A 6 and B 6 (cylindrical configuration) is different from that of fitted portions of the semiconductor chips A 6 ′ and B 6 (square pole configuration).
  • step St 75 the CPU 72 produces, on a basis of the fitting configuration forming data, semiconductor chip configuration data representing the configurations of semiconductor chips (in this embodiment, the semiconductor chips A 6 , A 6 ′ and B 6 ).
  • step St 76 the output section 74 outputs the semiconductor chip configuration data.
  • the semiconductor device 300 is designed.
  • the convex portions 43 a are designed on the semiconductor chip A 6
  • the convex portions 43 b are designed on the semiconductor chip A 6 ′
  • the openings 42 a and 42 b are designed on the semiconductor chip B 6 such that when the semiconductor chips A 6 and A 6 ′ are adhered on the semiconductor chip B 6 , the convex portions 43 a are fitted into the openings 42 a and the convex portions 43 b are fitted into the opening portions 42 b .
  • the semiconductor chip A 6 is securely fixed without misalignment when being adhered on the semiconductor chip B 6 together with the semiconductor chip A 6 ′ in a process for manufacturing the semiconductor device 300 .
  • the convex portions 43 a and the opening portions 42 a are designed in a cylindrical configuration.
  • the convex portions 43 b and the opening portions 42 b are designed in a square pole configuration.
  • the convex portions 43 a and the opening portions 42 a are formed in a cylindrical configuration and the convex portion 43 b and the opening portions 42 b are formed in a square pole configuration in this embodiment, the present invention is not limited to such case.
  • the convex portions 43 a and the opening portions 42 a may have any configurations including a star-shaped configuration and a triangular pole configuration.
  • FIG. 24 is a flowchart illustrating operations of the design device 600 when the semiconductor device 300 of the embodiment 6 without the convex portions 43 a and 43 b and the opening portions 42 a and 42 b being provided thereat is designed.
  • FIG. 24 is a flowchart illustrating operations of the design device 600 when the semiconductor device 300 of the embodiment 6 is designed.
  • step St 81 semiconductor chip arrangement data and semiconductor chip configuration data are inputted to the input section 71 .
  • the semiconductor chip arrangement data refers to data representing an arrangement relationship when the semiconductor chips A 6 and A 6 ′ are adhered on the semiconductor chip B 6 .
  • the semiconductor chip configuration data refers to data representing the configurations of the semiconductor chips A 6 , A 6 ′ and B 6 .
  • the CPU 72 selects the data and stores the same in the database 73 .
  • step St 82 the CPU 72 searches, from the respective data, the positions that the semiconductor chips A 6 , B 6 and C 6 are to be disposed.
  • step St 83 it is determined whether or not a plurality of semiconductor chips are to be mounted on a semiconductor chip (multi-chip mounting). In a case of the multi-chip mounting as in this embodiment, the process proceeds to step St 84 b . Otherwise, the step proceeds to step St 84 a.
  • step St 84 a the CPU 72 activates the chip arrangement mark forming section 90 .
  • the chip arrangement mark forming section 90 determines chip arrangement mark forming data (coordinates and configurations) used for forming chip arrangement marks (e.g., the chip arrangement mark 44 a shown in FIG. 8 and the like) serving as a mark used when two semiconductor chips are to be adhered with each other.
  • the chip arrangement mark forming section 90 makes reference to chip arrangement mark forming data (in this embodiment, characters such as L and R) already stored as a default in the database 73 . Then, the process proceeds to step St 85 .
  • step St 84 b the CPU 72 activates the chip arrangement mark forming section 90 .
  • the chip arrangement mark forming section 90 determines chip arrangement mark forming data (coordinates and configurations) used for forming the chip arrangement marks 44 a and 44 b serving as a mark utilized when semiconductor chips are adhered with each other on the semiconductor chips when the semiconductor chips are adhered with each other.
  • the chip arrangement mark forming section 90 makes reference to the chip arrangement mark forming data already stored as a default in the database 73 (in this embodiment, characters such as L and R). Then, the process proceeds to step St 85 .
  • step St 84 c the CPU 72 activates the chip arrangement mark changing section 91 .
  • the chip arrangement mark changing section 91 changes the chip arrangement mark forming data obtained in step St 84 b so that chip arrangement marks are different for each mounted semiconductor chip.
  • the mark on the semiconductor chips A 6 and B 6 (“L” of the chip arrangement mark 44 a ) is different from that on the semiconductor chips A 6 ′ and B 6 (“R” of the chip arrangement mark 44 b ).
  • step St 85 the CPU 72 produces, on a basis of the chip arrangement mark forming data, semiconductor chip configuration data representing the configurations of semiconductor chips (in this embodiment, the semiconductor chips A 6 , A 6 ′ and B 6 ).
  • step St 86 the output section 74 outputs the semiconductor chip configuration data.
  • the semiconductor device 300 is designed.
  • the chip arrangement mark 44 a for disposing the semiconductor chip A 6 is designed at the area on the semiconductor chip B 6 that the semiconductor chip A 6 is to be adhered.
  • the chip arrangement mark 44 b for disposing the semiconductor chip A 6 ′ is designed at the area on the semiconductor chip B 6 that the semiconductor chip A 6 ′ is to be adhered.
  • the semiconductor chip A 6 is seldom mistaken for the semiconductor chip A 6 ′ when being adhered on the semiconductor chip B 6 together with the semiconductor chip A 6 ′ in a process for manufacturing the semiconductor device 300 .
  • FIG. 25 is a flowchart illustrating operations of the design device 600 when the semiconductor chip A 7 of the embodiment 7 is designed.
  • FIG. 25 is a flowchart illustrating operations of the design device 600 when the semiconductor chip A 7 of the embodiment 7 is designed.
  • step St 91 a netlist for the internal circuit of the semiconductor chip A 7 and data of the configuration of the semiconductor chip A 7 are inputted to the input section 71 .
  • the CPU 72 selects the data and stores the same in the database 73 .
  • step St 92 the CPU 72 determines, from the respective data, the positions on the semiconductor chip A 7 that the wire bonding pads 20 and the bump connection pads 30 connected in parallel to the internal circuit are disposed.
  • step St 93 the CPU 72 activates the pad forming section 92 .
  • the pad forming section 92 calculates pad forming data on a basis of the positions of the pads obtained in step St 92 and the pad configuration data stored in advance in the database 73 .
  • step St 94 the CPU 72 produces, on a basis of the pad forming data, semiconductor chip configuration data representing the configuration of the semiconductor chip A 7 .
  • step St 95 the output section 74 outputs the semiconductor chip configuration data.
  • the semiconductor chip A 7 is designed.
  • the semiconductor chip A 7 that comprises the wire bonding pads 20 and the bump connection pads 30 connected in parallel to the internal circuit is designed. Accordingly, wiring for the semiconductor chip A 7 is possible by either wire bonding or bump connection.
  • an optimum connection method for structuring a semiconductor device can be selected depending on sizes of semiconductor chip to be adhered to the semiconductor chip A 7 and wiring rules. Namely, a degree of freedom in designing a semiconductor chip and a semiconductor device is extremely improved.
  • FIG. 26 is a flowchart illustrating operation of the design device 600 when the semiconductor device 500 of the embodiment 8 is designed.
  • step St 101 circuit structure data, inter-circuit connection data and pad position data are inputted to the input section 71 .
  • Circuit structure data refers to data representing the structures of the internal circuits provided respectively within the semiconductor chips A 8 and B 8 and the external circuit that the semiconductor device 500 is connected.
  • Inter-circuit connection data refers to data representing the connection relationship between the internal circuit for the semiconductor chip A 8 , the internal circuit for the semiconductor B 8 and the external circuit.
  • Pad position data refers to data representing the positions of the pads 20 for the semiconductor chip A 8 , the pads 10 for the semiconductor chip B 8 and external pads for the external circuit (leads of lead frame).
  • the CPU 72 selects the data and stores the same in the database 73 .
  • step St 102 the CPU 72 searches, by using the respective data, pads serving as a ground potential when two semiconductor chips are adhered with each other among the pads for the semiconductor chips A 8 and B 8 .
  • step St 103 the CPU 72 activates the wire shield forming section 93 .
  • the wire shield forming section 93 calculates wire shield forming data for forming a wire shield by connecting the pads serving as a ground potential obtained in step St 102 .
  • step St 104 the CPU 72 produces wire bonding performing data for a wire bonding device to perform wire bonding from the wire shield forming data obtained in step St 103 .
  • step St 105 the output section 74 outputs the wire bonding performing data.
  • the semiconductor device 500 is designed.
  • the semiconductor device 500 designed in accordance with this embodiment is provided a shield with a ground potential. For this reason, EMI (Electro Magnetic Interference) can be prevented in the semiconductor device 500 .
  • EMI Electro Magnetic Interference
  • Programs for design methods represented by the flowcharts illustrated in FIGS. 16 to 26 may be recorded in a computer readable recording medium and then be used for designing semiconductor devices with a computer.
  • the programs for design methods represented by the flowcharts illustrated in FIGS. 16 to 26 may be obtained through electronic information communication means and then be used for designing semiconductor devices with a computer. Specifically, the programs are updated in an FTP site. Then, the programs may be downloaded into a computer via an internet and then be used for designing semiconductor devices.
  • the steps described in the embodiment 9 (the steps shown in FIG. 16) serving as procedures are stored in a computer readable recording medium as a program. Then, the semiconductor device 100 a can be automatically designed.
  • Examples of the recording medium include, in addition to a magnetic tape utilizing a magnetic body, a floppy (R) disk, an HDD, a non-volatile memory such as an EEPROM and an optical disk such as a CD or a DVD, and any of them may be used.
  • a semiconductor device which is easily designed and manufactured and in which a plurality of semiconductor chips are integrally structured can be provided.

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US20070241345A1 (en) * 2006-04-14 2007-10-18 High Power Optoelectronics, Inc. Semiconductor light-emitting device and method of fabricating the same
CN100547784C (zh) * 2005-12-16 2009-10-07 晨星半导体股份有限公司 多芯片封装结构的内连线

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