[go: up one dir, main page]

US20010005614A1 - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

Info

Publication number
US20010005614A1
US20010005614A1 US09/741,879 US74187900A US2001005614A1 US 20010005614 A1 US20010005614 A1 US 20010005614A1 US 74187900 A US74187900 A US 74187900A US 2001005614 A1 US2001005614 A1 US 2001005614A1
Authority
US
United States
Prior art keywords
insulating film
film
sacrificed
gas
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/741,879
Other versions
US6287905B2 (en
Inventor
Jeong Kim
Young Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Assigned to HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. reassignment HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KIM, YONG SEO, KIM, JEONG HO
Publication of US20010005614A1 publication Critical patent/US20010005614A1/en
Application granted granted Critical
Publication of US6287905B2 publication Critical patent/US6287905B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31616—Deposition of Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31633—Deposition of carbon doped silicon oxide, e.g. SiOC

Definitions

  • the present invention relates to a method for fabricating a semiconductor device, and in particular to a method for forming a bit line contact and a storage electrode contact for a high integration device, without damaging a device isolating insulating film and a substrate.
  • Resolution (R) of the photoresist film pattern is proportional to a light source wavelength ( ⁇ ) and a process variable (k) of a micro exposure device, and inversely proportional to a numerical aperture (NA) of the exposure device.
  • the wavelength of the light source is decreased.
  • resolution of the G-line and I-line micro exposure devices having wavelengths of 436 nm and 365 nm, respectively, is about 0.7 ⁇ m and 0.5 ⁇ m, respectively.
  • the exposure device using a deep ultraviolet (DUV) light having a small wavelength for example, a KrF laser of 248 nm or an ArF laser of 193 nm, is employed to form a fine pattern below 0.5 ⁇ m.
  • a method for using a phase shift mask as a photo mask has been suggested.
  • a contrast enhancement layer (CEL) method for forming a thin film on a wafer has been suggested for enhancing an image contrast.
  • a tri layer resist (TLR) method has been suggested for positioning an intermediate layer, such as a spin on glass (SOG) film between two photoresist films.
  • a silylation method has been suggested for selectively implanting a silicon into an upper portion of a photoresist film.
  • a size of a contact hole, which connects the upper and lower conductive interconnections, and a space between the contact hole and an adjacent interconnection are decreased, and an aspect ratio of the contact hole is increased.
  • the high integration semiconductor device having multi-layer conductive interconnections requires precise mask alignment in a contact formation process, thereby reducing a process margin.
  • masks are formed in consideration: of misalignment tolerance in a mask alignment, lens distortion in an exposure process, critical dimension variations in mask formation and photoetching processes, and mask registration.
  • the SAC method may use a polycrystalline silicon layer, a nitride film or an oxide nitride film as an etching barrier film.
  • the nitride film is employed as the etching barrier film.
  • a substructure consisting of, for example, a device isolating insulating film, a gate insulating film and a metal-oxide semiconductor field effect transistor (MOSFET) having a gate electrode overlapped with a mask oxide film pattern, and source/drain regions are formed on a semiconductor substrate.
  • MOSFET metal-oxide semiconductor field effect transistor
  • An etching barrier film and an interlayer insulating film consisting of an oxide film are sequentially formed over the entire structure.
  • a photoresist film pattern is formed to expose the interlayer insulating film in a presumed region of a storage electrode contact or bit line contact on the semiconductor substrate.
  • the interlayer insulating film exposed by the photoresist film pattern is dry-etched to expose the etching barrier film. Then, a contact hole is formed by etching the etching barrier film.
  • the T type mask has a sufficient misalignment margin of the bit line contact.
  • the contact hole has a sloped section in the storage electrode contact formation region due to misalignment and the contact oxide film etching process, and thus the contact region is difficult to obtain. Accordingly, this method cannot be applied to a device below 0.13 ⁇ m.
  • the I type mask etches the oxide film by shifting a device isolating mask on the device isolating insulating film.
  • an etching area is wider than a mask area, and thus a high selection ratio for a nitride film is hardly obtained.
  • the etching area has to be much smaller than the non-etching area in order to obtain the high selection ratio for the nitride film in the oxide film etching process.
  • the etching area is wider than the non-etching area, a polymer cannot sufficiently protect the nitride film.
  • the active region is exposed to the plasma and damaged in the oxide film etching process, and thus increases a resistance of the contact and a current leakage.
  • the present invention provides a method for fabricating a semiconductor device, the method including: forming a device isolating insulating film for defining an active region on a semiconductor substrate; forming a gate insulating film at the upper portion of the resultant structure; forming a gate electrode overlapped with a mask insulating film pattern at the upper portion of the gate insulating film; forming insulating film spacers at the side walls of the gate electrode and the mask insulating film pattern; forming source/drain regions on the semiconductor substrate at both sides of the insulating film spacers; forming a device isolating insulating film protective film at the upper portion of the resultant structure; forming a sacrificed insulating film at the upper portion of the resultant structure; forming an I type photoresist film pattern for protecting the presumed portion of a bit line contact and a storage electrode contact at the upper portion of the sacrificed insulating film; forming a sacrificed insulating film pattern by etching the sacrificed
  • FIG. 1 is a layout diagram of a semiconductor device in accordance with the present invention.
  • FIGS. 2A through 2I are cross-sectional diagrams illustrating sequential steps of a method for fabricating the semiconductor device, taken along line X-X′ in FIG. 1.
  • FIG. 1 is a layout diagram of the semiconductor device in accordance with an exemplary embodiment.
  • a device isolating insulating film 13 , active region 14 and gate electrode 15 are formed.
  • an I type photoresist film pattern 25 for exposing the whole region in an I type, except a presumed contact region, is formed.
  • a portion indicated by the I type photoresist film pattern 25 is exposed.
  • a sacrificed insulating film is etched therein.
  • FIGS. 2A through 2I are cross-sectional diagrams of FIG. 1, taken along line X-X′ illustrating sequential steps of a method for fabricating the semiconductor device.
  • the device isolating insulating film 13 is formed in a presumed device isolating region on a semiconductor substrate 11 .
  • a gate insulating film (not shown) is formed at the upper portion of the resultant structure, and a stacked structure of a gate electrode conductive layer (not shown) and a mask insulating film (not shown) is formed at the upper portion of the gate insulating film.
  • the gate electrode 15 and the mask insulating film pattern 17 are formed by etching the stacked structure by using a gate electrode mask as an etching mask.
  • the mask insulating film pattern 17 comprises at least one of SiN film, SiON film and an SRON film containing a large amount of Si (hereinafter, referred to as ‘SRON film’) .
  • the etching process is performed by using a mixed gas of CF 4 , O 2 and Ar or a mixed gas of CHF 3 , O 2 and Ar, thereby forming the etching surface in a vertical shape.
  • Insulating film spacers 19 are formed at the sidewalls of the gate electrode 15 and the mask insulating film pattern 17 by etching the insulating film.
  • the insulating film spacers 19 may comprise an SiN film.
  • a lightly-doped impurity is ion-implanted into the semiconductor substrate 11 at both sides of the insulating film spacers 19 , thereby forming source/drain regions (not shown).
  • a device isolating insulating film protective film 21 having a predetermined thickness, is formed at the upper portion of the resultant structure.
  • the device isolating insulating film protective film 21 is selected from the group consisting of SiN film, SiON film, Al 2 O 3 film, Ta 2 O 5 film, SiOCH film or SiCH film so that the device isolating insulating film cannot be damaged in the etching process for forming a contact hole.
  • a sacrificed insulating film 23 is formed at the upper portion of the resultant structure.
  • the sacrificed insulating film 23 comprises a doped oxide film having an etching selection ratio difference from the device isolating insulating film protective film 21 , such as a PSG film, BPSG film or advanced planarization layer (APL).
  • the I type photoresist film pattern 25 for exposing the whole region in an I type, except the presumed contact region of the bit line and storage electrode is formed at the upper portion of the sacrificed insulating film 23 .
  • a sacrificed insulating film pattern 25 for protecting a presumed contact region is formed, by etching the sacrificed insulating film 23 using the I type photoresist film pattern 25 as an etching mask.
  • the sacrificed insulating film 23 may be etched by employing a perfluorocarbon containing gas producing a large amount of polymers, the gas being selected from the group consisting of C 2 F 6 , C 2 F 4 , C 3 F 6 , C 3 F 8 , C 4 F 6 , C 4 F 8 , C 5 F 8 , C 5 F 10 or C 2 HF 5 , or a mixed gas of the perfluorocarbon containing gas and a hydrogen containing gas such as CHF 3 , CH 3 F, CH 2 F 2 , CH 2 , CH 4 , C 2 H 4 and H 2 .
  • a perfluorocarbon containing gas producing a large amount of polymers
  • the gas being selected from the group consisting of C 2 F 6 , C 2 F 4 , C 3 F 6 , C 3 F 8 , C 4 F 6 , C 4 F 8 , C 5 F 8 , C 5 F 10 or C 2 HF 5
  • the etching process may be performed by adding an inert gas such as He, Ne, Ar or Xe into the perfluorocarbon containing gas and the mixed gas.
  • an inert gas such as He, Ne, Ar or Xe
  • the etching process may be performed by using CxHyFz gas (X ⁇ 2, y ⁇ 2, z ⁇ 2) as an etching gas, to thereby obtain a high selection ratio in regard to the mask insulating film pattern 17 and the insulating film spacer 19 .
  • the etching process may be carried out by employing a mixed gas as an etching gas, the mixed gas comprising the CxHyFz gas(X ⁇ 2, y ⁇ 2, z ⁇ 2) and the inert gas.
  • an interlayer insulating film 27 for isolating devices is formed at the upper portion of the resultant structure.
  • the interlayer insulating film 27 is selected from the group consisting of an undoped oxide film (such as, e.g., a low temperature oxide film, middle temperature oxide film, high temperature oxide film, tetra ethyl ortho silicate glass (TEOS) oxide film or high density plasma), undoped silicate glass (USG) film, an SiN film, and an SiON film, and combinations thereof.
  • an undoped oxide film such as, e.g., a low temperature oxide film, middle temperature oxide film, high temperature oxide film, tetra ethyl ortho silicate glass (TEOS) oxide film or high density plasma
  • undoped silicate glass (USG) film such as, e.g., a low temperature oxide film, middle temperature oxide film, high temperature oxide film, tetra ethyl ortho silicate glass (TEOS) oxide film or high density plasma
  • USG undoped
  • the interlayer insulating film 27 is etched according to a chemical mechanical polishing (CMP) process or whole surface etching process.
  • CMP chemical mechanical polishing
  • the sacrificed insulating film pattern 24 is used as an etching barrier.
  • the sacrificed insulating film pattern 24 is etched by using the etching selection ratio difference between the sacrificed insulating film pattern 24 and the interlayer insulating film pattern 28 .
  • the etching process is a wet etching process using a mixed solution of HF and deionized water, or a mixed solution of NH 4 OH, HF and deionized water.
  • the etching process may be an isotropic dry etching process using a mixed gas as an etching gas, the mixed gas comprising a main etching gas (such as CF 4 , SF 6 , NF 3 or C 2 F 6 ), an oxygen containing gas (such as O 2 , CO 2 , CO or SO 2 ), and an inert gas (such as He, Ne, Ar or Xe).
  • a mixed gas as an etching gas
  • the mixed gas comprising a main etching gas (such as CF 4 , SF 6 , NF 3 or C 2 F 6 ), an oxygen containing gas (such as O 2 , CO 2 , CO or SO 2 ), and an inert gas (such as He, Ne, Ar or Xe).
  • the device isolating insulating film protective film 21 exposed to the interlayer insulating film pattern 28 is removed by using a mixed gas of the main etching gas (such as CF 4 , SF 6 , NF 3 or C 2 F 6 ), the oxygen containing gas (such as O 2 , CO 2 , CO or SO 2 ), and the inert gas (such as He, Ne, Ar or Xe), and by using a low bias power. Accordingly, a damage on the semiconductor substrate 11 is minimized.
  • a mixed gas of the main etching gas such as CF 4 , SF 6 , NF 3 or C 2 F 6
  • the oxygen containing gas such as O 2 , CO 2 , CO or SO 2
  • the inert gas such as He, Ne, Ar or Xe
  • a conductive layer 29 is formed at the upper portion of the resultant structure.
  • the conductive layer 29 comprises a polysilicon layer, a tungsten film, a selectively-formed tungsten film or a silicon layer formed according to a selective epitaxial growth (SEG) method.
  • SEG selective epitaxial growth
  • a contact plug 30 is formed by removing the conductive layer 29 and the interlayer insulating film pattern 28 according to the CMP process so that the mask insulating film pattern 17 can be exposed.
  • the conductive layer 29 comprises the selectively-formed tungsten film or the silicon layer formed according to the SEG method
  • the CMP process can be skipped.
  • the MOSFET is formed, the device isolating insulating film protective film is formed at the upper portion of the resultant structure, the sacrificed insulating film pattern is formed at the upper portion of the contact region, the interlayer insulating film is formed and etched according to the CMP process to expose the sacrificed insulating film pattern, the device isolating insulating film protective film formed in the contact region is removed, and the contact plug is formed.
  • the etching process for exposing the contact region is performed on the device isolating insulating film, thereby preventing damage of the semiconductor substrate, improving the contact property, and restricting current leakage due to the damaged device isolating insulating film. Moreover, a margin for the misalignment is increased, and thus the device property and yield are improved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)

Abstract

The present invention discloses a method for fabricating a semiconductor device. In a process for forming a bit line contact plug and storage electrode contact plug for the high integration semiconductor device, a MOSFET is formed, a device isolating insulating film protective film is formed at the upper portion of the resultant structure, a sacrificed insulating film pattern is formed at the upper portion of a contact region, an interlayer insulating film is formed and etched according to the CMP process to expose the sacrificed insulating film pattern, the device isolating insulating film protective film formed in the contact region is removed, and a contact plug is formed. That is, the etching process for exposing the contact region is performed on a device isolating insulating film, thereby preventing damage of the semiconductor substrate, improving a contact property, and restricting current leakage due to the damaged device isolating insulating film. Moreover, a margin for the misalignment is increased, and as a result device property and yield are improved.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to a method for fabricating a semiconductor device, and in particular to a method for forming a bit line contact and a storage electrode contact for a high integration device, without damaging a device isolating insulating film and a substrate. [0002]
  • 2. Description of the Background Art [0003]
  • Recently, the high integration of a semiconductor device has been remarkably influenced by the development of techniques for forming a fine pattern. In a method for fabricating the semiconductor device, it is essential to miniaturize a photoresist film pattern used as a mask in an etching or ion implantation process. [0004]
  • Resolution (R) of the photoresist film pattern is proportional to a light source wavelength (λ) and a process variable (k) of a micro exposure device, and inversely proportional to a numerical aperture (NA) of the exposure device. [0005]
  • R=k*λ/NA
  • Here, in order to improve optical resolution of the micro exposure device, the wavelength of the light source is decreased. For example, resolution of the G-line and I-line micro exposure devices, having wavelengths of 436 nm and 365 nm, respectively, is about 0.7 μm and 0.5 μm, respectively. Accordingly, the exposure device using a deep ultraviolet (DUV) light having a small wavelength, for example, a KrF laser of 248 nm or an ArF laser of 193 nm, is employed to form a fine pattern below 0.5 μm. In addition, in order to improve the resolution, a method for using a phase shift mask as a photo mask has been suggested. A contrast enhancement layer (CEL) method for forming a thin film on a wafer has been suggested for enhancing an image contrast. A tri layer resist (TLR) method has been suggested for positioning an intermediate layer, such as a spin on glass (SOG) film between two photoresist films. And a silylation method has been suggested for selectively implanting a silicon into an upper portion of a photoresist film. [0006]
  • According to the high integration of the semiconductor device, a size of a contact hole, which connects the upper and lower conductive interconnections, and a space between the contact hole and an adjacent interconnection are decreased, and an aspect ratio of the contact hole is increased. [0007]
  • Thus, the high integration semiconductor device having multi-layer conductive interconnections requires precise mask alignment in a contact formation process, thereby reducing a process margin. [0008]
  • In order to maintain a space between the contact holes, masks are formed in consideration: of misalignment tolerance in a mask alignment, lens distortion in an exposure process, critical dimension variations in mask formation and photoetching processes, and mask registration. [0009]
  • In addition, there has been taught a self aligned contact (SAC) method for forming a contact hole according to a self alignment method to overcome a disadvantage of a lithography process. [0010]
  • The SAC method may use a polycrystalline silicon layer, a nitride film or an oxide nitride film as an etching barrier film. In general, the nitride film is employed as the etching barrier film. [0011]
  • Although not illustrated, the conventional SAC method for fabricating the semiconductor device will now be described. [0012]
  • Firstly, a substructure consisting of, for example, a device isolating insulating film, a gate insulating film and a metal-oxide semiconductor field effect transistor (MOSFET) having a gate electrode overlapped with a mask oxide film pattern, and source/drain regions are formed on a semiconductor substrate. An etching barrier film and an interlayer insulating film consisting of an oxide film are sequentially formed over the entire structure. [0013]
  • Thereafter, a photoresist film pattern is formed to expose the interlayer insulating film in a presumed region of a storage electrode contact or bit line contact on the semiconductor substrate. [0014]
  • The interlayer insulating film exposed by the photoresist film pattern is dry-etched to expose the etching barrier film. Then, a contact hole is formed by etching the etching barrier film. [0015]
  • In the conventional SAC method for fabricating the semiconductor device, when the bit line contact and the storage electrode contact for a device below 0.15 μm are formed, a general circular contact cannot obtain a contact region due to misalignment in the lithography. In order to overcome such a disadvantage, there has been taught a method for forming a conductive layer by etching the oxide film by using the photoresist film pattern for exposing the contact region in a T or I type as an etching mask, and forming a plug by chemical mechanical polishing (CMP) the conductive layer. [0016]
  • The T type mask has a sufficient misalignment margin of the bit line contact. However, the contact hole has a sloped section in the storage electrode contact formation region due to misalignment and the contact oxide film etching process, and thus the contact region is difficult to obtain. Accordingly, this method cannot be applied to a device below 0.13 μm. [0017]
  • In addition, the I type mask etches the oxide film by shifting a device isolating mask on the device isolating insulating film. Here, an etching area is wider than a mask area, and thus a high selection ratio for a nitride film is hardly obtained. [0018]
  • The etching area has to be much smaller than the non-etching area in order to obtain the high selection ratio for the nitride film in the oxide film etching process. When the etching area is wider than the non-etching area, a polymer cannot sufficiently protect the nitride film. [0019]
  • Moreover, since the etching process using the T type mask or I type mask is performed in the active region of the semiconductor substrate, the active region is exposed to the plasma and damaged in the oxide film etching process, and thus increases a resistance of the contact and a current leakage. [0020]
    • SUMMARY OF THE INVENTION
  • Therefore, there is a need to to provide a method for fabricating a semiconductor device which can form a contact plug by forming a device isolating insulating film protective film at the upper portion of a device isolating insulating film, forming a sacrificed insulating film pattern for exposing the device isolating insulating film in an I type for insulation between contact plugs, filling the exposed portion by forming an interlayer insulating film for insulating devices, removing the sacrificed insulating film pattern, and forming a conductive layer in the region where the sacrificed insulating film has been removed. [0021]
  • Accordingly, the present invention provides a method for fabricating a semiconductor device, the method including: forming a device isolating insulating film for defining an active region on a semiconductor substrate; forming a gate insulating film at the upper portion of the resultant structure; forming a gate electrode overlapped with a mask insulating film pattern at the upper portion of the gate insulating film; forming insulating film spacers at the side walls of the gate electrode and the mask insulating film pattern; forming source/drain regions on the semiconductor substrate at both sides of the insulating film spacers; forming a device isolating insulating film protective film at the upper portion of the resultant structure; forming a sacrificed insulating film at the upper portion of the resultant structure; forming an I type photoresist film pattern for protecting the presumed portion of a bit line contact and a storage electrode contact at the upper portion of the sacrificed insulating film; forming a sacrificed insulating film pattern by etching the sacrificed insulating film by using the I type photoresist film pattern as an etching mask; forming an interlayer insulating film at the upper portion of the resultant structure; forming an interlayer insulating film pattern filled between the sacrificed insulating film patterns, by etching the interlayer insulating film; exposing the device isolating insulating film protective film, by removing the sacrificed insulating film pattern by using an etching selection ratio difference from the interlayer insulating film pattern; exposing a contact region of the semiconductor substrate, by removing the device isolating insulating film protective film by using the etching selection ratio difference from the interlayer insulating film pattern; forming a conductive layer at the upper portion of the resultant structure; and forming a contact plug by removing the conductive layer and the interlayer insulating film pattern according to a chemical mechanical polishing process employing the mask insulating film pattern as an etching barrier. [0022]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention will become better understood with reference to the accompanying drawings which are given only by way of illustration and thus are not limitative of the present invention, wherein: [0023]
  • FIG. 1 is a layout diagram of a semiconductor device in accordance with the present invention; and [0024]
  • FIGS. 2A through 2I are cross-sectional diagrams illustrating sequential steps of a method for fabricating the semiconductor device, taken along line X-X′ in FIG. 1. [0025]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • A method for fabricating a semiconductor device in accordance with the present invention will now be described in detail with reference to the accompanying drawings. [0026]
  • FIG. 1 is a layout diagram of the semiconductor device in accordance with an exemplary embodiment. A device isolating [0027] insulating film 13, active region 14 and gate electrode 15 are formed. In addition, an I type photoresist film pattern 25 for exposing the whole region in an I type, except a presumed contact region, is formed. Here, a portion indicated by the I type photoresist film pattern 25 is exposed. A sacrificed insulating film is etched therein.
  • FIGS. 2A through 2I are cross-sectional diagrams of FIG. 1, taken along line X-X′ illustrating sequential steps of a method for fabricating the semiconductor device. [0028]
  • As illustrated in FIG. 2A, the device isolating [0029] insulating film 13 is formed in a presumed device isolating region on a semiconductor substrate 11.
  • A gate insulating film (not shown) is formed at the upper portion of the resultant structure, and a stacked structure of a gate electrode conductive layer (not shown) and a mask insulating film (not shown) is formed at the upper portion of the gate insulating film. [0030]
  • The [0031] gate electrode 15 and the mask insulating film pattern 17 are formed by etching the stacked structure by using a gate electrode mask as an etching mask. Here, the mask insulating film pattern 17 comprises at least one of SiN film, SiON film and an SRON film containing a large amount of Si (hereinafter, referred to as ‘SRON film’) . The etching process is performed by using a mixed gas of CF4, O2 and Ar or a mixed gas of CHF3, O2 and Ar, thereby forming the etching surface in a vertical shape.
  • Thereafter, an insulating film is formed at the upper portion of the resultant structure. Insulating [0032] film spacers 19 are formed at the sidewalls of the gate electrode 15 and the mask insulating film pattern 17 by etching the insulating film. The insulating film spacers 19 may comprise an SiN film.
  • Although not illustrated, a lightly-doped impurity is ion-implanted into the [0033] semiconductor substrate 11 at both sides of the insulating film spacers 19, thereby forming source/drain regions (not shown).
  • Referring to FIG. 2B, a device isolating insulating film [0034] protective film 21, having a predetermined thickness, is formed at the upper portion of the resultant structure. Here, the device isolating insulating film protective film 21 is selected from the group consisting of SiN film, SiON film, Al2O3 film, Ta2O5 film, SiOCH film or SiCH film so that the device isolating insulating film cannot be damaged in the etching process for forming a contact hole.
  • A sacrificed insulating [0035] film 23 is formed at the upper portion of the resultant structure. The sacrificed insulating film 23 comprises a doped oxide film having an etching selection ratio difference from the device isolating insulating film protective film 21, such as a PSG film, BPSG film or advanced planarization layer (APL).
  • As shown in FIG. 2C, the I type [0036] photoresist film pattern 25 for exposing the whole region in an I type, except the presumed contact region of the bit line and storage electrode is formed at the upper portion of the sacrificed insulating film 23.
  • As depicted in FIG. 2D, a sacrificed insulating [0037] film pattern 25 for protecting a presumed contact region is formed, by etching the sacrificed insulating film 23 using the I type photoresist film pattern 25 as an etching mask.
  • The sacrificed insulating [0038] film 23 may be etched by employing a perfluorocarbon containing gas producing a large amount of polymers, the gas being selected from the group consisting of C2F6, C2F4, C3F6, C3F8, C4F6, C4F8, C5F8, C5F10 or C2HF5, or a mixed gas of the perfluorocarbon containing gas and a hydrogen containing gas such as CHF3, CH3F, CH2F2, CH2, CH4, C2H4 and H2. In addition, the etching process may be performed by adding an inert gas such as He, Ne, Ar or Xe into the perfluorocarbon containing gas and the mixed gas. As a result, the plasma stability and sputtering effects are improved, and thus the etch stop phenomenon is overcome, thereby performing a reproducible etching process. The etching process may be performed by using CxHyFz gas (X≧2, y≧2, z≧2) as an etching gas, to thereby obtain a high selection ratio in regard to the mask insulating film pattern 17 and the insulating film spacer 19. The etching process may be carried out by employing a mixed gas as an etching gas, the mixed gas comprising the CxHyFz gas(X≧2, y≧2, z≧2) and the inert gas.
  • Thereafter, the I type [0039] photoresist film pattern 25 is removed.
  • As illustrated in FIG. 2E, an [0040] interlayer insulating film 27 for isolating devices is formed at the upper portion of the resultant structure. In order to have the etching selection ratio difference from the sacrificed insulating film pattern 24, the interlayer insulating film 27 is selected from the group consisting of an undoped oxide film (such as, e.g., a low temperature oxide film, middle temperature oxide film, high temperature oxide film, tetra ethyl ortho silicate glass (TEOS) oxide film or high density plasma), undoped silicate glass (USG) film, an SiN film, and an SiON film, and combinations thereof.
  • As depicted in FIG. 2F, the [0041] interlayer insulating film 27 is etched according to a chemical mechanical polishing (CMP) process or whole surface etching process. The sacrificed insulating film pattern 24 is used as an etching barrier.
  • Referring to FIG. 2G, the sacrificed insulating [0042] film pattern 24 is etched by using the etching selection ratio difference between the sacrificed insulating film pattern 24 and the interlayer insulating film pattern 28. The etching process is a wet etching process using a mixed solution of HF and deionized water, or a mixed solution of NH4OH, HF and deionized water. In addition, the etching process may be an isotropic dry etching process using a mixed gas as an etching gas, the mixed gas comprising a main etching gas (such as CF4, SF6, NF3 or C2F6), an oxygen containing gas (such as O2, CO2, CO or SO2), and an inert gas (such as He, Ne, Ar or Xe).
  • Thereafter, the device isolating insulating film [0043] protective film 21 exposed to the interlayer insulating film pattern 28 is removed by using a mixed gas of the main etching gas (such as CF4, SF6, NF3 or C2F6), the oxygen containing gas (such as O2, CO2, CO or SO2), and the inert gas (such as He, Ne, Ar or Xe), and by using a low bias power. Accordingly, a damage on the semiconductor substrate 11 is minimized.
  • As illustrated in FIG. 2H, a [0044] conductive layer 29 is formed at the upper portion of the resultant structure. The conductive layer 29 comprises a polysilicon layer, a tungsten film, a selectively-formed tungsten film or a silicon layer formed according to a selective epitaxial growth (SEG) method.
  • As depicted in FIG. 2I, a [0045] contact plug 30 is formed by removing the conductive layer 29 and the interlayer insulating film pattern 28 according to the CMP process so that the mask insulating film pattern 17 can be exposed. Here, when the conductive layer 29 comprises the selectively-formed tungsten film or the silicon layer formed according to the SEG method, the CMP process can be skipped.
  • As discussed earlier, in accordance with the present invention, in the process for forming the bit line contact plug and storage electrode contact plug for the high integration semiconductor device, the MOSFET is formed, the device isolating insulating film protective film is formed at the upper portion of the resultant structure, the sacrificed insulating film pattern is formed at the upper portion of the contact region, the interlayer insulating film is formed and etched according to the CMP process to expose the sacrificed insulating film pattern, the device isolating insulating film protective film formed in the contact region is removed, and the contact plug is formed. That is, the etching process for exposing the contact region is performed on the device isolating insulating film, thereby preventing damage of the semiconductor substrate, improving the contact property, and restricting current leakage due to the damaged device isolating insulating film. Moreover, a margin for the misalignment is increased, and thus the device property and yield are improved. [0046]
  • As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiment is not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims. [0047]

Claims (20)

What is claimed is:
1. A method for fabricating a semiconductor device, the method comprising:
forming a device isolating insulating film for defining an active region on a semiconductor substrate;
forming a gate insulating film at the upper portion of the resultant structure;
forming a gate electrode overlapped with a mask insulating film pattern at the upper portion of the gate insulating film;
forming insulating film spacers at the side walls of the gate electrode and the mask insulating film pattern;
forming source/drain regions on the semiconductor substrate at both sides of the insulating film spacers;
forming a device isolating insulating film protective film at the upper portion of the resultant structure;
forming a sacrificed insulating film at the upper portion of the resultant structure;
forming a photoresist film pattern for exposing the whole region in an I type, except the presumed portion of a bit line contact and a storage electrode contact at the upper portion of the sacrificed insulating film;
forming a sacrificed insulating film pattern by etching the sacrificed insulating film by using the photoresist film pattern as an etching mask;
removing the photoresist film pattern;
forming an interlayer insulating film at the upper portion of the resultant structure;
forming an interlayer insulating film pattern filled between the sacrificed insulating film patterns, by etching the interlayer insulating film;
exposing the device isolating insulating film protective film, by removing the sacrificed insulating film pattern by using an etching selection ratio difference from the interlayer insulating film pattern;
exposing a contact region of the semiconductor substrate, by removing the device isolating insulating film protective film by using the etching selection ratio difference from the interlayer insulating film pattern;
forming a conductive layer at the upper portion of the resultant structure; and
forming a contact plug by removing the conductive layer and the interlayer insulating film pattern according to a chemical mechanical polishing process employing the mask insulating film pattern as an etching barrier.
2. The method according to
claim 1
, wherein the mask insulating film pattern is selected from the group consisting of SiN film, SiON film, Al2O3 film, Ta2O5 film, SiOCH film, SiCH film, and combinations thereof.
3. The method according to
claim 1
, wherein the insulating film spacers comprise an SiN film.
4. The method according to
claim 1
, wherein the device isolating insulating film protective film is formed by using a thin film having an etching selection ratio difference from the device isolating insulating film, and is selected from the group consisting of an SiN film, SiON film, Al2O3 film, Ta2O5 film, SiOCH film, SiCH film, and combinations thereof.
5. The method according to
claim 1
, wherein the sacrificed insulating film comprises a doped oxide film selected from the group consisting of a PSG film, BPSG film, advanced planarization layer(APL), and combinations thereof, which have an etching selection ratio difference from the device isolating insulating film protective film.
6. The method according to
claim 1
, wherein the sacrificed insulating film is etched by employing a perfluorocarbon containing gas causing a large amount of polymers, the perfluorocarbon containing gas and being selected from the group consisting of C2F6, C2F4, C3F6, C3F8, C4F6, C4F8, C5F8, C5F10, C2HF5, and combinations thereof, in order to have a high selection ratio in regard to the mask insulating film pattern and the insulating film spacers.
7. The method according to
claim 1
 or
6
, wherein the sacrificed insulating film is etched by using a mixed gas of the perfluorocarbon containing gas and an inert gas as an etching gas.
8. The method according to
claim 1
 or
6
, wherein the sacrificed insulating film is etched by using a mixed gas as an etching gas, the mixed gas comprising of the perfluorocarbon containing gas and a hydrogen containing gas.
9. The method according to
claim 8
, wherein the hydrogen containing gas is selected from the group consisting of CHF3, CH3F, CH2F2, CH2, CH4, C2H4, H2, and combinations thereof.
10. The method according to
claim 8
, wherein the sacrificed insulating film is etched by using a as an etching gas, the gas mixture comprising the mixed gas and an inert gas.
11. The method according to
claim 1
, wherein the sacrificed insulating film is etched by using CxHyFz gas(X≧2, y≧2, z≧2) as an etching gas, to obtain a high selection ratio in regard to the mask insulating film pattern and the insulating film spacer.
12. The method according to
claim 11
, wherein the sacrificed insulating film is etched by using a mixed gas as an etching gas, the mixed gas comprising the CxHyFz gas(X≧2, y≧2, z≧2) and an inert gas.
13. The method according to
claim 1
, wherein the interlayer insulating film is selected from the group consisting of an undoped oxide film, undoped silicate glass (USG) film, an SiN film, an SiON film, and combinations thereof, which have an etching selection ratio to the sacrificed insulating film.
14. The method according to
claim 13
, wherein the undoped oxide film comprises at least one of 2 low temperatureoxide film, 2 middle temperature oxide film, a high temperature oxide film, a tetraethylortho silicate glass (TEOS) oxide film, and a high density plasma.
15. The method according to
claim 1
, wherein the sacrificed insulating film pattern is removed according to a wet etching process using a mixed solution as an etchant, the mixed solution comprising HF and deionized water.
16. The method according to
claim 1
, wherein the sacrificed insulating film patterns is removed according to a wet etching process using a mixed solution as an etchant, the mixed solution comprising NH4OH, HF and deionized water.
17. The method according to
claim 1
, wherein the sacrificed insulating film pattern is removed according to an isotropic dry etching process using a mixed gas as an etching gas, the mixed gas comprising a main etching gas selected from the group consisting of CF4, SF6, NF3, C2F6 and combinations thereof, an oxygen containing gas and an inert gas.
18. The method according to
claim 1
, wherein the device isolating insulating film protective film is removed by using a mixed gas as an etching gas, the mixed gas comprising a main etching gas selected from the group consisting of CF4, SF6, NF3, C2F6 and combinations thereof, an oxygen containing gas and an inert gas.
19. The method according to
claim 1
, wherein the conductive layer comprises at least one of a polysilicon layer, a tungsten film, a selectively-formed tungsten film and a silicon layer formed according to a selective epitaxial growth method.
20. The method according to
claim 1
 or
19
, wherein a succeeding chemical mechanical polishing process is skipped when the conductive layer comprises at least one of the selectively-formed tungsten film and the silicon layer formed according to the selective epitaxial growth method.
US09/741,879 1999-12-24 2000-12-22 Method for fabricating semiconductor device Expired - Fee Related US6287905B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR99-61849 1999-12-24
KR10-1999-0061849A KR100474546B1 (en) 1999-12-24 1999-12-24 Fabricating method for semiconductor device
KR1999-61849 1999-12-24

Publications (2)

Publication Number Publication Date
US20010005614A1 true US20010005614A1 (en) 2001-06-28
US6287905B2 US6287905B2 (en) 2001-09-11

Family

ID=19629415

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/741,879 Expired - Fee Related US6287905B2 (en) 1999-12-24 2000-12-22 Method for fabricating semiconductor device

Country Status (3)

Country Link
US (1) US6287905B2 (en)
JP (1) JP2001230387A (en)
KR (1) KR100474546B1 (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003052808A2 (en) * 2001-12-13 2003-06-26 Applied Materials, Inc. Self-aligned contact etch with high sensitivity to nitride shoulder
US6703314B2 (en) * 2001-12-14 2004-03-09 Hynix Semiconductor Inc. Method for fabricating semiconductor device
US20050218373A1 (en) * 2001-08-30 2005-10-06 Kei-Yu Ko Etching methods
US20060017116A1 (en) * 2004-07-26 2006-01-26 Seok-Su Kim Semiconductor device and method for manufacturing the same
US20070044545A1 (en) * 2005-08-19 2007-03-01 Arthur Beyder Oscillator and method of making for atomic force microscope and other applications
US20070275553A1 (en) * 2006-05-25 2007-11-29 Elpida Memory, Inc. Method for manufacturing semiconductor device
DE10229346B4 (en) * 2001-06-29 2009-09-24 Hynix Semiconductor Inc., Icheon Process for producing a semiconductor element
US20110159677A1 (en) * 2009-12-30 2011-06-30 Hynix Semiconductor Inc. Method of fabricating landing plug contact in semiconductor memory device
CN102637629A (en) * 2011-02-14 2012-08-15 旺宏电子股份有限公司 Reduced number of mask combinations and methods for IC devices with stacked contact layers
CN107924844A (en) * 2016-03-24 2018-04-17 东京毅力科创株式会社 Manufacturing method of semiconductor device
CN117677192A (en) * 2024-01-31 2024-03-08 合肥晶合集成电路股份有限公司 Method for manufacturing semiconductor device and semiconductor device

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6602434B1 (en) * 1998-03-27 2003-08-05 Applied Materials, Inc. Process for etching oxide using hexafluorobutadiene or related fluorocarbons and manifesting a wide process window
KR100341663B1 (en) * 1999-09-27 2002-06-24 윤종용 Method of forming bit line contact holes in a semiconductor device with reduced photolithography process
KR100527577B1 (en) * 1999-12-24 2005-11-09 주식회사 하이닉스반도체 Fabricating method for semiconductor device
US6432318B1 (en) * 2000-02-17 2002-08-13 Applied Materials, Inc. Dielectric etch process reducing striations and maintaining critical dimensions
KR100390838B1 (en) * 2001-06-28 2003-07-12 주식회사 하이닉스반도체 Method for forming landing plug contact in semiconductor device
KR100704469B1 (en) * 2001-12-14 2007-04-09 주식회사 하이닉스반도체 Semiconductor device manufacturing method
KR20030058584A (en) * 2001-12-31 2003-07-07 주식회사 하이닉스반도체 A method for forming a contact of a semiconductor device
KR100465835B1 (en) * 2002-06-29 2005-01-13 주식회사 하이닉스반도체 Method for fabricating semiconductor device
US7541270B2 (en) * 2002-08-13 2009-06-02 Micron Technology, Inc. Methods for forming openings in doped silicon dioxide
DE10314274B3 (en) * 2003-03-29 2004-09-16 Infineon Technologies Ag Production of a first contact perforated surface in a storage device having storage cells comprises preparing a semiconductor substrate with an arrangement of gate electrode strips on the semiconductor surface, and further processing
DE10332600B3 (en) * 2003-07-17 2005-04-14 Infineon Technologies Ag Method for producing an electrically conductive contact
DE102004019786B3 (en) * 2004-04-23 2005-09-01 Infineon Technologies Ag Production of a first contact hole of a memory component comprises forming a semiconductor substrate having a cell field region and a logic region, producing an insulating layer on the semiconductor surface, and further processing
KR100538101B1 (en) * 2004-07-07 2005-12-21 삼성전자주식회사 Semiconductor device and method of manufacturing for the same
KR100602093B1 (en) * 2004-07-26 2006-07-19 동부일렉트로닉스 주식회사 Semiconductor device and manufacturing method
KR100695431B1 (en) * 2005-06-22 2007-03-15 주식회사 하이닉스반도체 Contact hole formation method of semiconductor device
US20100084709A1 (en) * 2005-07-05 2010-04-08 Ryuta Tsuchiya Semiconductor device and method for manufacturing same
KR100732272B1 (en) * 2006-01-26 2007-06-25 주식회사 하이닉스반도체 Manufacturing Method of Semiconductor Device
KR100732773B1 (en) * 2006-06-29 2007-06-27 주식회사 하이닉스반도체 Method of manufacturing semiconductor device which prevents lifting between insulating layers

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5296400A (en) * 1991-12-14 1994-03-22 Hyundai Electronics Industries Co., Ltd. Method of manufacturing a contact of a highly integrated semiconductor device
EP0562207B1 (en) * 1992-03-27 1996-06-05 International Business Machines Corporation Method of forming thin film pseudo-planar PFET devices and structures resulting therefrom
JPH08148564A (en) * 1994-11-22 1996-06-07 Sony Corp Manufacture of semiconductor device
KR0139891B1 (en) * 1994-12-29 1999-04-15 김주용 Contact formation method of semiconductor device
JP3703885B2 (en) * 1995-09-29 2005-10-05 株式会社東芝 Semiconductor memory device and manufacturing method thereof
KR100365742B1 (en) * 1995-12-16 2003-03-03 주식회사 하이닉스반도체 A method for forming contact hole of semiconductor device
JPH09270461A (en) * 1996-03-29 1997-10-14 Mitsubishi Electric Corp Semiconductor device
JPH1022385A (en) * 1996-07-04 1998-01-23 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
JPH10261628A (en) * 1996-10-24 1998-09-29 Hyundai Electron Ind Co Ltd Formation of contact hole of semiconductor device
KR19990004940A (en) * 1997-06-30 1999-01-25 김영환 Semiconductor device manufacturing method
JP3127955B2 (en) * 1997-06-30 2001-01-29 日本電気株式会社 Semiconductor device and manufacturing method thereof
US6183655B1 (en) * 1997-09-19 2001-02-06 Applied Materials, Inc. Tunable process for selectively etching oxide using fluoropropylene and a hydrofluorocarbon
US6124164A (en) * 1998-09-17 2000-09-26 Micron Technology, Inc. Method of making integrated capacitor incorporating high K dielectric
JP4260275B2 (en) * 1999-03-18 2009-04-30 富士通マイクロエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10229346B4 (en) * 2001-06-29 2009-09-24 Hynix Semiconductor Inc., Icheon Process for producing a semiconductor element
US20050218373A1 (en) * 2001-08-30 2005-10-06 Kei-Yu Ko Etching methods
WO2003052808A2 (en) * 2001-12-13 2003-06-26 Applied Materials, Inc. Self-aligned contact etch with high sensitivity to nitride shoulder
WO2003052808A3 (en) * 2001-12-13 2004-04-15 Applied Materials Inc Self-aligned contact etch with high sensitivity to nitride shoulder
US6703314B2 (en) * 2001-12-14 2004-03-09 Hynix Semiconductor Inc. Method for fabricating semiconductor device
US20060017116A1 (en) * 2004-07-26 2006-01-26 Seok-Su Kim Semiconductor device and method for manufacturing the same
US8178441B2 (en) 2004-07-26 2012-05-15 Dongbu Electronics Co., Ltd. Semiconductor device and method for manufacturing the same
US20070044545A1 (en) * 2005-08-19 2007-03-01 Arthur Beyder Oscillator and method of making for atomic force microscope and other applications
US20070062265A1 (en) * 2005-08-19 2007-03-22 Arthur Beyder Oscillator for atomic force microscope and other applications
US7582554B2 (en) * 2006-05-25 2009-09-01 Elpida Memory, Inc. Method for manufacturing semiconductor device
US20070275553A1 (en) * 2006-05-25 2007-11-29 Elpida Memory, Inc. Method for manufacturing semiconductor device
US20110159677A1 (en) * 2009-12-30 2011-06-30 Hynix Semiconductor Inc. Method of fabricating landing plug contact in semiconductor memory device
CN102637629A (en) * 2011-02-14 2012-08-15 旺宏电子股份有限公司 Reduced number of mask combinations and methods for IC devices with stacked contact layers
CN107924844A (en) * 2016-03-24 2018-04-17 东京毅力科创株式会社 Manufacturing method of semiconductor device
CN117677192A (en) * 2024-01-31 2024-03-08 合肥晶合集成电路股份有限公司 Method for manufacturing semiconductor device and semiconductor device

Also Published As

Publication number Publication date
US6287905B2 (en) 2001-09-11
KR20010063762A (en) 2001-07-09
KR100474546B1 (en) 2005-03-08
JP2001230387A (en) 2001-08-24

Similar Documents

Publication Publication Date Title
US6287905B2 (en) Method for fabricating semiconductor device
KR20030034501A (en) Method for forming metal line using damascene process
US6274471B1 (en) Method for making high-aspect-ratio contacts on integrated circuits using a borderless pre-opened hard-mask technique
US6432816B2 (en) Method for fabricating semiconductor device
US6528418B1 (en) Manufacturing method for semiconductor device
US6372575B1 (en) Method for fabricating capacitor of dram using self-aligned contact etching technology
KR100465596B1 (en) A manufacturing method for semiconductor device
US6444559B2 (en) Method for fabricating semiconductor device
US20110248385A1 (en) Method for selectively forming symmetrical or asymmetrical features using a symmetrical photomask during fabrication of a semiconductor device and electronic systems including the semiconductor device
KR100420413B1 (en) Manufacturing method for semiconductor device
KR100726148B1 (en) Manufacturing method of semiconductor device
US6191034B1 (en) Forming minimal size spaces in integrated circuit conductive lines
KR100596831B1 (en) Manufacturing method of semiconductor device
KR100324015B1 (en) Method for fabricating contact hole of semiconductor device
KR20030093436A (en) Method for fabricating semiconductor device
KR100772698B1 (en) Semiconductor device manufacturing method
KR100672761B1 (en) How to Form Contact Plugs
KR20030058573A (en) Manufacturing method for semiconductor device
KR100400321B1 (en) A method for forming of a semiconductor device
KR100816721B1 (en) Semiconductor device manufacturing method
KR20000045358A (en) Fabrication method of semiconductor device
KR20010063856A (en) Fabricating method for semiconductor device
KR20030050773A (en) A fabricating method of semiconductor devices
KR20030043156A (en) A fabricating method of semiconductor devices
KR20020089759A (en) Manufacturing method for semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD., KOREA, R

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIM, JEONG HO;KIM, YONG SEO;REEL/FRAME:011401/0707;SIGNING DATES FROM 20001201 TO 20001202

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FEPP Fee payment procedure

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20130911