US11111598B2 - Crystal growth method in a semiconductor device - Google Patents
Crystal growth method in a semiconductor device Download PDFInfo
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- US11111598B2 US11111598B2 US16/456,265 US201916456265A US11111598B2 US 11111598 B2 US11111598 B2 US 11111598B2 US 201916456265 A US201916456265 A US 201916456265A US 11111598 B2 US11111598 B2 US 11111598B2
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- 238000002109 crystal growth method Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title description 40
- 239000013078 crystal Substances 0.000 claims abstract description 189
- 239000000463 material Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims description 57
- 229910052710 silicon Inorganic materials 0.000 claims description 26
- 229910052732 germanium Inorganic materials 0.000 claims description 7
- 150000001875 compounds Chemical class 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 6
- 229910052733 gallium Inorganic materials 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 5
- 229910052749 magnesium Inorganic materials 0.000 claims description 5
- 238000007740 vapor deposition Methods 0.000 claims description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 229910002601 GaN Inorganic materials 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 239000007791 liquid phase Substances 0.000 claims description 4
- 239000007790 solid phase Substances 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 229910052725 zinc Inorganic materials 0.000 claims description 3
- 229910052688 Gadolinium Inorganic materials 0.000 claims description 2
- 229910052786 argon Inorganic materials 0.000 claims description 2
- 229910052797 bismuth Inorganic materials 0.000 claims description 2
- 229910052793 cadmium Inorganic materials 0.000 claims description 2
- 229910052734 helium Inorganic materials 0.000 claims description 2
- 239000001307 helium Substances 0.000 claims description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 2
- 239000001257 hydrogen Substances 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 2
- 229910052742 iron Inorganic materials 0.000 claims description 2
- 229910052745 lead Inorganic materials 0.000 claims description 2
- 229910052748 manganese Inorganic materials 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 229910052709 silver Inorganic materials 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 238000012545 processing Methods 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 230000005496 eutectics Effects 0.000 description 5
- 239000003054 catalyst Substances 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000002243 precursor Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910000618 GeSbTe Inorganic materials 0.000 description 1
- 229910005900 GeTe Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 229910052961 molybdenite Inorganic materials 0.000 description 1
- CWQXQMHSOZUFJS-UHFFFAOYSA-N molybdenum disulfide Chemical compound S=[Mo]=S CWQXQMHSOZUFJS-UHFFFAOYSA-N 0.000 description 1
- 229910052982 molybdenum disulfide Inorganic materials 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/63—Vertical IGFETs
Definitions
- Embodiments described herein relate generally to a crystal growth method and a semiconductor device.
- FIG. 1 is a flowchart illustrating a crystal growth method according to a first embodiment
- FIG. 2A to FIG. 2E are schematic views illustrating the crystal growth method according to the first embodiment
- FIG. 3A and FIG. 3B are schematic views illustrating the crystal growth method according to the first embodiment
- FIG. 4A to FIG. 4H are schematic cross-sectional views illustrating the crystal growth method according to the first embodiment
- FIG. 5A to FIG. 5E are schematic cross-sectional views illustrating the crystal growth method according to the first embodiment
- FIG. 6 is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment.
- FIG. 7 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment.
- a crystal growth method includes forming a first member at at least a part of a bottom portion of a hole in a structure body.
- the hole includes the bottom portion and a side portion.
- the first member includes a first element.
- the first element is not adhered to at least a part of the side portion in the forming the first member.
- the crystal growth method includes growing a crystal member inside the hole by supplying a source material to the hole after the forming the first member.
- the source material includes a second element.
- the crystal member includes the second element.
- FIG. 1 is a flowchart illustrating a crystal growth method according to a first embodiment.
- the crystal growth method includes a first member formation process of forming a first member (step S 110 ) and a growth process of growing a crystal member (step S 120 ).
- the crystal growth method may further include a removal process of removing a first film (step S 105 ).
- the crystal growth method may further include an insulating film formation process of forming an insulating film (step S 115 ).
- FIG. 2A to FIG. 2E are schematic views illustrating the crystal growth method according to the first embodiment.
- FIG. 2A , FIG. 2B , FIG. 2D , and FIG. 2E are cross-sectional views.
- FIG. 2C is a plan view as viewed along arrow AA of FIG. 2B .
- FIG. 2B is a line A 1 -A 2 cross-sectional view of FIG. 2C .
- a structure body 30 is prepared as shown in FIG. 2A .
- the structure body 30 has a hole 30 H.
- the hole 30 H includes a bottom portion 30 B and a side portion 30 S.
- the hole 30 H has an opening 30 P.
- the hole 30 H may be a recess.
- the structure body 30 includes a crystal.
- the structure body 30 includes, for example, a semiconductor.
- a first film 35 is provided in the example.
- the first film 35 is provided at the bottom portion 30 B and the side portion 30 S.
- the structure body 30 includes silicon.
- the first film 35 includes a compound including silicon.
- the first film 35 includes silicon oxide.
- the crystal growth method according to the embodiment may include a removal process of removing at least a portion of the first film 35 (step S 105 : referring to FIG. 1 ).
- processing is performed using, for example, buffered hydrogen fluoride.
- Processing that uses oxygen plasma may be performed before the buffered hydrogen fluoride processing.
- the first film 35 that includes silicon oxide is removed by such processing.
- the duration of the processing using buffered hydrogen fluoride is, for example, not less than 30 seconds and not more than 5 minutes.
- the duration of the processing may depends on the material and the thickness of the first film 35 , for example.
- the power of the oxygen plasma processing is, for example, not less than 300 W and not more than 1000 W.
- the duration of the oxygen plasma processing is, for example, not less than 10 seconds and not more than 2 minutes.
- the first film 35 is formed by oxidizing the surface of the structure body 30 .
- the removal process recited above can be omitted. Examples of the material of the structure body 30 and examples of the material of the first film 35 are described below.
- the structure body 30 is obtained by the removal of the first film 35 (referring to FIG. 2B ).
- the structure body 30 has the hole 30 H.
- the hole 30 H includes the bottom portion 30 B, the side portion 30 S, and the opening 30 P.
- the direction from the bottom portion 30 B toward the opening 30 P is taken as a first direction.
- the first direction is taken as a Z-axis direction.
- One direction perpendicular to the Z-axis direction is taken as an X-axis direction.
- a direction perpendicular to the Z-axis direction and the X-axis direction is taken as a Y-axis direction.
- the hole 30 H has a length W 2 in the second direction and a length W 3 in a third direction.
- the second direction crosses the first direction (the Z-axis direction).
- the second direction is the X-axis direction.
- the third direction crosses a plane including the first direction and the second direction.
- the third direction is, for example, the Y-axis direction.
- the length W 2 is shorter than the length W 3 .
- the hole 30 H is a “trench.”
- the length W 2 may be substantially the same as the length W 3 .
- the configuration of the hole 30 H when cut by the X-Y plane may be substantially square or substantially circular.
- the length W 2 is taken to be not more than the length W 3 .
- the direction of the shorter length corresponds to the second direction.
- the direction of the longer length corresponds to the third direction.
- the hole 30 H is, for example, a trench or a via hole.
- a depth D 1 of the hole 30 H is the length along the first direction (the Z-axis direction) of the hole 30 H.
- the depth D 1 is greater than the length W 2 .
- the aspect ratio of the hole 30 H is high.
- the aspect ratio is, for example, the ratio of the depth D 1 to the length W 2 .
- the hole 30 H is formed by removing a portion of the member used to form the structure body 30 .
- the removal is performed by dry etching or wet etching.
- the structure body 30 includes a first region 31 and a second region 32 .
- the first region 31 includes the bottom portion 30 B.
- the second region 32 includes the side portion 30 S.
- the second region 32 is continuous with the first region 31 .
- the first region 31 and the second region 32 are seamless.
- the structure body 30 includes a crystal; and the first region 31 and the second region 32 also include a crystal.
- the crystal orientation of the second region 32 is substantially the same as the crystal orientation of the first region 31 .
- a first member 10 is formed at the bottom portion 30 B of the hole 30 H.
- the first member 10 includes a first element.
- the first element includes, for example, at least one selected from the group consisting of Au, Al, Ag, Bi, Cd, Co, Cu, Dy, Fe, Ga, Gd, In, Mg, Mn, Ni, Os, Pb, Pd, Pt, Te, Ti, and Zn.
- the first member functions as a catalyst in the growth process of growing the crystal member (step S 120 ).
- the first element and the first member include Au.
- the first member 10 that includes the first element is formed at the bottom portion 30 B of the structure body 30 having the hole 30 H.
- at least a portion of the side portion 30 S is not covered with the first member 10 .
- the first element is not adhered to the side portion 30 S in the formation of the first member 10 .
- the first element is not adhered to at least a portion of the side portion 30 S in the formation of the first member 10 .
- the first member 10 is not adhered to the side portion 30 S in the formation of the first member 10 .
- the first member 10 is formed by vapor deposition of the first element.
- the first member formation process may include performing at least one of vapor deposition of the first element or “Long Throw Sputtering” of the first element.
- the spread angle in the direction in which the first element travels is small in these methods.
- the first element enters the hole 30 H from the opening 30 P of the hole 30 H along the Z-axis direction.
- the first element reaches the bottom portion 30 B of the hole 30 H.
- the adhesion of the first element to the side portion 30 S is suppressed. Thereby, at least a portion of the side portion 30 S is not covered with the first member 10 .
- the first member 10 is in a solid phase in the first member formation process (in FIG. 2D ).
- a crystal member 20 that includes a second element is grown inside the hole 30 H by supplying a source material including the second element to the hole 30 H after the first member formation process.
- the supplying of the source material includes supplying a first gas.
- the growth process is performed at a high temperature.
- the temperature in the growth process is, for example, not less than 360° C. and not more than 1500° C.
- the temperature in the growth process is, for example, higher than an eutectic temperature of a material including a first element and the second element.
- the eutectic temperature of Au/Si is 363° C. In a case where the first member 10 includes Au and Si, the temperature is not less than 360° C.
- the eutectic temperature of Al/Si is 577° C. In a case where the first member 10 includes Al and Si, the temperature is not less than 557° C. and not more than 800° C., for example.
- the eutectic temperature of Zn/Si is 419° C. In a case where the first member 10 includes Zn and Si, the temperature is not less than 419° C. and not more than 1500° C., for example.
- the eutectic temperature of Ti/Si is 1330° C. In a case where the first member 10 includes Ti and Si, the temperature is not less than 1330° C. and not more than 1500° C., for example.
- the interior of the chamber in the growth process is an atmospheric-pressure state or a reduced-pressure state.
- the pressure inside the chamber is, for example, not less than 1 ⁇ 10 ⁇ 6 Pa and not more than 1.014 ⁇ 10 6 Pa.
- the source material recited above e.g., the first gas
- the precursor includes the second element.
- the second element includes, for example, at least one selected from the group consisting of Si, Ge, Ga, and In.
- the crystal member 20 includes a crystal including the second element.
- the crystal member 20 includes, for example, at least one selected from the group consisting of Si, Ge, SiGe, GaAs, GaN, InP, GeTe, GeSbTe, MoS 2 , and MoSe 2 .
- the crystal member 20 includes a silicon crystal.
- the first member 10 contacts the bottom portion 30 B of the hole 30 H before the growth process ( FIG. 2E ). Because the growth process is performed at a high temperature, for example, the first member 10 is in a liquid phase in the growth process. In the growth process, the crystal member 20 is formed between the bottom portion 30 B and the first member 10 . For example, the crystal member 20 is epitaxially grown at the bottom portion 30 B.
- the first member 10 As the crystal member 20 grows, the first member 10 is pushed upward; and the position of the first member 10 ascends. The crystal member 20 contacts the bottom portion 30 B in the growth process and after the growth process.
- the crystal orientation of the crystal member 20 that is grown is aligned with the crystal orientation of the bottom portion 30 B.
- the crystal member 20 that has a uniform crystal orientation is obtained.
- the first member 10 is provided at the bottom portion 30 B and is substantially not provided at the side portion 30 S.
- the crystal member 20 that grows using the first member 10 as a catalyst grows from the bottom portion 30 B.
- the growth of the crystal member 20 from the side portion 30 S is suppressed. Because the crystal member 20 grows in substantially one direction (the direction from the bottom portion 30 B), the crystal orientation of the crystal member 20 becomes uniform easily.
- a crystal growth method that can grow a high-quality crystal can be provided.
- a seed layer is provided at the side portion of the hole.
- the seed layer is a Au layer.
- a liquid of Au included in the seed layer flows and moves to the bottom portion of the hole. Subsequently, crystal growth is performed.
- the seed layer is once adhered to the side portion of the hole. Therefore, the seed layer remains easily on the side portion.
- the crystal member is formed by the crystal grown from the bottom portion of the hole and the crystal grown from the side portion of the hole contacting each other.
- a distinct boundary or gap occurs easily between the crystal grown from the bottom portion of the hole and the crystal grown from the side portion of the hole.
- the crystal grows from multiple locations.
- the crystal orientations are not the same between the crystals grown from the multiple locations. Therefore, in the example, it is difficult to obtain a high-quality crystal member.
- the size of the crystal grains included in the crystal member is small. In the example, multiple crystal grains that have mutually-different crystal orientations are formed easily.
- the crystal member 20 is grown from the bottom portion 30 B; and the growth of the crystal member 20 from the side portion 30 S is suppressed effectively.
- the crystal member 20 that has a uniform crystal orientation is obtained easily thereby.
- large crystal grains are obtained.
- one crystal member 20 is substantially one crystal. According to the embodiment, for example, a crystal growth method that can grow a high-quality crystal can be provided.
- multiple holes 30 H may be provided in the structure body 30 .
- multiple crystal members 20 are provided to correspond to the multiple holes 30 H.
- One of the multiple crystal members 20 is formed inside one of the multiple holes 30 H.
- the crystal orientations of the multiple crystal members 20 are aligned respectively with the crystal orientations of the bottom portions 30 B of the multiple holes 30 H. Therefore, the crystal orientations of the multiple crystal members 20 are substantially the same.
- the crystal member 20 that has uniform characteristics is obtained. A higher-quality crystal is obtained easily.
- the crystal member 20 contacts at least a portion of the side portion 30 S of the hole 30 H.
- the crystal member 20 that is grown from the bottom portion 30 B grows while contacting the side portion 30 S of the hole 30 H.
- the crystal member 20 grows while being affected by the side portion 30 S.
- the crystal orientation of the crystal member 20 reflects the crystal orientation of the side portion 30 S.
- the crystal orientation of the crystal member 20 is aligned with the crystal orientation of the first region 31 of the structure body 30 .
- the crystal orientation of the crystal member 20 may be aligned with the crystal orientation of the second region 32 of the structure body 30 .
- the crystal member 20 contacts at least a portion of the second region 32 .
- a seed layer is provided at the side portion of the hole; and a liquid of the Au included in the seed layer moves to the bottom portion of the hole due to the high-temperature processing.
- the seed layer is once adhered to the side portion of the hole, it is difficult to completely remove the seed layer that was adhered to the side portion.
- the first member 10 is formed at the bottom portion 30 B so that the first element is not adhered to the side portion 30 S in the formation of the first member 10 . Because the first element is not adhered to the side portion 30 S, the growth of the crystal member 20 from the side portion 30 S is suppressed effectively.
- FIG. 3A and FIG. 3B are schematic views illustrating the crystal growth method according to the first embodiment.
- FIG. 3A is a cross section SEM (Scanning Electron Microscope) image of the structure body 30 .
- FIG. 3B is a schematic cross-sectional view drawn based on FIG. 3A .
- FIG. 3A and FIG. 3B illustrate the state after the first member formation process and before the growth process.
- the structure body 30 that has the hole 30 H is provided.
- the first member 10 is formed at the bottom portion 30 B of the hole 30 H.
- the cross-sectional configuration of the hole 30 H is not always rectangular.
- the bottom portion 30 B of the hole 30 H may include portions having curved configurations.
- the bottom portion 30 B may be defined as follows. For example, as described above, the direction from the bottom portion 30 B toward the opening 30 P is aligned with the first direction (i.e., the Z-axis direction). The length along the first direction of the hole 30 H is taken as the depth D 1 .
- the depth D 1 is, for example, the maximum value of the distance along the first direction between the bottom portion 30 B and the opening 30 P.
- the depth D 1 is the sum of a bottom portion length D 2 along the first direction of the bottom portion 30 B and a side portion length D 3 along the first direction of the side portion 30 S.
- the bottom portion length D 2 may be defined at 50% of the depth D 1 .
- the position of 50% of the depth D 1 of the hole 30 H may be taken as the boundary between the bottom portion 30 B and the side portion 30 S. 50% of the depth D 1 of the hole 30 H corresponds to the length of the side portion 30 S.
- the first member 10 is formed at the bottom portion 30 B such as that recited above.
- the first element is not adhered to the side portion 30 S such as that recited above.
- a portion 30 Ba of the surface of the hole 30 H is included in the bottom portion 30 B.
- the first member 10 is formed at such a portion 30 Ba of the surface of the hole 30 H.
- the first element of the first member 10 is substantially not adhered to the region higher than the portion 30 Ba of the surface.
- the length of the first member 10 along the first direction from the bottom portion 30 B toward the opening 30 P is taken as a length 10 z .
- the length of the first member 10 along the second direction crossing the first direction is taken as a length 10 x .
- the second direction is the direction of the length W 2 and is aligned with the X-axis direction.
- the direction of the shorter length corresponds to the second direction.
- the length 10 z of the first member 10 along the first direction (the Z-axis direction) is longer than the length 10 x of the first member 10 along the second direction (in the example, the X-axis direction).
- the first member 10 that has a steep hill shape is formed.
- the length 10 z of the first member 10 along the first direction (the Z-axis direction) to be not less than 20% of the length W 2 of the opening 30 P along the second direction (in the example, the X-axis direction).
- the length 10 z is not less than 20% of the length W 2
- substantially the entire bottom portion 30 B of the hole 30 H is covered with the first member 10 when the first member 10 changes to a liquid phase due to the high temperature.
- the continuous crystal member 20 easily is grown uniformly.
- the length 10 z is less than 20% of the length W 2 , the amount of the first member 10 is low. Therefore, the first member 10 is formed in an island state at the bottom portion 30 B of the hole 30 H when the first member 10 changes to a liquid phase due to the high temperature. In such a case, it may be difficult to obtain a continuous and uniform crystal member 20 .
- a sufficient amount of the first member 10 is formed at the bottom portion 30 B of the hole 30 H. Thereby, it is easy to uniformly grow the continuous crystal member 20 .
- the length 10 z of the first member 10 along the first direction (the Z-axis direction) to be, for example, not less than 40% of the depth D 1 of the hole 30 H along the first direction.
- the opening 30 P of the hole 30 H may be narrower than the maximum width of the hole 30 H.
- the length W 2 of the opening 30 P along the second direction in the example, the X-axis direction
- Wmax maximum value of the length along the second direction of the hole 30 H.
- the depth D 1 of the hole 30 H is about 2579 nm.
- the length W 2 (the width) of the opening 30 P is about 866 nm.
- the maximum value Wmax (the maximum width) of the length along the second direction of the hole 30 H is, for example, 1183 nm.
- the height of the first member 10 (the length 10 z along the first direction) is 1087 nm.
- the width of the first member 10 (the length 10 x along the second direction) is 658 nm.
- the uniform crystal member 20 is obtained easily when the length 10 z (the height) of the first member 10 is about 200 nm or more. In one example, the length 10 z is about 284 nm.
- the crystal member 20 is conductive.
- the conductivity type of the crystal member 20 may be different from the conductivity type of the second region 32 of the structure body 30 .
- the second region 32 is of an n-type; and the crystal member 20 is of a p-type.
- the second region 32 may be of the p-type; and the crystal member 20 may be of the n-type.
- the conductivity type of the second region 32 of the structure body 30 may be the same as or different from the conductivity type of the first region 31 of the structure body 30 .
- FIG. 4A to FIG. 4H are schematic cross-sectional views illustrating the crystal growth method according to the first embodiment.
- the structure body 30 is prepared as shown in FIG. 4A .
- the first film 35 is provided in the example as well. At least a portion of the first film 35 is removed (step S 105 ).
- the structure body 30 is obtained by the removal of the first film 35 (referring to FIG. 4B ).
- the structure body 30 has the hole 30 H.
- the hole 30 H includes the bottom portion 30 B, the side portion 30 S, and the opening 30 P.
- the first member 10 is formed at the bottom portion 30 B of the hole 30 H.
- the first element is not adhered to the side portion 30 S in the formation of the first member 10 .
- the first member 10 is not adhered to the side portion 30 S.
- the first member 10 is formed by vapor deposition of the first element.
- the first member 10 is in a solid phase in the first member formation process (in FIG. 4C ).
- an insulating film 36 is formed at the side portion 30 S of the hole 30 H (an insulating film formation process; step S 115 ).
- the insulating film formation process is performed after the first member formation process ( FIG. 4C ) and before the growth process ( FIG. 4E ).
- the insulating film 36 may be formed from the structure body 30 .
- the insulating film 36 is formed by oxidizing or nitriding the surface portion of the side portion 30 S of the hole 30 H of the structure body 30 .
- the insulating film 36 includes silicon oxide or silicon nitride.
- the insulating film 36 may be formed by a method such as CVD (Chemical Vapor Deposition), etc., on the side portion 30 S of the hole 30 H.
- the insulating film 36 may include, for example, at least one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide.
- the crystal member 20 that includes the second element is grown inside the hole 30 H by supplying a source material including the second element to the hole 30 H.
- the first member 10 is provided at the bottom portion 30 B but is substantially not provided at the side portion 30 S.
- the crystal member 20 that grows using the first member 10 as a catalyst grows from the bottom portion 30 B.
- the growth of the crystal member 20 from the side portion 30 S is suppressed.
- the crystal member 20 becomes uniform easily.
- a crystal growth method that can grow a high-quality crystal can be provided.
- the first member 10 and a portion of the structure body 30 may be removed after forming the crystal member 20 recited above.
- the portion of the structure body 30 that is removed includes, for example, the first region 31 .
- the crystal member 20 and the second region 32 of the structure body 30 may be electrically insulated by the insulating film 36 by the removal of the portion of the structure body 30 .
- the crystal member 20 may function as a connection member.
- the surface of the second region 32 of the structure body 30 and the surface of the crystal member 20 are exposed.
- an insulating layer 38 a is formed at the surface (e.g., the lower surface) of the second region 32 and the surface (e.g., the lower surface) of the crystal member 20 .
- An insulating layer 38 b is formed at another surface (e.g., the upper surface) of the second region 32 and another surface (e.g., the upper surface) of the crystal member 20 .
- the insulating layers 38 a and 38 b include, for example, an oxide film of silicon oxide or the like, a resin film such as polyimide, etc.
- surfaces of the crystal member 20 are exposed by removing a portion of the insulating layer 38 a and a portion of the insulating layer 38 b .
- a conductive film 61 and a conductive film 62 are formed.
- the conductive film 61 is used as an interconnect (or an electrode) on the lower surface side.
- the conductive film 62 is used as an interconnect (or an electrode) on the upper surface side.
- the crystal member 20 is between the conductive film 61 and the conductive film 62 .
- a portion of the insulating layer 38 a is between the conductive film 61 and the crystal member 20 .
- a portion of the insulating layer 38 b is between the conductive film 62 and the crystal member 20 .
- the crystal member 20 is a connection member piercing the structure body 30 (the second region 32 ).
- the connection member electrically connects the conductive film 61 and the conductive film 62 .
- the second region 32 of the structure body 30 may include a conductive member and an insulating member that are stacked.
- a crystal growth method example will now be described in which the second region 32 includes a conductive member and an insulating member.
- FIG. 5A to FIG. 5E are schematic cross-sectional views illustrating the crystal growth method according to the first embodiment.
- the structure body 30 includes the first region 31 and the second region 32 .
- the second region 32 includes a conductive member 32 a and an insulating member 32 b .
- the direction from the insulating member 32 b toward the conductive member 32 a is aligned with the first direction (the Z-axis direction).
- the multiple conductive members 32 a and the multiple insulating members 32 b are provided in the example.
- One of the multiple insulating members 32 b is between one of the multiple conductive members 32 a and another one of the multiple conductive members 32 a .
- One of the multiple conductive members 32 a may be between one of the multiple insulating members 32 b and another one of the multiple insulating members 32 b.
- the hole 30 H is provided in the structure body 30 including such a second region 32 .
- the hole 30 H reaches the first region 31 .
- the first film 35 is provided in the example. At least a portion of the first film 35 is removed (step S 105 ).
- the structure body 30 is obtained by the removal of the first film 35 (referring to FIG. 5B ).
- the first member 10 is formed at the bottom portion 30 B of the hole 30 H.
- the first element is not adhered to the side portion 30 S in the formation of the first member 10 .
- the first member 10 is not adhered to the side portion 30 S.
- the first member 10 is formed by vapor deposition of the first element.
- the first member 10 is in a solid phase in the first member formation process (in FIG. 5C ).
- the insulating film 36 is formed at the side portion 30 S of the hole 30 H (the insulating film formation process; step S 115 ).
- the crystal member 20 that includes the second element is grown inside the hole 30 H by supplying a source material including the second element to the hole 30 H.
- the first member 10 is provided at the bottom portion 30 B but is substantially not provided at the side portion 30 S.
- the crystal member 20 that grows using the first member 10 as a catalyst grows from the bottom portion 30 B.
- the growth of the crystal member 20 from the side portion 30 S is suppressed.
- the crystal member 20 becomes uniform easily.
- a crystal growth method that can grow a high-quality crystal can be provided.
- the processes described in reference to FIG. 4F to FIG. 4H may be performed after the process illustrated in FIG. 5E .
- the structure body 30 includes a third element.
- the first film 35 includes, for example, a compound including the third element.
- the third element is silicon.
- the first film 35 includes, for example, silicon oxide.
- the structure body 30 includes, for example, at least one selected from the group consisting of Si, Ge, SiGe, GaAs, GaN, and InP.
- the structure body 30 includes, for example, a semiconductor.
- the second element included in the crystal member 20 includes, for example, at least one selected from the group consisting of Si, Ge, Ga, and In.
- the crystal member 20 includes, for example, at least one selected from the group consisting of Si, Ge, SiGe, GaAs, GaN, and InP.
- the material of the crystal member 20 may be substantially the same as the material of the structure body 30 .
- the lattice of the crystal of the crystal member 20 substantially matches the lattice of the crystal of the first region 31 of the structure body 30 .
- the lattice of the crystal of the crystal member 20 substantially matches the lattice of the crystal of the bottom portion 30 B of the hole 30 H of the structure body 30 .
- the first element that is included in the first member 10 is determined to match the crystal growth of the crystal member 20 .
- the conductivity type of the crystal member 20 may be the n-type or the p-type.
- the source material that is used in the growth of the crystal member 20 includes, for example, a compound including the second element.
- the compound is, for example, a precursor.
- the compound may include, for example, at least one selected from the group consisting of monosilane, disilane, and dichlorosilane.
- the supplying of the source material may include the irradiation of a beam of the second element.
- the supplying of the source material may include the irradiation of an atomic beam of silicon.
- the first gas that is used in the growth of the crystal member 20 may include, for example, a source material of an impurity providing a conductivity type.
- the source material of the impurity includes, for example, a fourth element.
- the fourth element includes, for example, at least one selected from the group consisting of P, B, As, and Mg.
- the fourth element includes, for example, at least one selected from the group consisting of P and As.
- the crystal member 20 is silicon
- the fourth element includes at least one selected from the group consisting of B and Al.
- the fourth element includes one of Mg or Si.
- the first gas may include at least one selected from the group consisting of hydrogen, nitrogen, argon, and helium. These elements are, for example, elements of the carrier gas.
- the depth D 1 of the hole 30 H is, for example, not less than 1 ⁇ m and not more than 1000 ⁇ m.
- the depth D 1 may be 50 ⁇ m or less.
- the length W 2 along the second direction of the opening 30 P of the hole 30 H is, for example, not less than 10 nm and not more than 2000 nm.
- the length W 3 along the third direction of the opening 30 P of the hole 30 H is, for example, not less than 0.1 ⁇ m and not more than 5 ⁇ m.
- a second embodiment relates to a semiconductor device.
- FIG. 6 is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment.
- the semiconductor device 110 includes the structure body 30 and the crystal member 20 .
- the structure body 30 includes a semiconductor.
- the structure body 30 includes the first region 31 and the second region 32 .
- the multiple crystal members 20 include, for example, crystal members 21 a to 21 c , etc.
- One of the multiple crystal members 20 e.g., the crystal member 21 a ) will now be focused upon.
- the direction from the first region 31 toward the crystal member 21 a is taken as the first direction.
- the first direction is, for example, the Z-axis direction.
- the direction from the crystal member 21 a toward the second region 32 is taken as the second direction.
- the first direction crosses the second direction.
- the second direction is, for example, the X-axis direction.
- the crystal orientation of the crystal member 21 a is aligned with the crystal orientation of the first region 31 .
- the crystal orientation of the crystal member 21 a is aligned with the crystal orientation of the second region 32 .
- the crystal member 21 a includes a first partial region pr 1 , a second partial region pr 2 , and a third partial region pr 3 .
- the third partial region pr 3 contacts the first region 31 .
- the second partial region pr 2 is between the third partial region pr 3 and the first partial region pr 1 .
- the length along the second direction of the first partial region pr 1 is taken as a length dx 1 .
- the length along the second direction of the second partial region pr 2 is taken as a length dx 2 .
- the length dx 1 is shorter than the length dx 2 .
- the crystal member 20 (e.g., the crystal member 21 a ) can be formed by performing crystal growth by supplying the second element to the hole 30 H provided in the structure body 30 (referring to FIG. 2B , etc.).
- the third partial region pr 3 is, for example, a portion contacting the bottom portion 30 B of the hole 30 H.
- the first partial region pr 1 is, for example, a portion corresponding to the opening of the hole 30 H.
- the second partial region pr 2 corresponds to the portion where the width of the hole 30 H is a maximum.
- the width (the length dx 1 ) of the first partial region pr 1 corresponding to the opening is narrower than the width (the length dx 2 ) of the second partial region pr 2 corresponding to the portion where the width is a maximum, the first member 10 does not easily adhere to the side portion 30 S of the hole 30 H. Therefore, high quality of the crystal member 20 is obtained.
- the semiconductor device 110 includes first to third electrodes 51 to 53 .
- the structure body 30 includes third to fifth regions 43 to 45 .
- the direction from a second electrode 52 toward the first electrode 51 is aligned with the Z-axis direction.
- the direction from the second electrode 52 toward the third electrode 53 is aligned with the Z-axis direction.
- the third region 43 includes the third partial region pr 3 of the crystal member 20 .
- the fourth region 44 is between the third region 43 and the first electrode 51 .
- the fifth region 45 is between the fourth region 44 and the first electrode 51 .
- the first region 31 , the second region 32 , the third region 43 , the fourth region 44 , and the fifth region 45 include, for example, silicon.
- the first region 31 is, for example, an n + -region.
- the second region 32 is, for example, an n ⁇ -region.
- the third region 43 is, for example, a p ⁇ -region.
- the fourth region 44 is, for example, an n + -region.
- the fifth region 45 is, for example, an n + -region.
- at least a portion of the third region 43 , at least a portion of the fourth region 44 , and at least a portion of the fifth region 45 can be formed from the crystal member 20 .
- the third region 43 , the fourth region 44 , and the fifth region 45 can be formed by implanting an impurity of the appropriate conductivity type into the crystal member 20 or the second region 32 .
- the second region 32 is between the second electrode 52 and the third electrode 53 .
- An insulating layer 50 i is between the second region 32 and the third electrode 53 .
- the semiconductor device 110 is, for example, a transistor having a super junction structure.
- the semiconductor device 110 for example, good characteristics are obtained stably because the crystal quality of the crystal member 20 is high.
- FIG. 7 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment.
- the semiconductor device 120 includes the structure body 30 and the crystal member 20 .
- the structure body 30 and the crystal member 20 are included in one semiconductor component 60 .
- the crystal member 20 pierces the second region 32 of the structure body 30 .
- the insulating film 36 is between the second region 32 and the crystal member 20 .
- the semiconductor component 60 includes the conductive film 61 and the conductive film 62 .
- the conductive film 61 and the conductive film 62 are electrically connected by the crystal member 20 .
- the insulating layers 38 a and 38 b described in reference to FIG. 4G and FIG. 4H are not illustrated in FIG. 7 .
- the semiconductor component 60 includes a circuit portion 63 .
- the circuit portion 63 may include, for example, a transistor or the like based on the semiconductor of the second region 32 .
- Multiple semiconductor components 60 are provided in the example.
- the multiple semiconductor components 60 are stacked in the Z-axis direction.
- a connection member 65 is provided between one semiconductor component 60 and another one semiconductor component 60 .
- the connection member 65 electrically connects the conductive film 62 of the one semiconductor component 60 and the conductive film 61 of the other one semiconductor component 60 .
- the conductive film 61 and the conductive film 62 are electrically connected with a low resistance by the crystal member 20 . Good characteristics are obtained stably.
- a semiconductor member is filled into a hole (a trench, a via hole, etc.) formed in a semiconductor layer.
- a semiconductor layer For example, stacked multiple circuit layers are electrically connected by such a semiconductor member.
- a semiconductor crystal is filled into a trench in a semiconductor device having a super junction structure.
- the characteristics degrade; and the characteristics become nonuniform.
- the characteristics of the semiconductor device easily become unstable.
- the breakdown voltage of the semiconductor device may decrease due to the discontinuous interface or gap.
- the first film 35 of the hole 30 H is removed. Further, the first member 10 that includes the first element is formed at the bottom portion 30 B of the hole 30 H so that the first element is not adhered to the side portion 30 S of the hole 30 H. Thereby, the crystal member 20 grows from the bottom portion 30 B of the hole 30 H. A uniform and high-quality crystal member 20 is obtained. The crystal orientation of the crystal member 20 is aligned with the crystal orientation of the structure body 30 in which the hole 30 H is provided.
- a crystal growth method and a semiconductor device can be provided in which a high-quality crystal can be grown.
- perpendicular and parallel refer to not only strictly perpendicular and strictly parallel but also include, for example, the fluctuation due to manufacturing processes, etc. It is sufficient to be substantially perpendicular and substantially parallel.
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003197524A (en) | 2001-12-27 | 2003-07-11 | Sharp Corp | Semiconductor film, its forming method, semiconductor device, and display device |
US6605535B1 (en) * | 2002-09-26 | 2003-08-12 | Promos Technologies, Inc | Method of filling trenches using vapor-liquid-solid mechanism |
US20070228496A1 (en) | 2004-09-03 | 2007-10-04 | Koninklijke Philips Electronics N.V. | Vertical Semiconductor Devices and Methods of Manufacturing Such Devices |
US20090057839A1 (en) * | 2007-08-28 | 2009-03-05 | Lewis Nathan S | Polymer-embedded semiconductor rod arrays |
JP2009224606A (en) | 2008-03-17 | 2009-10-01 | Shin Etsu Handotai Co Ltd | Manufacturing method of semiconductor element having superjunction structure |
JP2017034154A (en) | 2015-08-04 | 2017-02-09 | 株式会社東芝 | Semiconductor device |
JP2021009984A (en) | 2019-06-28 | 2021-01-28 | 株式会社東芝 | Crystal growth method and semiconductor device |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59181529A (en) * | 1983-03-31 | 1984-10-16 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
US4910165A (en) * | 1988-11-04 | 1990-03-20 | Ncr Corporation | Method for forming epitaxial silicon on insulator structures using oxidized porous silicon |
JP3550157B2 (en) * | 1992-01-21 | 2004-08-04 | 株式会社東芝 | Manufacturing method of circuit measurement terminals |
JP5066164B2 (en) * | 2009-12-07 | 2012-11-07 | シャープ株式会社 | Manufacturing method of semiconductor device |
FR2962595B1 (en) * | 2010-07-06 | 2015-08-07 | Commissariat Energie Atomique | MICROELECTRONIC DEVICE WITH METALLIC INTERCONNECTION LEVELS CONNECTED BY PROGRAMMABLE VIAS |
JP2013219203A (en) * | 2012-04-09 | 2013-10-24 | Canon Inc | Columnar structure manufacturing method |
KR102059526B1 (en) * | 2012-11-22 | 2019-12-26 | 삼성전자주식회사 | Method of forming semiconductor device having embedded stressor and related device |
US9443865B2 (en) * | 2014-12-18 | 2016-09-13 | Sandisk Technologies Llc | Fabricating 3D NAND memory having monolithic crystalline silicon vertical NAND channel |
-
2019
- 2019-06-28 US US16/456,265 patent/US11111598B2/en active Active
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Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003197524A (en) | 2001-12-27 | 2003-07-11 | Sharp Corp | Semiconductor film, its forming method, semiconductor device, and display device |
US6605535B1 (en) * | 2002-09-26 | 2003-08-12 | Promos Technologies, Inc | Method of filling trenches using vapor-liquid-solid mechanism |
US20070228496A1 (en) | 2004-09-03 | 2007-10-04 | Koninklijke Philips Electronics N.V. | Vertical Semiconductor Devices and Methods of Manufacturing Such Devices |
JP2008511982A (en) | 2004-09-03 | 2008-04-17 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Vertical semiconductor device and method of manufacturing such a device |
US20090057839A1 (en) * | 2007-08-28 | 2009-03-05 | Lewis Nathan S | Polymer-embedded semiconductor rod arrays |
JP2009224606A (en) | 2008-03-17 | 2009-10-01 | Shin Etsu Handotai Co Ltd | Manufacturing method of semiconductor element having superjunction structure |
JP2017034154A (en) | 2015-08-04 | 2017-02-09 | 株式会社東芝 | Semiconductor device |
US20170040414A1 (en) | 2015-08-04 | 2017-02-09 | Kabushiki Kaisha Toshiba | Semiconductor device |
JP2021009984A (en) | 2019-06-28 | 2021-01-28 | 株式会社東芝 | Crystal growth method and semiconductor device |
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