[go: up one dir, main page]

US10879208B2 - Chip-on-film and method of manufacturing the same - Google Patents

Chip-on-film and method of manufacturing the same Download PDF

Info

Publication number
US10879208B2
US10879208B2 US16/533,440 US201916533440A US10879208B2 US 10879208 B2 US10879208 B2 US 10879208B2 US 201916533440 A US201916533440 A US 201916533440A US 10879208 B2 US10879208 B2 US 10879208B2
Authority
US
United States
Prior art keywords
insulating film
interconnections
stepped portion
bonding region
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US16/533,440
Other versions
US20200243474A1 (en
Inventor
Jae Min Jung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JUNG, JAE MIN
Publication of US20200243474A1 publication Critical patent/US20200243474A1/en
Application granted granted Critical
Publication of US10879208B2 publication Critical patent/US10879208B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02354—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light using a coherent radiation, e.g. a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • Apparatus and methods consistent with example embodiments relate to a chip-on-film (COF) and to a method of manufacturing the same.
  • COF chip-on-film
  • a solder resist may be applied to metal interconnections formed on a polyimide (PI) surface in order to protect the metal interconnections.
  • the SR is not to be applied, however, to a bonding region of the PI surface in which the COF is to be bonded to a printed circuit board (PCB) or a display panel.
  • PCB printed circuit board
  • minimum tolerances of the bonding region are necessarily reduced as the width of a bezel surrounding the display is narrowed to comply with industry demands.
  • a chip-on-film which includes an insulating film including a bonding region for bonding to an external device, a plurality of interconnections disposed on the insulating film and partially extending into the bonding region, and an integrated circuit (IC) chip disposed on the insulating film so as to be electrically connected to the plurality of interconnections.
  • the chip-on-film further includes a solder resist disposed so as to cover the insulating film excluding the bonding region and so as to cover the plurality of interconnections excluding portions extending into the bonding region, and a stepped portion located between the bonding region and the solder resist. The stepped portion forms a boundary against a flow of the solder resist into the bonding region.
  • a method of manufacturing a chip-on-film which includes punching sprocket holes in an insulating film along an edge of the insulating film, the insulating film including a bonding region for bonding to an external device, and forming a plurality of interconnections on the insulating film so as to partially extend into the bonding region.
  • the method further includes forming a solder resist so as to cover the insulating film excluding the bonding region, and so as to cover the plurality of interconnections excluding portions extending into the bonding region, forming a stepped portion by etching upper surfaces of the insulating film and the plurality of interconnections, the stepped portion located at a boundary between the solder resist and the bonding region, electrically connecting the plurality of interconnections to an integrated circuit (IC) chip through a plurality of electrode bumps, and molding a periphery of the IC chip.
  • IC integrated circuit
  • a method of manufacturing a chip-on-film which includes punching sprocket holes in an insulating film along an edge of the insulating film, the insulating film including a bonding region for bonding to an external device, and forming a plurality of interconnections on the insulating film so as to partially extend into the bonding region.
  • the method further includes forming a stepped portion by etching upper surfaces of the insulating film and the plurality of interconnections at portions located at a boundary of the bonding region, forming a solder resist so as to cover the insulating film excluding the bonding region, and so as to cover the plurality of interconnections excluding portions extending into the bonding region, electrically connecting the plurality of interconnections to an integrated circuit (IC) chip through a plurality of electrode bumps, and molding a periphery of the IC chip.
  • IC integrated circuit
  • FIG. 1 is a plan view of a chip-on-film (COF) according to an example embodiment of the inventive concept.
  • FIG. 2 is a plan view showing an example in which the COF according to the example embodiment of the inventive concept is bonded to a display panel.
  • FIG. 3 is a cross-sectional view showing an example in which the COF according to the example embodiment of the inventive concept is bonded to the display panel.
  • FIG. 4 is a view showing portions of the display panel and the COF that are bonded together.
  • FIG. 5 is a view showing a stepped portion formed in the COF.
  • FIG. 6 is a cross-sectional view taken along line A 1 -A 2 of FIG. 1 .
  • FIG. 7 is a view representing a reduction in thicknesses of an interconnection and a base film (PI) when a stepped portion is formed.
  • FIG. 8 is a view showing a state in which a solder resist, which is applied to protect an interconnection pattern of a COF, flows down into a bonding region of an output end such that a failure occurs.
  • FIG. 9 is a view showing a state in which a stepped portion is formed at an output end so that an applied solder resist is prevented from flowing down into a bonding region.
  • FIG. 10 is a flowchart for reference in describing a method of manufacturing a COF according to an example embodiment of the inventive concept.
  • FIG. 11 is a flowchart for reference in describing a method of manufacturing a COF according to another example embodiment of the inventive concept.
  • FIG. 1 is a plan view of a COF according to an example embodiment of the inventive concept.
  • FIGS. 2 and 3 are a plan view and a cross-sectional view, respectively, showing an example in which the COF according to the example embodiment of the inventive concept is bonded to a display panel.
  • the COF when laid flat is shown as lying in an x-y plane, where x and y are directions orthogonal to each other and orthogonal to a z direction.
  • a COF 100 of the inventive concept may include an insulating film 110 (e.g., polyimide (PI)), an integrated circuit (IC) chip 120 , a plurality of interconnections 130 (shown in FIG. 4 ), a solder resist 140 , and a stepped portion 150 .
  • PI polyimide
  • IC integrated circuit
  • the insulating film 110 is a base film and the plurality of interconnections 130 , that is, an interconnection pattern, may be disposed on the insulating film 110 . Further, the IC chip 120 electrically connected to the interconnection pattern may be disposed on the insulating film 110 . That is, for example, the plurality of interconnections 130 may be electrically connected to the IC chip 120 through a plurality of electrode bumps (not shown).
  • the interconnections 130 may be formed of an electrically conductive metal, for example, copper (Cu).
  • the IC chip 120 may be disposed at a central portion of the insulating film 110 .
  • Sprocket holes 112 which are provided for alignment purposes in an exposure process, are formed adjacent opposite edges of the insulating film 110 . In this example, the opposite edges of the insulating film 110 extend in the y-direction.
  • the solder resist 140 may be applied to cover a surface portion of the insulating film 110 and interconnections 130 excluding a region in which a display panel 200 and the interconnections 130 are bonded.
  • the solder resist 140 may be disposed to cover portions of the insulating film 110 and the interconnections 130 in order to protect the insulating film 110 and the interconnections 130 .
  • the solder resist 140 may be disposed to cover the insulating film 110 and the interconnections 130 in a region excluding the bonding region.
  • Output ends of the interconnections 130 may be exposed to the outside of the solder resist 140 .
  • the exposed portions of the output ends of the interconnections 130 may be bonded to a non-display region of the display panel 200 .
  • Input ends of the interconnections 130 may be exposed to the outside of the solder resist 140 .
  • the exposed portions of the input ends of the interconnections 130 may be bonded to a printed circuit board (PCB) 300 .
  • PCB printed circuit board
  • FIG. 4 is a view showing portions of the display panel and the COF that are bonded together.
  • ACF anisotropic conductive film
  • the COF 100 of the inventive concept may be bent (see FIG. 3 ) so as to be disposed opposite to a surface on which an image is displayed after being bonded to the display panel 200 .
  • An input end of the COF 100 and the PCB 300 may be electrically connected and the PCB 300 may be disposed to overlap the display panel 200 .
  • FIG. 5 is a view showing the stepped portion formed in the COF.
  • FIG. 6 is a cross-sectional view taken along line A 1 -A 2 of FIG. 1 .
  • the stepped portion 150 may be formed on a rear surface of the COF 100 . That is, the stepped portion 150 may be formed on a surface on which the interconnection pattern of the COF is disposed. The stepped portion 150 may be formed at a boundary portion between the solder resist 140 and the bonding region. The stepped portion 150 may be formed to have a predetermined width (e.g., a width of 25 ⁇ m to 75 ⁇ m in the y-direction) by etching the insulating film 110 and the plurality of interconnections 130 using a laser etching process.
  • a predetermined width e.g., a width of 25 ⁇ m to 75 ⁇ m in the y-direction
  • the insulating film 110 may be etched from an upper surface thereof by a predetermined thickness by performing a laser etching process at the boundary portion between the solder resist 140 and the bonding region. Further, the stepped portion 150 may be formed in the form of a trench (or a dam) by etching the plurality of interconnections 130 from upper surfaces thereof by a predetermined thickness.
  • the stepped portion 150 includes “steps” in both the x-direction and the y-direction. That is, in the x-direction, trenches formed in the insulating film 110 step up to and down from trenches formed in the interconnections 130 . In the y-direction, a principal surface of the insulating film 110 steps down to and up from a surface of the trenches formed in the insulating film 110 , and a principal surface of the interconnections 130 steps down to and up from surfaces of respective trenches formed in the interconnections 130 .
  • the stepped portion 150 has been described as being disposed at the boundary portion between the solder resist 140 and the bonding region.
  • the inventive concept is not limited thereto, and the boundary portion of the bonding region may be defined by forming the stepped portion 150 at an end on which the solder resist 140 is formed. That is, the boundary portion between the solder resist 140 and the bonding region may be defined by the stepped portion 150 .
  • the solder resist 140 is not present on the insulating film 110 and the interconnections 130 of the stepped portion 150 . That is, when the stepped portion 150 is formed using a laser etching process, the solder resist 140 is removed while the insulating film 110 and the interconnections 130 are etched so that the solder resist 140 is not formed on the stepped portion 150 .
  • solder resist 140 when the solder resist 140 is applied after the stepped portion 150 is formed, a portion of the solder resist 140 may remain on the insulating film 110 and the interconnections 130 of the stepped portion 150 .
  • a trench or a dam
  • the solder resist 140 may be prevented from entering the bonding region.
  • FIG. 7 is a view showing a state in which thicknesses of an interconnection and a base film (PI) are reduced when a stepped portion is formed.
  • a portion of the insulating film 110 excluding the stepped portion 150 may have a thickness “a” in the z-direction.
  • a portion of the insulating film 110 corresponding to the stepped portion 150 may have a thickness “b” in the z-direction that is less than the thickness “a”.
  • Portions of the interconnections 130 excluding the stepped portion 150 may have a thickness “c” in the z-direction.
  • Portions of the interconnections 130 corresponding to the stepped portion 150 may have thickness “d” in the z-direction that is less than the thickness “c”.
  • the stepped portion 150 may be formed by etching the insulating film 110 by 10% to 50% of a total thickness thereof. Further, the stepped portion 150 may be formed by etching the interconnections 130 by 20% to 90% of a total thickness thereof. That is, in a portion in which the stepped portion 150 is formed, the insulating film 110 has a thickness of 50% to 90% of other portions of the insulating film 110 . In the portion in which the stepped portion 150 is formed, the interconnections 130 have a thickness of 10% to 80% of the other portions of the interconnections 130 . As described above, the insulating film 110 and the interconnections 130 may be formed to have a reduced thickness in the stepped portion 150 to form a trench (or a dam) having a predetermined width.
  • FIG. 8 is a view showing a state in which a solder resist, which is applied to protect an interconnection pattern of a COF, flows down into a bonding region of an output end such that a failure occurs.
  • a solder resist 40 is applied by a screen mask printing method in order to protect a plurality of interconnections 30 disposed on a surface of an insulating film 10 .
  • a paste of the solder resist 40 is supplied onto a screen mask, a squeegee is moved to squeeze a protective region of a pattern of the interconnections 30 .
  • a region which is bonded to a display panel is left as a region in which the solder resist 40 is not applied.
  • the solder resist 40 should not be applied to a bonding region of the COF.
  • the paste of the solder resist 40 flows down into a bonding region 40 a so that the solder resist 40 enters the bonding region.
  • FIG. 9 is a view showing a state in which a stepped portion is formed at an output end so that a solder resist to be applied is prevented from flowing down.
  • the COF 100 of the inventive concept includes a stepped portion 150 having a predetermined depth (e.g., a depth of 10% to 50% of a total thickness of the insulating film or a depth of 20% to 90% of a total thickness of the interconnection) and a predetermined width (e.g., a width of 25 ⁇ m to 75 ⁇ m) at the boundary portion between the solder resist 140 and the bonding region.
  • a predetermined depth e.g., a depth of 10% to 50% of a total thickness of the insulating film or a depth of 20% to 90% of a total thickness of the interconnection
  • a predetermined width e.g., a width of 25 ⁇ m to 75 ⁇ m
  • the stepped portion 150 may be formed in the form of a straight line at the boundary portion between the solder resist 140 and the bonding region.
  • the stepped portion 150 may be formed in the form of a straight line so as to cross the plurality of interconnections 130 .
  • the stepped portion 150 may be formed at the boundary portion between the solder resist 140 and the bonding region so that the solder resist 140 may be prevented from entering the bonding region.
  • the stepped portion 150 is formed first in consideration of the width of the bonding region, and the solder resist 140 may be applied after the stepped portion 150 is formed.
  • a trench (or a dam) is formed on an interface between the bonding region and the solder resist 140 due to the stepped portion 150 . Accordingly, it is possible to prevent the paste of the solder resist 140 from flowing into the bonding region and thereby prevent the solder resist 140 from entering the bonding region.
  • the stepped portion 150 may be formed at the boundary portion between the solder resist 140 and the bonding region.
  • the solder resist 140 which has entered the bonding region is removed when the stepped portion 150 is formed so that the solder resist 140 may be prevented from entering the bonding region.
  • FIG. 10 is a flowchart for reference in describing a method of manufacturing a COF according to an example embodiment of the inventive concept.
  • sprocket holes 112 which are functional holes for aligning in an exposure process, may be formed at an edge of an insulating film 110 by performing a punching process (S 11 ).
  • an interconnection pattern may be formed on the insulating film 110 (S 12 ).
  • the interconnection pattern may include a plurality of interconnections 130 and the plurality of interconnections 130 may be formed of a metal (e.g., copper (Cu)) having a high conductivity.
  • a metal e.g., copper (Cu)
  • a solder resist 140 may be formed by applying a paste to cover the insulating film 110 and the plurality of interconnections 130 (S 13 ).
  • the solder resist 140 may be disposed to cover portions of the insulating film 110 and the plurality of interconnections 130 in order to protect the insulating film 110 and the plurality of interconnections 130 .
  • the solder resist 140 may be formed on a portion excluding a bonding region in which a display panel 200 and a COF 100 are to be bonded. That is, the solder resist 140 may be disposed to cover the insulating film 110 and the plurality of interconnections 130 in the region excluding the bonding region.
  • Output ends of the plurality of interconnections 130 may be exposed to the outside of the solder resist 140 .
  • the exposed portions of the output ends of the plurality of interconnections 130 may be bonded to a non-display region of the display panel 200 .
  • Input ends of the plurality of interconnections 130 may be exposed to the outside of the solder resist 140 .
  • the exposed portions of the input ends of the plurality of interconnections 130 may be bonded to a PCB 300 .
  • a stepped portion 150 may be formed at a boundary portion between the solder resist 140 and the bonding region (S 14 ).
  • the stepped portion 150 may be formed to have a predetermined width (e.g., a width of 25 ⁇ m to 75 ⁇ m) by etching the insulating film 110 and the plurality of interconnections 130 using a laser etching process.
  • the insulating film 110 may be etched from an upper surface thereof by a predetermined thickness by performing a laser etching process. That is, a thickness of the insulating film 110 may be reduced by performing the laser etching process.
  • the stepped portion 150 may be formed in the form of a trench (or a dam) by etching the plurality of interconnections 130 from upper surfaces thereof by a predetermined thickness. That is, thicknesses of the plurality of interconnections 130 may be reduced by performing the laser etching process.
  • the stepped portion 150 may be formed by etching the insulating film 110 by 10% to 50% of the total thickness thereof and etching the plurality of interconnections 130 by 20% to 90% of the total thickness thereof. That is, in a portion in which the stepped portion 150 is formed, the insulating film 110 may have a thickness of 50% to 90% of the other portions. In the portion in which the stepped portion 150 is formed, the plurality of interconnections 130 may have a thickness of 10% to 80% of the other portions.
  • the stepped portion 150 is formed by etching the insulating film 110 and the plurality of interconnections 130 such that the thicknesses of the insulating film 110 and the plurality of interconnections 130 are reduced, and a trench (or a dam) having a predetermined width may be formed by the stepped portion 150 .
  • the interconnection pattern and an IC chip 120 may be bonded (S 15 ).
  • the plurality of interconnections 130 may be electrically connected to the IC chip 120 through a plurality of electrode bumps.
  • the IC chip 120 may be disposed at a central portion of the insulating film 110 .
  • a periphery of the IC chip 120 may be molded with a molding material (S 16 ).
  • a liquid potting material having a constant viscosity containing a non-conductive paste (NCP), an epoxy resin, or curing agent may be used as the molding material.
  • FIG. 11 is a flowchart for reference in describing a method of manufacturing a COF according to an example embodiment of the inventive concept.
  • sprocket holes 112 which are functional holes for aligning in an exposure process, may be formed at an edge of an insulating film 110 by performing a punching process (S 21 ).
  • an interconnection pattern may be formed on the insulating film 110 (S 22 ).
  • the interconnection pattern may include a plurality of interconnections 130 and the plurality of interconnections 130 may be formed of a metal (e.g., copper (Cu)) having a high conductivity.
  • a metal e.g., copper (Cu)
  • a stepped portion 150 may be formed at a boundary portion of a bonding region (S 23 ).
  • the stepped portion 150 may be formed to have a predetermined width (e.g., a width of 25 ⁇ m to 75 ⁇ m) by etching the insulating film 110 and the plurality of interconnections 130 using a laser etching process.
  • the insulating film 110 may be etched from an upper surface thereof by a predetermined thickness by performing a laser etching process. That is, a thickness of the insulating film 110 may be reduced by performing the laser etching process.
  • the stepped portion 150 may be formed in the form of a trench (or a dam) by etching the plurality of interconnections 130 from upper surfaces thereof by a predetermined thickness. That is, thicknesses of the plurality of interconnections 130 may be reduced by performing the laser etching process.
  • the stepped portion 150 may be formed by etching the insulating film 110 by 10% to 50% of the total thickness thereof and etching the plurality of interconnections 130 by 20% to 90% of the total thickness thereof. That is, in a portion in which the stepped portion 150 is formed, the insulating film 110 may have a thickness of 50% to 90% of the other portions. In the portion in which the stepped portion 150 is formed, the plurality of interconnections 130 may have a thickness of 10% to 80% of the other portions.
  • the stepped portion 150 is formed by etching the insulating film 110 and the plurality of interconnections 130 such that the thicknesses of the insulating film 110 and the plurality of interconnections 130 are reduced, and a trench (or a dam) having a predetermined width may be formed by the stepped portion 150 .
  • a solder resist 140 may be formed by applying a paste to cover the insulating film 110 and the plurality of interconnections 130 (S 24 ).
  • the solder resist 140 may be disposed to cover portions of the insulating film 110 and the plurality of interconnections 130 in order to protect the insulating film 110 and the plurality of interconnections 130 .
  • the solder resist 140 may be formed on a portion excluding the bonding region in which the display panel 200 and the COF 100 are bonded. That is, the solder resist 140 may be disposed to cover the insulating film 110 and the plurality of interconnections 130 in the region excluding the bonding region.
  • Output ends of the plurality of interconnections 130 may be exposed to the outside of the solder resist 140 .
  • the exposed portions of the output ends of the plurality of interconnections 130 may be bonded to a non-display region of a display panel 200 .
  • Input ends of the plurality of interconnections 130 may be exposed to the outside of the solder resist 140 .
  • the exposed portions of the input ends of the plurality of interconnections 130 may be bonded to a PCB 300 .
  • the interconnection pattern and an IC chip 120 may be bonded (S 25 ).
  • the plurality of interconnections 130 may be electrically connected to the IC chip 120 through a plurality of electrode bumps.
  • the IC chip 120 may be disposed at a central portion of the insulating film 110 .
  • a periphery of the IC chip 120 may be molded with a molding material (S 26 ).
  • a liquid potting material having a constant viscosity containing an NCP, an epoxy resin, or curing agent may be used as the molding material.
  • a stepped portion may be formed, for example in the form of an elongate trench, at a boundary between a solder resist and a bonding region to inhibit the flow of solder resist into the bonding region.
  • a width tolerance of the bonding region of the COF can be reduced. Accordingly, a width of a bezel of a display device can be reduced.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Structure Of Printed Boards (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Abstract

A chip-on-film includes an insulating film including a bonding region for bonding to an external device, a plurality of interconnections disposed on the insulating film and partially extending into the bonding region, and an integrated circuit (IC) chip disposed on the insulating film so as to be electrically connected to the plurality of interconnections. The chip-on-film further includes a solder resist disposed so as to cover the insulating film excluding the bonding region and so as to cover the plurality of interconnections excluding portions extending into the bonding region, and a stepped portion located between the bonding region and the solder resist. The stepped portion forms a boundary against a flow of the solder resist into the bonding region.

Description

CROSS-REFERENCE TO RELATED APPLICATION
A claim of priority is made to Korean Patent Application No. 10-2019-0008996, filed Jan. 24, 2019, the disclosure of which is incorporated herein by reference in its entirety.
BACKGROUND
Apparatus and methods consistent with example embodiments relate to a chip-on-film (COF) and to a method of manufacturing the same.
In COF technology, a solder resist (SR) may be applied to metal interconnections formed on a polyimide (PI) surface in order to protect the metal interconnections. The SR is not to be applied, however, to a bonding region of the PI surface in which the COF is to be bonded to a printed circuit board (PCB) or a display panel. In the meantime, in the case where the COF is applied to a display panel, minimum tolerances of the bonding region are necessarily reduced as the width of a bezel surrounding the display is narrowed to comply with industry demands.
SUMMARY
According to example embodiments, a chip-on-film is provided which includes an insulating film including a bonding region for bonding to an external device, a plurality of interconnections disposed on the insulating film and partially extending into the bonding region, and an integrated circuit (IC) chip disposed on the insulating film so as to be electrically connected to the plurality of interconnections. The chip-on-film further includes a solder resist disposed so as to cover the insulating film excluding the bonding region and so as to cover the plurality of interconnections excluding portions extending into the bonding region, and a stepped portion located between the bonding region and the solder resist. The stepped portion forms a boundary against a flow of the solder resist into the bonding region.
According to example embodiments, a method of manufacturing a chip-on-film is provided which includes punching sprocket holes in an insulating film along an edge of the insulating film, the insulating film including a bonding region for bonding to an external device, and forming a plurality of interconnections on the insulating film so as to partially extend into the bonding region. The method further includes forming a solder resist so as to cover the insulating film excluding the bonding region, and so as to cover the plurality of interconnections excluding portions extending into the bonding region, forming a stepped portion by etching upper surfaces of the insulating film and the plurality of interconnections, the stepped portion located at a boundary between the solder resist and the bonding region, electrically connecting the plurality of interconnections to an integrated circuit (IC) chip through a plurality of electrode bumps, and molding a periphery of the IC chip.
According to example embodiments, a method of manufacturing a chip-on-film is provided which includes punching sprocket holes in an insulating film along an edge of the insulating film, the insulating film including a bonding region for bonding to an external device, and forming a plurality of interconnections on the insulating film so as to partially extend into the bonding region. The method further includes forming a stepped portion by etching upper surfaces of the insulating film and the plurality of interconnections at portions located at a boundary of the bonding region, forming a solder resist so as to cover the insulating film excluding the bonding region, and so as to cover the plurality of interconnections excluding portions extending into the bonding region, electrically connecting the plurality of interconnections to an integrated circuit (IC) chip through a plurality of electrode bumps, and molding a periphery of the IC chip.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a plan view of a chip-on-film (COF) according to an example embodiment of the inventive concept.
FIG. 2 is a plan view showing an example in which the COF according to the example embodiment of the inventive concept is bonded to a display panel.
FIG. 3 is a cross-sectional view showing an example in which the COF according to the example embodiment of the inventive concept is bonded to the display panel.
FIG. 4 is a view showing portions of the display panel and the COF that are bonded together.
FIG. 5 is a view showing a stepped portion formed in the COF.
FIG. 6 is a cross-sectional view taken along line A1-A2 of FIG. 1.
FIG. 7 is a view representing a reduction in thicknesses of an interconnection and a base film (PI) when a stepped portion is formed.
FIG. 8 is a view showing a state in which a solder resist, which is applied to protect an interconnection pattern of a COF, flows down into a bonding region of an output end such that a failure occurs.
FIG. 9 is a view showing a state in which a stepped portion is formed at an output end so that an applied solder resist is prevented from flowing down into a bonding region.
FIG. 10 is a flowchart for reference in describing a method of manufacturing a COF according to an example embodiment of the inventive concept.
FIG. 11 is a flowchart for reference in describing a method of manufacturing a COF according to another example embodiment of the inventive concept.
 DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS
Hereinafter, a chip-on-film (COF) and a method of manufacturing the same according to example embodiments of the inventive concept will be described with reference to the accompanying drawings.
FIG. 1 is a plan view of a COF according to an example embodiment of the inventive concept. FIGS. 2 and 3 are a plan view and a cross-sectional view, respectively, showing an example in which the COF according to the example embodiment of the inventive concept is bonded to a display panel. For purposes of explanation, the COF when laid flat is shown as lying in an x-y plane, where x and y are directions orthogonal to each other and orthogonal to a z direction.
Referring collectively to FIGS. 1 to 3, a COF 100 of the inventive concept may include an insulating film 110 (e.g., polyimide (PI)), an integrated circuit (IC) chip 120, a plurality of interconnections 130 (shown in FIG. 4), a solder resist 140, and a stepped portion 150.
The insulating film 110 is a base film and the plurality of interconnections 130, that is, an interconnection pattern, may be disposed on the insulating film 110. Further, the IC chip 120 electrically connected to the interconnection pattern may be disposed on the insulating film 110. That is, for example, the plurality of interconnections 130 may be electrically connected to the IC chip 120 through a plurality of electrode bumps (not shown). The interconnections 130 may be formed of an electrically conductive metal, for example, copper (Cu). The IC chip 120 may be disposed at a central portion of the insulating film 110. Sprocket holes 112, which are provided for alignment purposes in an exposure process, are formed adjacent opposite edges of the insulating film 110. In this example, the opposite edges of the insulating film 110 extend in the y-direction.
The solder resist 140 may be applied to cover a surface portion of the insulating film 110 and interconnections 130 excluding a region in which a display panel 200 and the interconnections 130 are bonded. The solder resist 140 may be disposed to cover portions of the insulating film 110 and the interconnections 130 in order to protect the insulating film 110 and the interconnections 130. For example, the solder resist 140 may be disposed to cover the insulating film 110 and the interconnections 130 in a region excluding the bonding region.
Output ends of the interconnections 130 may be exposed to the outside of the solder resist 140. The exposed portions of the output ends of the interconnections 130 may be bonded to a non-display region of the display panel 200. Input ends of the interconnections 130 may be exposed to the outside of the solder resist 140. The exposed portions of the input ends of the interconnections 130 may be bonded to a printed circuit board (PCB) 300.
FIG. 4 is a view showing portions of the display panel and the COF that are bonded together.
Referring to FIG. 4, the output ends of the interconnections 130 are exposed to the outside of the solder resist 140. An anisotropic conductive film (ACF) 170 may be disposed on the exposed portions of the output ends of the plurality of interconnections 130.
The COF 100 of the inventive concept may be bent (see FIG. 3) so as to be disposed opposite to a surface on which an image is displayed after being bonded to the display panel 200. An input end of the COF 100 and the PCB 300 may be electrically connected and the PCB 300 may be disposed to overlap the display panel 200.
FIG. 5 is a view showing the stepped portion formed in the COF. FIG. 6 is a cross-sectional view taken along line A1-A2 of FIG. 1.
Referring to FIGS. 1, 5, and 6, the stepped portion 150 may be formed on a rear surface of the COF 100. That is, the stepped portion 150 may be formed on a surface on which the interconnection pattern of the COF is disposed. The stepped portion 150 may be formed at a boundary portion between the solder resist 140 and the bonding region. The stepped portion 150 may be formed to have a predetermined width (e.g., a width of 25 μm to 75 μm in the y-direction) by etching the insulating film 110 and the plurality of interconnections 130 using a laser etching process. The insulating film 110 may be etched from an upper surface thereof by a predetermined thickness by performing a laser etching process at the boundary portion between the solder resist 140 and the bonding region. Further, the stepped portion 150 may be formed in the form of a trench (or a dam) by etching the plurality of interconnections 130 from upper surfaces thereof by a predetermined thickness.
In the example of FIGS. 5 and 6, the stepped portion 150 includes “steps” in both the x-direction and the y-direction. That is, in the x-direction, trenches formed in the insulating film 110 step up to and down from trenches formed in the interconnections 130. In the y-direction, a principal surface of the insulating film 110 steps down to and up from a surface of the trenches formed in the insulating film 110, and a principal surface of the interconnections 130 steps down to and up from surfaces of respective trenches formed in the interconnections 130.
The stepped portion 150 has been described as being disposed at the boundary portion between the solder resist 140 and the bonding region. The inventive concept is not limited thereto, and the boundary portion of the bonding region may be defined by forming the stepped portion 150 at an end on which the solder resist 140 is formed. That is, the boundary portion between the solder resist 140 and the bonding region may be defined by the stepped portion 150.
For example, in the manufacturing process, when the stepped portion 150 is formed after the solder resist 140 is applied, the solder resist 140 is not present on the insulating film 110 and the interconnections 130 of the stepped portion 150. That is, when the stepped portion 150 is formed using a laser etching process, the solder resist 140 is removed while the insulating film 110 and the interconnections 130 are etched so that the solder resist 140 is not formed on the stepped portion 150.
For example, in the manufacturing process, when the solder resist 140 is applied after the stepped portion 150 is formed, a portion of the solder resist 140 may remain on the insulating film 110 and the interconnections 130 of the stepped portion 150. When the solder resist 140 is formed after the stepped portion 150 is formed, a trench (or a dam) may be formed by the stepped portion 150 so that the solder resist 140 may be prevented from entering the bonding region.
FIG. 7 is a view showing a state in which thicknesses of an interconnection and a base film (PI) are reduced when a stepped portion is formed.
Referring to FIG. 7, a portion of the insulating film 110 excluding the stepped portion 150 may have a thickness “a” in the z-direction. A portion of the insulating film 110 corresponding to the stepped portion 150 may have a thickness “b” in the z-direction that is less than the thickness “a”. Portions of the interconnections 130 excluding the stepped portion 150 may have a thickness “c” in the z-direction. Portions of the interconnections 130 corresponding to the stepped portion 150 may have thickness “d” in the z-direction that is less than the thickness “c”.
The stepped portion 150 may be formed by etching the insulating film 110 by 10% to 50% of a total thickness thereof. Further, the stepped portion 150 may be formed by etching the interconnections 130 by 20% to 90% of a total thickness thereof. That is, in a portion in which the stepped portion 150 is formed, the insulating film 110 has a thickness of 50% to 90% of other portions of the insulating film 110. In the portion in which the stepped portion 150 is formed, the interconnections 130 have a thickness of 10% to 80% of the other portions of the interconnections 130. As described above, the insulating film 110 and the interconnections 130 may be formed to have a reduced thickness in the stepped portion 150 to form a trench (or a dam) having a predetermined width.
FIG. 8 is a view showing a state in which a solder resist, which is applied to protect an interconnection pattern of a COF, flows down into a bonding region of an output end such that a failure occurs.
Referring to FIG. 8, when a COF is manufactured generally, a solder resist 40 is applied by a screen mask printing method in order to protect a plurality of interconnections 30 disposed on a surface of an insulating film 10. When a paste of the solder resist 40 is supplied onto a screen mask, a squeegee is moved to squeeze a protective region of a pattern of the interconnections 30.
A region which is bonded to a display panel is left as a region in which the solder resist 40 is not applied. As described above, the solder resist 40 should not be applied to a bonding region of the COF. However, the paste of the solder resist 40 flows down into a bonding region 40 a so that the solder resist 40 enters the bonding region.
As semiconductor devices are becoming highly integrated, a density of an interconnection pattern of a COF is increased and a solder resist 40 is unevenly formed in a bonding region, and thus a bonding failure of the display panel and the COF may occur. In order to reduce the number of bonding failures, a tolerance of ±90 μm should be ensured to avoid the solder resist 40 from flowing down into the bonding region. When the COF is applied to a display device, this tolerance disadvantageously increases the width of a bezel of a display device.
FIG. 9 is a view showing a state in which a stepped portion is formed at an output end so that a solder resist to be applied is prevented from flowing down.
Referring to FIG. 9, the COF 100 of the inventive concept includes a stepped portion 150 having a predetermined depth (e.g., a depth of 10% to 50% of a total thickness of the insulating film or a depth of 20% to 90% of a total thickness of the interconnection) and a predetermined width (e.g., a width of 25 μm to 75 μm) at the boundary portion between the solder resist 140 and the bonding region.
The stepped portion 150 may be formed in the form of a straight line at the boundary portion between the solder resist 140 and the bonding region. The stepped portion 150 may be formed in the form of a straight line so as to cross the plurality of interconnections 130. The stepped portion 150 may be formed at the boundary portion between the solder resist 140 and the bonding region so that the solder resist 140 may be prevented from entering the bonding region.
For example, in the manufacturing process, the stepped portion 150 is formed first in consideration of the width of the bonding region, and the solder resist 140 may be applied after the stepped portion 150 is formed. A trench (or a dam) is formed on an interface between the bonding region and the solder resist 140 due to the stepped portion 150. Accordingly, it is possible to prevent the paste of the solder resist 140 from flowing into the bonding region and thereby prevent the solder resist 140 from entering the bonding region.
For example, in the manufacturing process, after the solder resist 140 is applied, the stepped portion 150 may be formed at the boundary portion between the solder resist 140 and the bonding region. In the manufacturing process, even when a portion of the solder resist 140 enters the bonding region, the solder resist 140 which has entered the bonding region is removed when the stepped portion 150 is formed so that the solder resist 140 may be prevented from entering the bonding region.
FIG. 10 is a flowchart for reference in describing a method of manufacturing a COF according to an example embodiment of the inventive concept.
Referring to FIGS. 1, 5, and 10, sprocket holes 112, which are functional holes for aligning in an exposure process, may be formed at an edge of an insulating film 110 by performing a punching process (S11).
Next, an interconnection pattern may be formed on the insulating film 110 (S12).
The interconnection pattern may include a plurality of interconnections 130 and the plurality of interconnections 130 may be formed of a metal (e.g., copper (Cu)) having a high conductivity.
Next, a solder resist 140 may be formed by applying a paste to cover the insulating film 110 and the plurality of interconnections 130 (S13).
For example, the solder resist 140 may be disposed to cover portions of the insulating film 110 and the plurality of interconnections 130 in order to protect the insulating film 110 and the plurality of interconnections 130. The solder resist 140 may be formed on a portion excluding a bonding region in which a display panel 200 and a COF 100 are to be bonded. That is, the solder resist 140 may be disposed to cover the insulating film 110 and the plurality of interconnections 130 in the region excluding the bonding region.
Output ends of the plurality of interconnections 130 may be exposed to the outside of the solder resist 140. In a subsequent manufacturing process, the exposed portions of the output ends of the plurality of interconnections 130 may be bonded to a non-display region of the display panel 200. Input ends of the plurality of interconnections 130 may be exposed to the outside of the solder resist 140. In the subsequent manufacturing process, the exposed portions of the input ends of the plurality of interconnections 130 may be bonded to a PCB 300.
Next, a stepped portion 150 may be formed at a boundary portion between the solder resist 140 and the bonding region (S14).
For example, the stepped portion 150 may be formed to have a predetermined width (e.g., a width of 25 μm to 75 μm) by etching the insulating film 110 and the plurality of interconnections 130 using a laser etching process. The insulating film 110 may be etched from an upper surface thereof by a predetermined thickness by performing a laser etching process. That is, a thickness of the insulating film 110 may be reduced by performing the laser etching process. Further, the stepped portion 150 may be formed in the form of a trench (or a dam) by etching the plurality of interconnections 130 from upper surfaces thereof by a predetermined thickness. That is, thicknesses of the plurality of interconnections 130 may be reduced by performing the laser etching process.
As shown in FIG. 7, the stepped portion 150 may be formed by etching the insulating film 110 by 10% to 50% of the total thickness thereof and etching the plurality of interconnections 130 by 20% to 90% of the total thickness thereof. That is, in a portion in which the stepped portion 150 is formed, the insulating film 110 may have a thickness of 50% to 90% of the other portions. In the portion in which the stepped portion 150 is formed, the plurality of interconnections 130 may have a thickness of 10% to 80% of the other portions. As described above, the stepped portion 150 is formed by etching the insulating film 110 and the plurality of interconnections 130 such that the thicknesses of the insulating film 110 and the plurality of interconnections 130 are reduced, and a trench (or a dam) having a predetermined width may be formed by the stepped portion 150.
Next, the interconnection pattern and an IC chip 120 may be bonded (S15).
The plurality of interconnections 130 may be electrically connected to the IC chip 120 through a plurality of electrode bumps. The IC chip 120 may be disposed at a central portion of the insulating film 110.
Next, a periphery of the IC chip 120 may be molded with a molding material (S16).
A liquid potting material having a constant viscosity containing a non-conductive paste (NCP), an epoxy resin, or curing agent may be used as the molding material.
FIG. 11 is a flowchart for reference in describing a method of manufacturing a COF according to an example embodiment of the inventive concept.
Referring to FIGS. 1, 5, and 11, sprocket holes 112, which are functional holes for aligning in an exposure process, may be formed at an edge of an insulating film 110 by performing a punching process (S21).
Next, an interconnection pattern may be formed on the insulating film 110 (S22).
The interconnection pattern may include a plurality of interconnections 130 and the plurality of interconnections 130 may be formed of a metal (e.g., copper (Cu)) having a high conductivity.
Next, a stepped portion 150 may be formed at a boundary portion of a bonding region (S23).
For example, the stepped portion 150 may be formed to have a predetermined width (e.g., a width of 25 μm to 75 μm) by etching the insulating film 110 and the plurality of interconnections 130 using a laser etching process. The insulating film 110 may be etched from an upper surface thereof by a predetermined thickness by performing a laser etching process. That is, a thickness of the insulating film 110 may be reduced by performing the laser etching process. Further, the stepped portion 150 may be formed in the form of a trench (or a dam) by etching the plurality of interconnections 130 from upper surfaces thereof by a predetermined thickness. That is, thicknesses of the plurality of interconnections 130 may be reduced by performing the laser etching process.
As shown in FIG. 7 described previously, the stepped portion 150 may be formed by etching the insulating film 110 by 10% to 50% of the total thickness thereof and etching the plurality of interconnections 130 by 20% to 90% of the total thickness thereof. That is, in a portion in which the stepped portion 150 is formed, the insulating film 110 may have a thickness of 50% to 90% of the other portions. In the portion in which the stepped portion 150 is formed, the plurality of interconnections 130 may have a thickness of 10% to 80% of the other portions. As described above, the stepped portion 150 is formed by etching the insulating film 110 and the plurality of interconnections 130 such that the thicknesses of the insulating film 110 and the plurality of interconnections 130 are reduced, and a trench (or a dam) having a predetermined width may be formed by the stepped portion 150.
Next, a solder resist 140 may be formed by applying a paste to cover the insulating film 110 and the plurality of interconnections 130 (S24).
For example, the solder resist 140 may be disposed to cover portions of the insulating film 110 and the plurality of interconnections 130 in order to protect the insulating film 110 and the plurality of interconnections 130. The solder resist 140 may be formed on a portion excluding the bonding region in which the display panel 200 and the COF 100 are bonded. That is, the solder resist 140 may be disposed to cover the insulating film 110 and the plurality of interconnections 130 in the region excluding the bonding region.
Output ends of the plurality of interconnections 130 may be exposed to the outside of the solder resist 140. In the subsequent manufacturing process, the exposed portions of the output ends of the plurality of interconnections 130 may be bonded to a non-display region of a display panel 200. Input ends of the plurality of interconnections 130 may be exposed to the outside of the solder resist 140. In the subsequent manufacturing process, the exposed portions of the input ends of the plurality of interconnections 130 may be bonded to a PCB 300.
Next, the interconnection pattern and an IC chip 120 may be bonded (S25).
The plurality of interconnections 130 may be electrically connected to the IC chip 120 through a plurality of electrode bumps. The IC chip 120 may be disposed at a central portion of the insulating film 110.
Next, a periphery of the IC chip 120 may be molded with a molding material (S26).
A liquid potting material having a constant viscosity containing an NCP, an epoxy resin, or curing agent may be used as the molding material.
According to the example embodiments of the inventive concept, a stepped portion may be formed, for example in the form of an elongate trench, at a boundary between a solder resist and a bonding region to inhibit the flow of solder resist into the bonding region. As such, a width tolerance of the bonding region of the COF can be reduced. Accordingly, a width of a bezel of a display device can be reduced.
While the embodiments of the inventive concept have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various modifications may be made without departing from the scope of the inventive concept and without changing essential features thereof. Therefore, the above-described embodiments should be considered in a descriptive sense only and not for purposes of limitation.

Claims (20)

What is claimed is:
1. A chip-on-film comprising:
an insulating film including a bonding region for bonding to an external device;
a plurality of interconnections disposed on the insulating film and partially extending into the bonding region;
an integrated circuit (IC) chip disposed on the insulating film so as to be electrically connected to the plurality of interconnections;
a solder resist disposed so as to cover the insulating film excluding the bonding region and so as to cover the plurality of interconnections excluding portions extending into the bonding region; and
a stepped portion located between the bonding region and the solder resist, the stepped portion forming a boundary against a flow of the solder resist into the bonding region.
2. The chip-on-film of claim 1, wherein the stepped portion is a trench located in surfaces of the insulating film and the plurality of interconnections.
3. The chip-on-film of claim 2, wherein a portion of the insulating film excluding the trench has a first thickness and a portion of the insulating film at the trench has a second thickness which is less than the first thickness.
4. The chip-on-film of claim 3, wherein the second thickness is 10% to 50% less than the first thickness.
5. The chip-on-film of claim 2, wherein a portion of each of the plurality of interconnections excluding the stepped portion has a first thickness and a portion of each of the plurality of interconnections corresponding to the stepped portion has a second thickness that is less than the first thickness.
6. The chip-on-film of claim 5, wherein the second thickness is 20% to 90% less than the first thickness.
7. The chip-on-film of claim 1, wherein the stepped portion extends in a straight line so as to cross the plurality of interconnections.
8. The chip-on-film of claim 1, wherein the stepped portion has a width of 25 μm to 75 μm.
9. The chip-on-film of claim 1, wherein the bonding region is located at an output end of the chip-on-film.
10. The chip-on-film of claim 1, wherein the solder resist is not present in the stepped portion.
11. A method of manufacturing a chip-on-film, the method comprising:
punching sprocket holes in an insulating film along an edge of the insulating film, the insulating film including a bonding region for bonding to an external device;
forming a plurality of interconnections on the insulating film so as to partially extend into the bonding region;
forming a solder resist so as to cover the insulating film excluding the bonding region, and so as to cover the plurality of interconnections excluding portions extending into the bonding region;
forming a stepped portion by etching upper surfaces of the insulating film and the plurality of interconnections, the stepped portion located at a boundary between the solder resist and the bonding region;
electrically connecting the plurality of interconnections to an integrated circuit (IC) chip through a plurality of electrode bumps; and
molding a periphery of the IC chip.
12. The method of claim 11, wherein, when the stepped portion is formed, thicknesses of the insulating film and the plurality of interconnections are reduced by etching the upper surfaces of the insulating film and the plurality of interconnections with a laser.
13. The method of claim 12, wherein, when the stepped portion is formed, 10% to 50% of a total thickness of the insulating film is etched.
14. The method of claim 12, wherein, when the stepped portion is formed, 20% to 90% of a total thickness of the plurality of interconnections is etched.
15. The method of claim 12, wherein the stepped portion is formed to have a width of 25 μm to 75 μm.
16. A method of manufacturing a chip-on-film, the method comprising:
punching sprocket holes in an insulating film along an edge of the insulating film, the insulating film including a bonding region for bonding to an external device;
forming a plurality of interconnections on the insulating film so as to partially extend into the bonding region;
forming a stepped portion by etching upper surfaces of the insulating film and the plurality of interconnections at portions located at a boundary of the bonding region;
forming a solder resist so as to cover the insulating film excluding the bonding region, and so as to cover the plurality of interconnections excluding portions extending into the bonding region;
electrically connecting the plurality of interconnections to an integrated circuit (IC) chip through a plurality of electrode bumps; and
molding a periphery of the IC chip.
17. The method of claim 16, wherein, when the stepped portion is formed, thicknesses of the insulating film and the plurality of interconnections are reduced by etching the upper surfaces of the insulating film and the plurality of interconnections with a laser.
18. The method of claim 17, wherein, when the stepped portion is formed, 10% to 50% of a total thickness of the insulating film is etched.
19. The method of claim 17, wherein, when the stepped portion is formed, 20% to 90% of a total thickness of the plurality of interconnections is etched.
20. The method of claim 17, wherein the stepped portion is formed to have a width of 25 μm to 75 μm.
US16/533,440 2019-01-24 2019-08-06 Chip-on-film and method of manufacturing the same Active US10879208B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020190008996A KR102471275B1 (en) 2019-01-24 2019-01-24 Chip on film and method of manufacturing the same
KR10-2019-0008996 2019-01-24

Publications (2)

Publication Number Publication Date
US20200243474A1 US20200243474A1 (en) 2020-07-30
US10879208B2 true US10879208B2 (en) 2020-12-29

Family

ID=71732855

Family Applications (1)

Application Number Title Priority Date Filing Date
US16/533,440 Active US10879208B2 (en) 2019-01-24 2019-08-06 Chip-on-film and method of manufacturing the same

Country Status (4)

Country Link
US (1) US10879208B2 (en)
KR (1) KR102471275B1 (en)
CN (1) CN111477593A (en)
TW (1) TWI786337B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11282717B2 (en) * 2018-03-30 2022-03-22 Intel Corporation Micro-electronic package with substrate protrusion to facilitate dispense of underfill between a narrow die-to-die gap

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102791239B1 (en) * 2020-06-08 2025-04-04 삼성디스플레이 주식회사 Chip on film, display device, method of fabricating chip on film, device for fabricating chip on film
US12154837B2 (en) * 2021-01-22 2024-11-26 Sciperio, Inc Seamless interconnect thresholds using dielectric fluid channels
KR20220134319A (en) 2021-03-26 2022-10-05 스템코 주식회사 Circuit board and electronic apparatus including the same
KR20230042969A (en) 2021-09-23 2023-03-30 엘지이노텍 주식회사 Flexible printed circuit board, cof module and electronic device comprising the same

Citations (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980020497A (en) 1996-09-09 1998-06-25 김광호 Structure of the tap package to prevent short
JP2000323530A (en) 1999-05-06 2000-11-24 Mitsui Mining & Smelting Co Ltd Manufacture of tab tape and apparatus for applying solder resist thereto
US20040070057A1 (en) * 2002-09-30 2004-04-15 Kazuaki Yoshiike COF tape carrier, semiconductor element, COF semiconductor device, and method for manufacturing of COF semiconductor device
JP2004281861A (en) * 2003-03-18 2004-10-07 Toray Ind Inc Film with adhesive for semiconductor device, laminated film with metal foil, adhesive sheet for semiconductor device and semiconductor device using the same
US20040262758A1 (en) * 2003-04-22 2004-12-30 Seiko Epson Corporation Electronic device and method of manufacturing the same, and electronic instrument
US20050218513A1 (en) * 2004-03-30 2005-10-06 Toshiharu Seko Semiconductor apparatus, manufacturing method thereof, semiconductor module apparatus using semiconductor apparatus, and wire substrate for semiconductor apparatus
JP2005310838A (en) * 2004-04-16 2005-11-04 Hitachi Constr Mach Co Ltd Electromagnetic drive unit
US20050248521A1 (en) * 2000-09-28 2005-11-10 Nec Lcd Technologies, Ltd LCD device having scanning lines and common lines
US20050285277A1 (en) * 2004-06-25 2005-12-29 Kwon Yong-Hwan Circuit film with bump, film package using the same, and related fabrication methods
US20060071303A1 (en) 2004-10-06 2006-04-06 Chung-Sun Lee Film substrate of a semiconductor package and a manufacturing method
KR20060133672A (en) 2005-06-21 2006-12-27 삼성전자주식회사 Tape carrier package and display device having same
US20070057369A1 (en) * 2005-09-13 2007-03-15 Matsushita Electric Industrial Co., Ltd. Wiring board and method for manufacturing the same, and semiconductor device
US20080111249A1 (en) * 2006-11-09 2008-05-15 Nec Electronics Corporation Semiconductor device and method for manufacturing same
US7579552B2 (en) 2005-08-12 2009-08-25 Samsung Electronics Co., Ltd. Tab tape for tape carrier package
US20090273076A1 (en) * 2007-07-20 2009-11-05 Choi Kyong-Sei Tape for heat dissipating member, chip on film type semiconductor package including heat dissipating member, and elctronic apparatus including the same
US7649246B2 (en) * 2005-05-24 2010-01-19 Samsung Electronics Co., Ltd. Tab package connecting host device element
US7671454B2 (en) 2006-05-12 2010-03-02 Sharp Kabushiki Kaisha Tape carrier, semiconductor apparatus, and semiconductor module apparatus
US20110044017A1 (en) * 2008-07-02 2011-02-24 Omron Corporation Electronic component
US20130032939A1 (en) * 2011-08-04 2013-02-07 Chipmos Technologies Inc. Chip package structure
US20130175528A1 (en) * 2012-01-09 2013-07-11 Samsung Electronics Co., Ltd. Chip on film package including test pads and semiconductor devices including the same
US20140300849A1 (en) * 2013-04-05 2014-10-09 Samsung Electronics Co., Ltd. Chip-on-film package and device assembly including the same
US9113545B2 (en) * 2011-12-20 2015-08-18 Samsung Electronics Co., Ltd. Tape wiring substrate and chip-on-film package including the same
US20160197020A1 (en) * 2015-01-02 2016-07-07 Samsung Electronics Co., Ltd. Film for semiconductor package, semiconductor package using film and display device including the same
US20160218065A1 (en) * 2015-01-23 2016-07-28 Jeong-kyu Ha Semiconductor packages and package modules using the same
US9572248B2 (en) * 2015-01-14 2017-02-14 Samsung Display Co., Ltd. Display device
US20170062370A1 (en) * 2015-08-31 2017-03-02 Shinko Electric Industries Co., Ltd. Electronic component device
US20170287814A1 (en) * 2016-04-05 2017-10-05 Samsung Electronics Co., Ltd. Chip-on-film semiconductor packages and display apparatus including the same
US20170358762A1 (en) * 2016-06-10 2017-12-14 Samsung Display Co., Ltd. Display device and method of manufacturing the same
US20180322848A1 (en) * 2017-05-03 2018-11-08 Innolux Corporation Display device
US20190051593A1 (en) * 2017-08-10 2019-02-14 Japan Display Inc. Display device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3554533B2 (en) * 2000-10-13 2004-08-18 シャープ株式会社 Chip-on-film tape and semiconductor device
JP4615388B2 (en) * 2005-07-25 2011-01-19 Ｏｋｉセミコンダクタ株式会社 Semiconductor package and manufacturing method thereof
CN1921100A (en) * 2005-08-26 2007-02-28 南茂科技股份有限公司 Tape for film-on-chip packaging, structure and manufacturing method thereof
KR102254761B1 (en) * 2013-09-13 2021-05-25 삼성디스플레이 주식회사 Cof package, cof package array including the same, and display device
KR20160110861A (en) * 2015-03-13 2016-09-22 삼성디스플레이 주식회사 Flexible circuit substrate and display device including the same
JP6528272B2 (en) * 2015-04-22 2019-06-12 Ｔｉａｎｍａ Ｊａｐａｎ株式会社 Connection substrate and display device

Patent Citations (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980020497A (en) 1996-09-09 1998-06-25 김광호 Structure of the tap package to prevent short
JP2000323530A (en) 1999-05-06 2000-11-24 Mitsui Mining & Smelting Co Ltd Manufacture of tab tape and apparatus for applying solder resist thereto
US20050248521A1 (en) * 2000-09-28 2005-11-10 Nec Lcd Technologies, Ltd LCD device having scanning lines and common lines
US20040070057A1 (en) * 2002-09-30 2004-04-15 Kazuaki Yoshiike COF tape carrier, semiconductor element, COF semiconductor device, and method for manufacturing of COF semiconductor device
JP2004281861A (en) * 2003-03-18 2004-10-07 Toray Ind Inc Film with adhesive for semiconductor device, laminated film with metal foil, adhesive sheet for semiconductor device and semiconductor device using the same
US20040262758A1 (en) * 2003-04-22 2004-12-30 Seiko Epson Corporation Electronic device and method of manufacturing the same, and electronic instrument
US20050218513A1 (en) * 2004-03-30 2005-10-06 Toshiharu Seko Semiconductor apparatus, manufacturing method thereof, semiconductor module apparatus using semiconductor apparatus, and wire substrate for semiconductor apparatus
JP2005310838A (en) * 2004-04-16 2005-11-04 Hitachi Constr Mach Co Ltd Electromagnetic drive unit
US20050285277A1 (en) * 2004-06-25 2005-12-29 Kwon Yong-Hwan Circuit film with bump, film package using the same, and related fabrication methods
US7190073B2 (en) * 2004-06-25 2007-03-13 Samsung Electronics Co., Ltd. Circuit film with bump, film package using the same, and related fabrication methods
US20060071303A1 (en) 2004-10-06 2006-04-06 Chung-Sun Lee Film substrate of a semiconductor package and a manufacturing method
US7649246B2 (en) * 2005-05-24 2010-01-19 Samsung Electronics Co., Ltd. Tab package connecting host device element
KR20060133672A (en) 2005-06-21 2006-12-27 삼성전자주식회사 Tape carrier package and display device having same
US7579552B2 (en) 2005-08-12 2009-08-25 Samsung Electronics Co., Ltd. Tab tape for tape carrier package
US20070057369A1 (en) * 2005-09-13 2007-03-15 Matsushita Electric Industrial Co., Ltd. Wiring board and method for manufacturing the same, and semiconductor device
US7671454B2 (en) 2006-05-12 2010-03-02 Sharp Kabushiki Kaisha Tape carrier, semiconductor apparatus, and semiconductor module apparatus
US20080111249A1 (en) * 2006-11-09 2008-05-15 Nec Electronics Corporation Semiconductor device and method for manufacturing same
US20090273076A1 (en) * 2007-07-20 2009-11-05 Choi Kyong-Sei Tape for heat dissipating member, chip on film type semiconductor package including heat dissipating member, and elctronic apparatus including the same
US20110044017A1 (en) * 2008-07-02 2011-02-24 Omron Corporation Electronic component
US20130032939A1 (en) * 2011-08-04 2013-02-07 Chipmos Technologies Inc. Chip package structure
US9113545B2 (en) * 2011-12-20 2015-08-18 Samsung Electronics Co., Ltd. Tape wiring substrate and chip-on-film package including the same
US20130175528A1 (en) * 2012-01-09 2013-07-11 Samsung Electronics Co., Ltd. Chip on film package including test pads and semiconductor devices including the same
US20140300849A1 (en) * 2013-04-05 2014-10-09 Samsung Electronics Co., Ltd. Chip-on-film package and device assembly including the same
US20160197020A1 (en) * 2015-01-02 2016-07-07 Samsung Electronics Co., Ltd. Film for semiconductor package, semiconductor package using film and display device including the same
US9572248B2 (en) * 2015-01-14 2017-02-14 Samsung Display Co., Ltd. Display device
US20160218065A1 (en) * 2015-01-23 2016-07-28 Jeong-kyu Ha Semiconductor packages and package modules using the same
US20170062370A1 (en) * 2015-08-31 2017-03-02 Shinko Electric Industries Co., Ltd. Electronic component device
US20170287814A1 (en) * 2016-04-05 2017-10-05 Samsung Electronics Co., Ltd. Chip-on-film semiconductor packages and display apparatus including the same
US20170358762A1 (en) * 2016-06-10 2017-12-14 Samsung Display Co., Ltd. Display device and method of manufacturing the same
US20180322848A1 (en) * 2017-05-03 2018-11-08 Innolux Corporation Display device
US20190051593A1 (en) * 2017-08-10 2019-02-14 Japan Display Inc. Display device

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
Machine translation of Abstract, Myungcheon Kim, Korean Pat. Pub. No. KR 1998-0020497, translation date: Aug. 27, 2020, Espacenet, all pages. (Year: 2020). *
Machine translation, Fujimaru, Japanese Pat. Pub. No. JP 2004-281861, translation date: Aug. 27, 2020, Espacenet, all pages. (Year: 2020). *
Machine translation, Ikuta, Japanese Pat. Pub. No. JP 2000-323530, translation date: Aug. 27, 2020, Espacenet, all pages. (Year: 2020). *
Machine translation, Kim, Korean Pat. Pub. No. KR 10-2006-0133672, translation date: Aug. 27, 2020, Espacenet, all pages. (Year: 2020). *
Machine translation, Kim, Korean Pat. Pub. No. KR 1998-0020497, translation date: Aug. 27, 2020, KIPO, all pages. (Year: 2020). *
Machine translation, Nagao, Japanese Pat. Pub. No. JP 2005-310848, translation date: Aug. 27, 2020, Espacenet, all pages. (Year: 2020). *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11282717B2 (en) * 2018-03-30 2022-03-22 Intel Corporation Micro-electronic package with substrate protrusion to facilitate dispense of underfill between a narrow die-to-die gap
US11776821B2 (en) 2018-03-30 2023-10-03 Intel Corporation Micro-electronic package with substrate protrusion to facilitate dispense of underfill between a narrow die-to-die gap

Also Published As

Publication number Publication date
TW202029440A (en) 2020-08-01
KR20200092016A (en) 2020-08-03
CN111477593A (en) 2020-07-31
KR102471275B1 (en) 2022-11-28
TWI786337B (en) 2022-12-11
US20200243474A1 (en) 2020-07-30

Similar Documents

Publication Publication Date Title
US10879208B2 (en) Chip-on-film and method of manufacturing the same
US8336201B2 (en) Method of manufacturing printed circuit board having flow preventing dam
CN100552929C (en) Semiconductor device, manufacturing method thereof, semiconductor module device, and wiring substrate
CN101785106B (en) Semiconductor device including semiconductor constituent and manufacturing method thereof
JP4568215B2 (en) CIRCUIT DEVICE AND CIRCUIT DEVICE MANUFACTURING METHOD
US10667387B2 (en) Accurate positioning and alignment of a component during processes such as reflow soldering
TW200522828A (en) Printed wiring board and semiconductor device
US20080123041A1 (en) Electrode, device and electronic apparatus having the device
KR100631331B1 (en) Film Carrier Tape for Electronic Component Mounting and Manufacturing Method Thereof
KR101477818B1 (en) Wiring circuit board and manufacturing method thereof
US20070241462A1 (en) Wiring board, semiconductor device using the same, and method for manufacturing wiring board
CN106298714B (en) semiconductor structure
EP0645807A1 (en) Semiconductor device
US6853080B2 (en) Electronic device and method of manufacturing the same, and electronic instrument
US8530754B2 (en) Printed circuit board having adaptable wiring lines and method for manufacturing the same
CN112638054A (en) Manufacturing method of circuit board
JP2003133714A (en) Printed-wiring board and manufacturing method thereof
JP3821426B2 (en) Electronic component mounting board
JP2008235745A (en) Method for manufacturing sheet with which two or more unit substrate is connected and sheet to which two or more unit substrate is connected
JP2006253253A (en) Method of manufacturing flexible circuit board
KR100986294B1 (en) Manufacturing method of printed circuit board
JP2005209789A (en) Method for manufacturing bonding structure of circuit board
JP4973513B2 (en) Tape carrier for semiconductor device, method for manufacturing tape carrier for semiconductor device, and semiconductor device
JP2009071159A (en) Flexible wiring board and bare chip mounting method
KR100536947B1 (en) Method of fabricating Film Carrier Tape

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

AS Assignment

Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:JUNG, JAE MIN;REEL/FRAME:050020/0147

Effective date: 20190723

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4