TWM629323U - Flip Chip Package Structure - Google Patents

Abstract

The present invention provides a flip chip package structure, which includes a silicon substrate, a single graphene copper layer and a copper pillar. The silicon substrate has an abutting surface, and at least one conductive base is attached to the butting surface. A graphene copper layer covers the conductive base. The copper column is erected on the butt surface and connected to the graphene copper layer.

Description

Flip Chip Package Structure

The present invention relates to chip packaging, especially a flip-chip packaging structure with a single-layer metal bottom layer on its copper pillar pins and a manufacturing method thereof.

In the current chip packaging process, wire bonding or flip chip bonding is commonly used for electrical conduction between the chip and the substrate. With the continuous shrinking of integrated circuit technology and the development of high frequency and high pin count, traditional wire bonding packages can no longer meet the electrical requirements. Compared with wire bonding, flip chip bonding can configure more pins in the same surface area. Flip Chip is a surface-down bonding of substrates using copper pillars on the crystal surface as pins. In addition to increasing the density of chip pins, it can also reduce noise interference, enhance electrical performance, improve heat dissipation, and reduce package size. The copper pillar pins of the flip chip package structure are connected to the pin conductors of the circuit on the chip through a metal layer (Under Bump Metallization, UBM). The UBM metal layer is usually composed of a stack of multi-layer metal layers. For example, an existing UBM metal layer structure covers a titanium metal layer on the substrate (pad, usually aluminum) and further covers the titanium metal layer. The metal layer is formed by combining the metal conductive point and the copper metal layer with the titanium metal layer to facilitate further electroplating copper on the copper metal layer to form a copper bump. The titanium metal material itself is expensive, and the UBM metal layer needs to be sputtered or evaporated layer by layer, and the process cost is not easy to reduce.

In view of this, the creator of the present invention has devoted himself to the research and application of the theory, and tried his best to solve the above-mentioned problems, which is the goal of the creator's improvement.

The present invention provides a flip chip package structure, which includes a silicon substrate, a single graphene copper layer and a copper pillar. The silicon substrate has an abutting surface, and at least one conductive base is attached to the butting surface. A graphene copper layer covers the conductive base. The copper column is erected on the butt surface and connected to the graphene copper layer.

The thickness of the graphene copper layer in the flip-chip package structure of this creation is between 0.01 μm and 1.5 μm. The graphene copper layer includes a copper body, the copper body is layered and the butting surface of the silicon-clad substrate is embedded, and a plurality of graphene sheets are embedded in the copper body, and the graphene sheets are dispersed and distributed in the copper body. The thickness of the copper body is between 0.01 μm and 1.5 μm.

In the flip-chip package structure of the present invention, a solder is provided on the top of the copper pillar. The solder is an alloy containing at least tin. The solder further contains silver, nickel or graphene.

In the flip-chip package structure of this creation, the graphene-copper layer in the flip-chip package structure has graphene, and the bonding force between graphene and copper, aluminum and other metals is stronger than that between metals, so it can resist Greater shear stress, so it can be used as a single-layer plating as the metal layer under the pin to connect the copper post and the aluminum conductive base.

100: Silicon substrate

101: Butt Surface

110: Conductive base

300: Passivation layer

400: Graphene copper layer

410: Copper body

420: Graphene Sheet

500: photoresist layer

501: Recess

600: Copper Pillar

700: Solder

a~g: steps

FIG. 1 and FIG. 2 are flow charts of steps of a method for manufacturing a flip chip package structure according to a preferred embodiment of the present invention.

FIG. 3 to FIG. 11 are schematic diagrams of each step of the manufacturing method of the flip chip package structure according to the preferred embodiment of the present invention.

FIG. 12 is a schematic diagram of a flip-chip package structure according to a preferred embodiment of the present invention.

Referring to FIGS. 1 and 2 , a preferred embodiment of the present invention provides a method for manufacturing a flip chip package structure, which includes the following steps: First, as shown in FIGS. 1 and 3 , in step a, at least one silicon substrate 100 is provided The silicon substrate 100 has a docking surface 101 for docking the package, and at least one conductive base 110 is attached on the docking surface 101 , and the conductive base 110 is preferably made of aluminum. Preferably, a circuit is arranged on the silicon substrate 100 , and the conductive base 110 is connected to the circuit on the silicon substrate 100 , and the conductive base 110 may be a part of the circuit. Therefore, generally speaking, a plurality of conductive bases are attached to the docking surface 101 . 110. In this step, according to different process requirements, a single chip may be provided as the silicon substrate 100 , or a wafer may be provided as the silicon substrate 100 and the wafer includes a plurality of chips for batch packaging. For the convenience of description, only a part of the silicon substrate 100 and a cross-sectional view of one of the conductive bases 110 are shown in this creative embodiment to represent the description.

As shown in FIG. 1 and FIG. 6 , following step a, in step b, a graphene copper layer 400 is covered on the conductive base 110 as an Under Bump Metallization (UBM) layer of the copper pillar 600 . In this embodiment, the graphene copper layer 400 is plated on the conductive base 110 with a graphene copper target by sputtering or vapor deposition. As shown in FIG. 7 , the thickness of the graphene-copper layer 400 is between 0.01 μm and 1.5 μm. The structure of the graphene-copper layer 400 includes a copper body 410 . The copper body 410 is layered and the butting surface of the silicon-clad substrate 100 is formed. 101 , the thickness of the copper body 410 is between 0.01 μm and 1.5 μm, a plurality of graphene sheets 420 are embedded in the copper body 410 , and the graphene sheets 420 are dispersed in the copper body 410 . The graphene sheet 420 is a tiny fragment of a planar structure composed of carbon atoms arranged and bonded in a hexagonal arrangement.

As shown in FIGS. 2 and 5 to 6 , specifically, step b may include the following sub-steps: in step b1 shown in FIG. 4 , a passivation layer 300 (passivation) is covered on the butting surface 101 , For insulation and protection, the passivation layer 300 can be polyimide (PI) or silicon nitride (Si3N4). And the passivation layer 300 is etched to expose the passivation layer 300 from the conductive base 110 . in continuation Step b2 of step b1 covers the graphene copper layer 400 on the conductive base 110 . Specifically, in step b2, the graphene copper layer 400 is superimposed on the butt surface 101 so that the graphene copper layer 400 covers the passivation layer 300 on the aforementioned photoresist layer 500 and at the same time directly contacts the conductive base covering the exposed passivation layer 300 110.

As shown in FIG. 1 and FIG. 8 , following step b, in step c, a photoresist layer 500 (Photo Resistor, PR) is superimposed and covered on the butting surface 101 of the silicon substrate 100. The main components of the photoresist are resin (Resin) and The photosensitive agent, in this embodiment, the photoresist layer 500 covers the graphene copper layer 400 . Then, the photoresist layer 500 is etched to form a cavity 501 corresponding to the conductive base 110 , and the portion of the graphene copper layer 400 corresponding to the conductive base 110 is exposed at the bottom of the cavity 501 .

As shown in FIG. 1 and FIG. 9 , following step c, in step d, a copper material is electroplated on the graphene copper layer 400 , and the copper material is accumulated in the cavity 501 to form a copper pillar 600 . Specifically, a wet process is used in this step, and the silicon substrate 100 is immersed in an electrolyte containing copper ions, so that the copper ions are plated on the portion of the graphene copper layer 400 exposed at the bottom of the cavity 501, and the copper plated material is It accumulates along the inside of the cavity 501 to form a cylinder.

As shown in FIGS. 1 , 10 and 11 , following step d, in step e, the photoresist layer 500 (see FIG. 10 ) and the rest of the graphene copper layer 400 covered by the photoresist layer 500 are successively removed by etching (see FIG. 10 ) See Figure 11). Thereby, the copper pillars 600 are respectively fixed on the conductive bases 110 on the butting surface 101 of the silicon substrate 100 by the graphene copper layers 400 to complete the flip-chip packaging structure for the subsequent flip-chip packaging process.

As shown in FIG. 1 and FIGS. 8 to 11 , a step f may be further included between the step c and the step d. In the step f, a solder 700 is electroplated on the top of the copper pillar 600 , and the solder 700 is an alloy containing at least tin, and In this embodiment, the solder 700 preferably further includes silver, nickel or the graphene sheet 420 as described above. Specifically, after the step c is completed, the top of the copper pillar 600 is exposed in the cavity 501 , and the solder 700 is also plated on the exposed surface of the top of the copper pillar 600 by wet electroplating, and the solder 700 is plated along the surface of the copper pillar 600 . of the cavity 501 accumulated within. Furthermore, as shown in FIG. 1 and FIG. 12 , after the step e is completed, the solder 700 may be heated and softened in a reflow step g to form a hemispherical cohesion.

As shown in FIG. 12 , the aforementioned flip-chip package structure at least includes a silicon substrate 100 , a single layer of graphene copper 400 and a copper pillar 600 . The silicon substrate 100 has a docking surface 101 , and at least one conductive base 110 is attached on the docking surface 101 , and the conductive base 110 is preferably made of aluminum. Preferably, a circuit is arranged on the silicon substrate 100 , and the conductive base 110 is connected to the circuit on the silicon substrate 100 , and the conductive base 110 may be a part of the circuit. Therefore, generally speaking, a plurality of conductive bases are attached to the docking surface 101 . 110. The graphene copper layer 400 covers the conductive base 110 . The thickness of the graphene copper layer 400 is between 0.01 μm and 1.5 μm. The copper pillar 60 is erected on the butting surface 101 and connected to the graphene copper layer 400 .

As shown in FIG. 7 and FIG. 12 , the graphene copper layer 400 includes a copper body 410 , the copper body 410 is layered and the butting surface 101 of the silicon-clad substrate 100 is embedded, the copper body 410 is embedded with a plurality of graphene sheets 420 and graphene The sheets 420 are dispersed within the copper body 410 . The thickness of the copper body 410 is between 0.01 μm and 1.5 μm.

A solder 700 is provided on top of the copper pillar 600 . The solder 700 is an alloy containing at least tin. And the solder further includes silver, nickel or the aforementioned graphene sheet 420 .

In the method for manufacturing a flip chip package structure of the present invention, the graphene copper layer 400 in the flip chip package structure has graphene, and the bonding force between graphene and copper, aluminum and other metals is stronger than the bonding force between metals. Therefore, it can resist greater shear stress, so it can be used as an under-pin metal layer (UBM) with a single-layer plating layer to connect the copper pillar 600 and the aluminum conductive base 110 .

The above descriptions are only preferred embodiments of this creation, and are not intended to limit the patent scope of this creation. Other equivalent changes using the patent spirit of this creation shall all belong to the patent scope of this creation.

100: Silicon substrate

101: Butt Surface

110: Conductive base

300: Passivation layer

400: Graphene copper layer

600: Copper Pillar

700: Solder

Claims (7)

A flip-chip package structure, comprising: a silicon substrate, the silicon substrate has a butt surface, and at least one conductive base is attached to the butt surface; a single graphene copper layer covers the conductive base; and a copper A column is erected on the butt surface and connected to the graphene copper layer. The flip chip package structure according to claim 1, wherein the thickness of the graphene copper layer is between 0.01 μm and 1.5 μm. The flip-chip package structure of claim 1, wherein the graphene copper layer comprises a copper body, the copper body is layered and covers the butt surface of the silicon substrate, the copper body is embedded with a plurality of graphene sheets and The graphene sheets are dispersed in the copper body. The flip chip package structure of claim 3, wherein the thickness of the copper body is between 0.01 μm and 1.5 μm. The flip-chip package structure of claim 1, wherein a solder is provided on top of the copper pillar. The flip-chip package structure of claim 5, wherein the solder is an alloy containing at least tin. The flip-chip package structure of claim 6, wherein the solder further comprises silver, nickel or graphene.

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