TWM560677U - Driving circuit - Google Patents

Abstract

A driving circuit includes a prior-stage operation amplifier, a feedback output stage circuit, a switch circuit and a driving stage circuit. The prior-stage operation amplifier includes a gain stage circuit, and receives an input signal and a feedback output signal. The gain stage circuit generates a prior-stage amplified signal. The feedback output stage circuit generates the feedback output signal according to the prior-stage amplified signal. The switch circuit turns on or off a signal transmission channel according to a mode selection signal. The driving stage circuit receives the prior-stage amplified signal through the signal transmission channel, and generates a driving output signal according to the prior-stage amplified signal.

Description

Drive circuit

This novel creation relates to a driving circuit, and particularly to a driving circuit for driving a display panel.

With the advancement of electronic technology, electronic devices have become an essential tool in people's lives. Providing high-quality display interfaces on electronic devices has become an important function of electronic products.

In the display driving device of the conventional technology, the driving circuit therein needs to start the charging operation of the driving voltage after receiving the display data. As a result, it takes a certain settling time for the drive circuit to provide stable and correct drive voltage. In other words, pixels cannot display the correct brightness (or color) in the fastest time, resulting in a decrease in display quality. On the other hand, as the size and resolution of the display panel increases, the pixel voltage writing time is shortened, and the length of the connection path between the pixel and the driver increases and causes the load of the driver to increase. Will be more serious and become an important issue for designers in this field.

The novel creation provides a driving circuit, which can quickly provide stable driving signals.

The drive circuit created by the novel includes a pre-stage operational amplifier, a feedback output stage circuit, a switch circuit, and a drive stage circuit. The pre-stage operational amplifier has a first input terminal and a second input terminal to receive the input signal and the feedback output signal, respectively, and includes a gain stage circuit. The gain stage circuit has an output terminal to generate a pre-amplified signal. The feedback output stage circuit is coupled to the gain stage circuit, and generates a feedback output signal according to the amplified signal of the previous stage. The switch circuit is coupled to the pre-stage operational amplifier and turns on or off the signal transmission channel according to the mode selection signal. The driver stage circuit is coupled to the switch circuit, and receives the previous stage amplified signal through the signal transmission channel, and generates a drive output signal according to the previous stage amplified signal.

Based on the above, the novel creation uses the feedback output stage circuit to maintain the generation of the previous amplified signal according to the feedback output signal generated by the feedback output stage circuit when the drive circuit is in the non-driving mode, and the drive circuit is in the drive mode Next, the driver stage circuit quickly generates the driver output signal according to the pre-amplified signal that has been precharged, effectively improving the display quality of the driving pixels.

In order to make the above-mentioned features and advantages of the creation of the new model more obvious and understandable, the embodiments are specifically described below and described in detail in conjunction with the attached drawings.

100, 200, 400, 500 ‧‧‧ drive circuit

110, 210, 410, 510

120, 220‧‧‧ Feedback output stage circuit

520‧‧‧Voltage selector

130, 230, 530‧‧‧ switch circuit

521、531‧‧‧Part I

522, 532‧‧‧The second part of the circuit

140, 240‧‧‧ driver stage circuit

111, 411‧‧‧ input level

112, 412‧‧‧Gain stage circuit

V _IN ‧‧‧ input signal

AVF‧‧‧Feedback output signal

SA‧‧‧Pre-amplified signal

SP‧‧‧Preamp amplifier signal

SN‧‧‧Preamplifier signal

LD, LD1, LD2 ‧‧‧ mode selection signal

LDB, LDB1, LDB2 ‧‧‧ reverse mode selection signal

190‧‧‧ load

RL‧‧‧Resistance

CL‧‧‧Capacitor

SW1-SW5, SWC1, SWC2 ‧‧‧ switch

VDDA‧‧‧Power terminal

GNDA‧‧‧Reference ground

OUT‧‧‧ drive output signal

211_1A, 511_1A‧‧‧First differential pair

211_1B, 511_1B‧‧‧second differential pair

211_2A, 511_2A‧‧‧First current source

211_2B, 511_2B‧‧‧second current source

213A, 513A‧‧‧First active load

213B, 513B‧‧‧Second active load

P1A, P2A, N1A, N2A, N10, P10, N11P, P11P, N3A, N4A, P4A, P3A, N5-N8, P5-P8, P9FB, N9FB, P9D, N9D, MD1-MD4, MF1-MF4, MR1- MR4, MS1-MS4‧‧‧transistor

AVBP1, AVBP2, AVBP3, AVBP4, AVBN1, AVBN2, AVBN3, AVBN4, AVBN5, AVBP5 ‧‧‧ bias voltage

SW1-SW5, SW31-SW33, SW41-SW44, SWA1-SWA8, SWB, SW511, SW512, SW515, SW516, SW513, SW514, SW517, SW518, SW521, SW522, SW523, SW524, SW52B, SW525, SW526, SW527, SW528‧‧‧switch

SPD, SND‧‧‧signal

TR1‧‧‧Pre-drive time interval

TR2‧‧‧ drive time interval

420P, 420N, 550, 560‧‧‧ feedback output sub-circuit

V _INP , V _INN ‧‧‧ input signal

AVFP, AVFN‧‧‧ feedback sub-output signal

440P, 440N, 541, 542

VMID‧‧‧Second power supply

514A, 514B, 514C ‧‧‧ impedance provider

CHGB, CHG, NCHGB, NCHG‧‧‧signal

AVBN5 [P], AVBP5 [P], AVBP5 [N], AVBN5 [N] ‧‧‧bias voltage

SP1, SN1, SP2, SN2 ‧‧‧ preamplifier signal

VPW, VNW‧‧‧Voltage

FIG. 1A is a schematic diagram of a driving circuit of an embodiment of the novel creation.

FIG. 1B and FIG. 1C respectively illustrate schematic diagrams of different implementations of the driving circuit of the novel creation embodiment.

FIG. 2 illustrates a circuit diagram of the driving circuit of the embodiment of FIG. 1A created by the new form.

FIG. 3 shows a waveform diagram of a mode selection signal of the inventive embodiment.

FIG. 4 is a schematic diagram of another implementation manner of the driving circuit of the inventive creation example.

FIG. 5 is a circuit diagram of the driving circuit of the embodiment of FIG. 4 created by the novel.

Please refer to FIG. 1A, which is a schematic diagram of a driving circuit according to an embodiment of the present invention. The driving circuit 100 can be arranged in the source driver of the display device and used to drive the pixels of the display panel. The driving circuit 100 includes a pre-stage operational amplifier 110, a feedback output stage circuit 120, a switching circuit 130, and a driving stage circuit 140. The pre-stage operational amplifier 110 includes an input stage 111 and a gain stage circuit 112. The input stage 111 provides a first input terminal and a second input terminal. The first input terminal and the second input terminal are respectively used to receive the input signal V _IN and the feedback output signal AVF. The gain stage circuit 112 has an output terminal to generate the front stage The signal SA is amplified. In this embodiment, the front-stage amplified signal SA includes the front-stage amplified sub-signal SP and the front-stage amplified sub-signal SN.

The feedback output stage circuit 120 is coupled to the gain stage circuit 112, and receives the pre-amplifier sub-signal SP and the pre-amplifier sub-signal SN. The feedback output stage circuit 120 generates a feedback output signal according to the preamplifier sub-signal SP and the preamplifier sub-signal SN No. AVF, and directly provided to the second input terminal of the pre-stage operational amplifier 110.

The switch circuit 130 is coupled to the pre-stage operational amplifier 110 and turns on or off a signal transmission channel according to the mode selection signal LD and the reverse mode selection signal LDB. The aforementioned signal transmission channel is used to transmit the pre-amplifier sub-signal SP and the pre-amplifier sub-signal SN to the driver stage circuit 140. Specifically, when the signal transmission channel is turned on, the pre-amplifier sub-signal SP and the pre-amplifier sub-signal SN are transmitted to the driver stage circuit 140 through the transmission channel. In this way, the driving stage circuit 140 can generate the driving output signal OUT according to the preceding stage amplifying sub-signal SP and the preceding stage amplifying sub-signal SN, and used to drive the load 190. On the other hand, if the signal transmission channel is disconnected, the pre-amplifier sub-signal SP and the pre-amplifier sub-signal SN cannot be transmitted to the driver stage circuit 140. At the same time, the driver stage circuit 140 stops outputting the driver output signal OUT.

In this embodiment, the load 190 may have a resistance R _L and a capacitance C _L , but it is not limited thereto.

In this embodiment, the switch circuit 130 includes switches SW1, SW2, SW3 and switches SW4, SW5 formed of transmission gates. The switches SW1 and SW2 constitute the aforementioned signal transmission channel, and are turned on or off according to the mode selection signal LD and the reverse mode selection signal LDB. The mode selection signal LD and the reverse mode selection signal LDB are reversed, and the on and off states of the switches SW1 and SW2 are the same.

In addition, when the switches SW1 and SW2 are turned off, the switches SW4 and SW5 can be turned on, and the two input terminals of the driver stage circuit 140 are respectively coupled to the power supply terminal VDDA and the reference ground terminal GNDA to avoid the input terminal Floating floating) phenomenon. In addition, when the switches SW1 and SW2 are turned on, the switches SW4 and SW5 are turned off.

On the other hand, the switch SW3 is coupled between the output terminal of the driver stage circuit 140 and the output terminal of the feedback output stage circuit 120. When the driving stage circuit 140 generates the driving output signal OUT, the switch SW3 is turned on and provides the driving output signal OUT as the feedback output signal AVF, wherein the driving output signal OUT at this time is substantially the same as the feedback output signal AVF The voltage value is the same. On the contrary, when the driving stage circuit 140 stops generating the driving output signal OUT, the switch SW3 is turned off. That is, the on-off state of the switch SW3 is the same as the on-off state of the switches SW1, SW2, and is controlled by the mode selection signal LD and the reverse mode selection signal LDB.

It is worth mentioning that the mode selection signal LD is used to indicate whether the driving circuit 100 is in the pre-driving time interval or the driving time interval. During the pre-drive time interval, the display data is latched and becomes the input signal V _IN . Based on the condition that the input signal V _{IN is} not yet stable, the driver stage circuit 140 does not provide the driver output signal OUT to drive the pixels. At the same time, the feedback output stage circuit 120 in this embodiment keeps operating and provides the feedback output signal AVF to the pre-stage operational amplifier 110 so that the pre-stage operational amplifier 110 can generate The pre-amplified signal SA performs precharge operation. In this way, when the pre-driving time period ends and enters the driving time period, the pre-stage operational amplifier 110 can quickly provide a stable pre-stage amplified signal SA to the driving stage circuit 140, and the driving stage circuit 140 can quickly provide the driving output signal OUT drives the pixels to improve the display quality of the pixels.

Please refer to FIGS. 1B and 1C below. FIG. 1B and FIG. 1C respectively illustrate schematic diagrams of different implementations of the driving circuit of the novel creation embodiment. In FIG. 1B, the driving circuit 100 further includes a switch SW31. The switch SW31 is connected in series to the path of the feedback output signal AVF generated by the feedback output stage circuit 120. When the switch SW3 is turned on, the switch SW31 can be turned off according to the mode selection signal LD and the reverse mode selection signal LDB, and the coupling relationship between the output terminal of the feedback output stage circuit 120 and the input stage 111 is broken On, to avoid the mismatch between the output stage and the driver stage due to component mismatch, resulting in output voltage deviation. In contrast, when the switch SW3 is turned off, the switch SW31 can be turned on according to the mode selection signal LD and the reverse mode selection signal LDB, and the feedback output signal AVF is provided by the feedback output stage circuit 120 to the input stage 111 to maintain Operation of the pre-stage operational amplifier 110.

In FIG. 1C, unlike FIG. 1B, the driving circuit 100 further includes switches SW32, SW33, SWC1, and SWC2. The switches SW32 and SW33 are respectively connected in series to the path where the gain stage circuit 112 generates the preamplifier sub-signal SP and the preamplifier sub-signal SN, and is turned on or off according to the mode selection signal LD and the reverse mode selection signal LDB . The switch SWC1 is coupled between the power terminal VDDA and the switch SW32, and the switch SWC2 is coupled between the reference ground GNDA and the switch SW33. The on-off state of the switches SWC1, SWC2 may be opposite to the on-off state of the switches SW32, SW33. When the feedback output stage circuit 120 does not need to generate the feedback output signal AVF, the switches SW32 and SW33 can be turned off according to the mode selection signal LD and the reverse mode selection signal LDB at the same time, and the feedback output stage circuit 120 is maintained at Inactive state to reduce power consumption. In contrast, when the feedback output stage circuit 120 When the feedback output signal AVF needs to be generated, the switches SW32 and SW33 can be turned on at the same time according to the mode selection signal LD and the reverse mode selection signal LDB, and provide the preamplifier sub-signal SP and the preamplifier sub-signal SN to the feedback The output stage circuit 120 enables the feedback output stage circuit 120 to continuously generate the feedback output signal AVF.

Please refer to FIG. 2 below. FIG. 2 illustrates a circuit diagram of the driving circuit of the embodiment of FIG. The driving circuit 200 includes a pre-stage operational amplifier 210, a feedback output stage circuit 220, a switching circuit 230, and a driving stage circuit 240. The pre-stage operational amplifier 210 includes a plurality of first differential pairs 211_1A, a plurality of second differential pairs 211_1B, a first current source 211_2A, a second current source 211_2B, a first active load 213A, a second active load 213B, a power supply A first impedance provider composed of crystals N10, P10 and a second impedance provider composed of transistors N11P, P11P.

The first differential pair 211_1A and the second differential pair 211_1B form the input stage of the pre-stage operational amplifier 210. The first differential pair 211_1A includes a first differential pair formed by transistors N2A, N1A. The second differential pair 211_1B includes a second differential pair formed by transistors P2A, P1A. The forms of the first differential pair 211_1A and the second differential pair 211_1B are complementary. In addition, the number of differential pairs included in the first differential pair 211_1A and the second differential pair 211_1B may be one or more, and there is no fixed limit.

The first current source 211-2A includes transistors N3A and N4A. Transistor N4A receives bias voltage AVBN2, and transistor N3A receives bias voltage AVBN1. The first current source 211_2A is coupled between the first differential pair 211_1A and the reference ground GNDA. The second current source 211-2B includes transistors P4A and P3A. Electricity The crystal P4A receives the bias voltage AVBP2, and the transistor P3A receives the bias voltage AVBP1. The second current source 211_2B is coupled between the second differential pair 211_1B and the power supply terminal VDDA. In this embodiment, the shapes of the first current source 211-2A and the second current source 211-2B are complementary.

The first active load 213A is composed of transistors P5-P8, and the second active load 213B is composed of transistors N5-N8. The first active load 213A is coupled between the power supply terminal VDDA and the first differential pair 211_1A. The second active load 213B is coupled between the reference ground GNDA and the second differential pair 211_1B. The shapes of the first active load 213A and the second active load 213B are complementary. The first ends of the transistors P5 and P6 are connected to the power supply terminal VDDA, the control ends of the transistors P5 and P6 are coupled to each other and to the second end of the transistor P7, and the second ends of the transistors P5 and P6 are respectively It is coupled to the first ends of the transistors P7 and P8. In addition, the control terminals of the transistors P7 and P8 collectively receive the bias voltage AVBP4. The first ends of the transistors N5 and N6 are connected to the reference ground GNDA, the control ends of the transistors N5 and N6 are coupled to each other and to the first end of the transistor N7, and the second ends of the transistors N5 and N6 are respectively coupled Connect to the second end of transistors N7 and N8. In addition, the control terminals of the transistors N7 and N8 jointly receive the bias voltage AVBN4.

The first impedance provider composed of transistors N10 and P10 is coupled between the first active load 213A and the second active load 213B, and the second impedance provider composed of transistors N11P and P11P is coupled to the first active load 213A Between the second active load 213B. The second impedance provider composed of transistors N11P and P11P cooperates with the first active load 213A and the second active load 213B to form the gain stage circuit of the front-stage operational amplifier 210, and generates the first-stage amplified sub-signal SP and the first two The previous-stage amplified signal SA of the previous-stage amplified sub-signal SN.

In detail, the transistors N10 and P10 are coupled in parallel between the second end of the transistor P7 and the first end of the transistor N7. The control terminals of the transistors N10 and P10 receive the bias voltages AVBN3 and AVBP3, respectively. Transistors N11P and P11P are coupled in parallel between the second end of transistor P8 and the first end of transistor N8. The control terminals of the transistors N11P and P11P receive the bias voltages AVBN5 and AVBP5, respectively.

The feedback output stage circuit 220 includes transistors P9FB and N9FB. The transistor P9FB and the transistor N9FB are connected in series between the power supply terminal VDDA and the reference ground terminal GND. The control terminals of the transistor P9FB and the transistor N9FB respectively receive the first preamplifier sub-signal SP and the second preamplifier sub-signal SN, and generate a feedback output signal at the end point where the transistor P9FB and the transistor N9FB are coupled AVF.

The switch circuit 230 includes switches SW1-SW5. Among them, the switches SW1, SW2, SW3 are constructed by the transmission gate, and the switches SW4, SW5 are constructed by the transistor PSW1 and the transistor NSW1, respectively. The switches SW1, SW2 are controlled by the mode selection signal LD and the reverse mode selection signal LDB to be turned on or off, and provide signal transmission channels to respectively transmit the first preamplifier sub-signal SP and the second preamplifier sub-signal SN To driver stage circuit 240. The switch SW3 is controlled by the mode selection signal LD and the reverse mode selection signal LDB to be turned on or off, and when turned on, is used to transmit the drive output signal OUT as the feedback output signal AVF. The switches SW4 and SW5 are respectively used as a pull-up switch and a pull-down switch, and are turned on when the switches SW1 and SW2 are turned off, respectively providing operating power and a reference ground voltage to the two input terminals of the driver stage circuit 240. Among them, the on and off states of the switches SW1, SW2, SW3 are the same, The on-off states of the switches SW4 and SW5 are the same, and the on-off states of the switches SW1 and SW4 are complementary, and the on-off states of the switches SW2 and SW5 are complementary.

The driver stage circuit 240 includes a transistor P9D and a transistor N9D. Transistor P9D and transistor N9D receive signals SPD and SND, respectively. When the switches SW1 and SW2 are turned on, the signals SPD and SND are equal to the first preamplifier sub-signal SP and the second preamplifier sub-signal SN respectively. At this time, the driver stage circuit 240 generates a driving output signal OUT to drive pixels. On the other hand, when the switches SW1 and SW2 are turned off, the signals SPD and SND are equal to the operating power supply and the reference ground voltage, respectively. At this time, the driver stage circuit 240 stops generating the drive output signal OUT and makes the drive output signal OUT high The state of impedance.

Please refer to FIG. 3 below. FIG. 3 illustrates a waveform diagram of a mode selection signal in the creative embodiment of the present invention. The mode selection signal LD and the reverse mode selection signal LDB are used to instruct the driving circuit to operate in the pre-driving time interval or the driving time interval. In the embodiment of FIG. 2, when the mode selection signal LD is a logic high level signal (the reverse mode selection signal LDB is a logic low level signal), the driving circuit 200 operates in the pre-driving time interval TR1. When the mode selection signal LD is a logic low level signal (the reverse mode selection signal LDB is a logic high level signal), the driving circuit 200 operates in the driving time interval TR2.

Of course, in other embodiments, the designer can change the relationship between the logic level of the mode selection signal LD and the operation mode of the driving circuit according to requirements. The waveform shown in FIG. 3 is only an example and is not a necessary limitation.

Please refer to FIG. 4 below. FIG. 4 is a schematic diagram of another embodiment of the driving circuit of the inventive creation example. The driving circuit 400 includes a pre-stage operational amplifier 410, a voltage selector composed of switches SW41-SW44, feedback output stage sub-circuits 420P and 420N, a switching circuit composed of switches SWA1-SWA8 and SWB, and a driving stage sub-circuit 440P, 440N. The pre-stage operational amplifier 410 includes an input stage 411 and a gain stage circuit 412. The input stage 411 receives the input signal V _{INP of the} first polarity or the input signal V _{INN of the} second polarity, and receives the feedback output signal AVF. Wherein, the first polarity may be positive polarity, and the second polarity may be negative polarity opposite to the first polarity. The gain stage circuit 412 is used to generate the preamplifier sub-signals SP and SN according to the difference between the feedback output signal AVF and the input signal V _{INP of the} first polarity or the input signal V _INN of the second polarity.

The voltage selector selects and provides the preamplifier sub-signals SP and SN to the feedback output stage sub-circuit 420P or the feedback output stage sub-circuit 420N according to the polarity of the input signal. Specifically, when the input stage 411 receives the positive input signal V _INP , the switches SW41 and SW42 in the voltage selector are turned on (the switches SW43 and SW44 are turned off), and the preamplifier sub-signals SP and SN are transmitted to the feedback Output stage sub-circuit 420P. On the contrary, if the input stage 411 receives the negative input signal V _INN , the switches SW43 and SW44 in the voltage selector are turned on (the switches SW41 and SW42 are turned off), and the preamplifier sub-signals SP and SN are transmitted to the feedback output Level sub-circuit 420N.

The feedback output stage sub-circuits 420P and 420N respectively generate the feedback sub-output signals AVFP and AVFN. It is worth noting that, based on the function of the voltage selector, the feedback sub-output signals AVFP and AVFN are not generated at the same time. That is, when the input stage 411 receives the positive input signal V _INP , the feedback output stage sub-circuit 420P generates the feedback sub-output signal AVFP as the feedback output signal AVF, and when the input stage 411 receives the negative polarity When the signal V _INN is input, the feedback output stage sub-circuit 420N generates the feedback sub-output signal AVFN as the feedback output signal AVF.

On the other hand, the switches SWA1 and SWA2 in the switch circuit form a signal transmission channel to transmit the preamplifier sub-signals SP and SN to the driving subcircuit 440P, and the switches SWA3 and SWA4 form another signal transmission channel to transmit the preamplifier The signals SP, SN go to the driving sub-circuit 440N. Specifically, when the front-stage amplified sub-signals SP and SN are generated corresponding to the positive input signal V _INP , the switches SWA1 and SWA2 are turned on, and the switches SWA3 and SWA4 are turned off, and the front-stage amplified sub-signals SP and SN are transmitted. To drive sub-circuit 440P. When the preamplifier signals SP and SN are generated corresponding to the negative input signal V _INN , the switches SWA3 and SWA4 are turned on, and the switches SWA1 and SWA2 are turned off, and the preamplifier signals SP and SN are transmitted to the driver subcircuit 440N.

Corresponding to the on-off action of switches SWA1-SWA2, the on-off state of switches SW5, SW6 is opposite to that of switches SWA1-SWA2, and corresponding to the on-off action of switches SWA3-SWA4, the on-off state of switches SW7, SW8 Opposite to switches SWA3-SWA4.

Incidentally, the details of the operation of the switch SWB of this embodiment are the same as the details of the operation of the switch SW3 of the drive circuit 100, and will not be repeated here.

One of the driving stage sub-circuits 440P and 440N receives the previous stage amplification sub-signals SP and SN from the voltage selector to generate a driving output signal OUT to drive the load 490. Among them, the driving stage sub-circuit 440P is used to generate the first polarity (positive Polarity) driving output signal OUT, and the driving stage sub-circuit 440N is used to generate the driving output signal OUT of the second polarity (negative polarity).

Please pay special attention here. In this embodiment, the driver stage sub-circuit 440P is coupled to the power supply terminal VDDA to receive the first power supply as the operating power supply, and receives the second power supply VMID as the reference ground power supply. The driving stage sub-circuit 440N receives the second power VMID as the operating power and is coupled to the reference ground GNDA to receive the third power as the reference ground power. Wherein, the first power supply is greater than the second power supply VMID, and the second power supply VMID is greater than the third power supply.

It is worth mentioning that the driving circuit 400 of the embodiment of the present invention can be used to generate driving output signals of different polarities in different time intervals, which can be effectively applied to pixels that require polarity inversion, such as LCD pixels. The driving circuit 100 can also be used to generate driving output signals of different polarities. The difference between the driving circuit 400 and 100 is that the driving circuit 400 is a circuit architecture of a full voltage combined with a half voltage power supply, and the driving circuit 100 is a circuit architecture of a full voltage power supply.

Please refer to FIG. 5 below. FIG. 5 illustrates a circuit diagram of the driving circuit of the embodiment of FIG. 4 according to the present invention. The driving circuit 500 includes a pre-stage operational amplifier 510, a feedback output stage sub-circuit 550 constructed by transistors MF1, MF2, a feedback output stage sub-circuit 560 constructed by transistors MF3, MF4, a voltage selector 520, and a switching circuit 530 And driver stage circuits 541, 542 composed of transistors MD1-MD4. The pre-stage operational amplifier 510 includes a first differential pair 511_1A, a second differential pair 511_1B, a first current source 511_2A, a second current source 511_2B, a first active load 513A, a second active load 513B, and first to third impedances Providers 514A, 514B, 514C. among them, Unlike the aforementioned embodiment of FIG. 2, the second impedance provider 514B provided in the pre-stage operational amplifier 510 in this embodiment is coupled to the first active load 513A and the second active load through transistors MR1-MR2 513B, the third impedance provider 514C is coupled to the first active load 513A and the second active load 513B through the transistors MR3-MR4. Transistors MR1-MR2 are controlled by signals NCHGB and NCHG, respectively, and transistors MR3-MR4 are controlled by signals CHGB and CHG, respectively. The second impedance provider 514B includes transistors MS1 and MS2 coupled in parallel, wherein the types of the transistors MS1 and MS2 are complementary and controlled by the bias voltages AVBN5 [P] and AVBP5 [P], respectively. The third impedance provider 514C includes transistors MS3 and MS4 coupled in parallel, wherein the types of the transistors MS3 and MS4 are complementary and controlled by the bias voltages AVBN5 [N] and AVBP5 [N], respectively.

The second impedance provider 514B composed of transistors MS1 and MS2, together with the first active load 513A and the second active load 513B, forms a gain stage circuit of the pre-stage operational amplifier 510 and generates a pre-amplifier sub-signal SP1 including the first polarity , SN1. The third impedance provider 514C composed of transistors MS3 and MS4 together with the first active load 513A and the second active load 513B forms the gain stage circuit of the pre-stage operational amplifier 510, and generates the pre-amplifier sub-signal SP2 including the second polarity SN2. Wherein, both ends of the second impedance provider 514B provide the first-stage preamplifier sub-signals SP1, SN1, and both ends of the third impedance provider 514C provide the second-polarity pre-amplifier sub-signals SP2, SN2.

The voltage selector 520 includes a first partial circuit 521 and a second partial circuit 522. The first part of the circuit 521 includes switches SW511, SW512, SW515, SW516, the second partial circuit 522 includes switches SW513, SW514, SW517, SW518. Among them, the switches SW511 and SW512 are controlled by the signals NCHGB and NCHG, and are used to provide the preamplifier sub-signals SP1, SN1 to the transistors MF1 and MF2. The switches SW515 and SW516 are controlled by the signals NCHG and NCHGB, respectively, and are used to keep the input terminals of the transistors MF1 and MF2 from being floated. The switches SW513 and SW514 are controlled by the signals CHGB and CHG, and are used to provide the preamplifier sub-signals SP2 and SN2 to the transistors MF3 and MF4. The switches SW517 and SW518 are controlled by the signals CHG and CHGB, respectively, and are used to keep the input terminals of the transistors MF3 and MF4 from being floated.

Transistors MF1, MF2 form a feedback output stage sub-circuit 550, and transistors MF3, MF4 form another feedback output stage sub-circuit 560. It should be noted that the transistors MF1 and MF2 are connected in series between the power supply terminal VDDA and the second power supply VMID, and the transistors MF3 and MF4 are connected in series between the second power supply VMID and the reference ground terminal GNDA. Corresponding to the transistor MF2, the second terminal of the switch SW516 receives the voltage VPW, and corresponding to the transistor MF3, the first terminal of the switch SW517 receives the voltage VNW. In this embodiment, the output terminals of the two feedback output stage sub-circuits are coupled to each other and generate a feedback sub-output signal AVF. Wherein, the two feedback output stage sub-circuits do not operate simultaneously, and at the same time, one of the two feedback output stage sub-circuits provides the feedback sub-output signal AVF.

The switch circuit 530 includes a first partial circuit 531 and a second partial circuit 532. The first partial circuit 531 includes switches SW521, SW522, SW523, SW524, and SW52B. The second part of the circuit 532 includes switches SW525, SW526, SW527 and SW528. The switches SW521, SW522, SW523, and SW524 are turned on or off according to the mode selection signal LD1 and the reverse mode selection signal LDB1, and the switch SW52B is turned on or off according to the mode selection signal LD and the reverse mode selection signal LDB. Wherein, when the switches SW521 and SW522 are turned on, a signal transmission channel is provided to transmit the preamplifier sub-signals SP1 and SN1 to the driving sub-circuit 541. In addition, the switches SW525, SW526, SW527 and SW528 are turned on or off according to the mode selection signal LD2 and the reverse mode selection signal LDB2, wherein the switches SW525 and SW526 are turned on to provide signal transmission channels to transmit the preamplifier sub-signals SP2 and SN2 To driver stage subcircuit 542.

The switch SW52B is turned on or off according to the mode selection signal LD, and is turned off in the pre-driving time zone, and is turned on in the driving time zone. When the switch SW52B is turned on, the drive output signal OUT generated by one of the drive stage sub-circuits 541 and 542 is used as the feedback output signal AVF. In contrast, when the switch SW52B is turned off, the feedback output signal AVF is provided by the feedback output stage sub-circuit.

It is worth noting that the driver stage sub-circuit 541 is coupled to the power supply terminal VDDA to receive the operating power, and is coupled to the second power supply VMID as a reference voltage. The driver stage sub-circuit 542 receives the second power supply VMID as an operation power supply, and is coupled to the reference ground GNDA to receive the reference ground voltage.

In this embodiment, corresponding to the transistor MD2, the second terminal of the switch SW524 receives the voltage VPW, and corresponding to the transistor MD3, the first terminal of the switch SW527 receives the voltage VNW. In summary, the novel creation provides a feedback output stage circuit to maintain the feedback output signal of the pre-stage operational amplifier during the pre-driving time interval. Such as In this way, the pre-stage operational amplifier can pre-charge the pre-amplification signal to be generated during the pre-driving time interval. When entering the driving time interval, it can accelerate the generation of a stable drive output signal and effectively improve the display. quality.

Although the new creation has been disclosed as above with examples, it is not intended to limit the creation of the new creation. Anyone with ordinary knowledge in the technical field of the subject can make some changes and without departing from the spirit and scope of the new creation. Retouch, so the scope of protection of this new creation shall be subject to the scope defined in the appended patent application.

Claims (14)

A driving circuit includes: a pre-stage operational amplifier with a first input terminal and a second input terminal to receive an input signal and a feedback output signal, respectively, including: a gain stage circuit with an output terminal to generate a pre-stage Amplified signal; a feedback output stage circuit, coupled to the gain stage circuit, generates the feedback output signal according to the previous stage amplified signal; a switching circuit, coupled to the previous stage operational amplifier, according to a mode selection signal to turn on or Disconnect a signal transmission channel; and a driver stage circuit, coupled to the switch circuit, and receive the pre-amplified signal through the signal transmission channel, and generate a drive output signal according to the pre-amplified signal. The driving circuit as claimed in item 1 of the patent application, wherein the switching circuit disconnects the signal transmission channel according to the mode selection signal during a pre-driving time interval, and the switching circuit according to the mode selection signal during a driving time interval Turn on the signal transmission channel. The driving circuit as described in item 1 of the patent application scope further includes: a first switch coupled to the path of the feedback output stage circuit to generate the feedback output signal, and turned on or off according to the mode selection signal . The driving circuit as described in Item 3 of the patent application scope further includes: a second switch and a third switch, coupled to the path of the gain stage circuit generating the pre-amplified signal, and conducting according to the mode selection signal Or disconnect. The driving circuit according to item 1 of the patent application scope, wherein the switch circuit includes: a first switch that receives a first pre-amplification signal from the pre-amplification signal, is controlled by the mode selection signal, and Transmitting the first pre-amplification signal to the driver stage circuit when the first switch is turned on; and a second switch receiving a second pre-amplification signal in the pre-amplification signal, controlled by the mode Select the signal and transmit the second pre-amplification signal to the driver stage circuit when the second switch is turned on, wherein the on and off states of the first switch and the second switch are the same. The driving circuit as described in item 5 of the patent application scope, wherein the switch circuit further comprises: a third switch, coupled to the output end of the driver stage circuit and the second input end of the pre-stage operational amplifier, the feedback output Between the output terminals of the stage circuit, it is turned on or off according to the mode selection signal, wherein the on and off states of the third switch and the first switch are the same. The driving circuit as described in item 6 of the patent application scope, wherein the switch circuit further comprises: a fourth switch, coupled between the first input terminal of the driver stage circuit and a power supply terminal, and conducting according to the mode selection signal Or off; and a fifth switch, coupled between the second input terminal of the driver stage circuit and a reference ground terminal, according to the mode selection signal to turn on or off, wherein the fourth switch and the fifth The on-off states of the switches are the same, the fourth switch is opposite the on-off state of the first switch, and the fifth switch is opposite the on-off state of the second switch. The driving circuit as described in item 5 of the patent application scope, wherein the feedback output stage circuit includes: a first transistor, a first end of which is coupled to a power supply end, and a second end of which generates the feedback output signal, The control terminal receives the first preamplification signal; and a second transistor, the first terminal of the second transistor generates the feedback output signal, and the second terminal of the second transistor is coupled to a reference The ground terminal, the control terminal of which receives the second preamplification signal. The driving circuit as described in item 1 of the patent application scope, wherein the feedback output stage circuit includes: a first feedback output stage sub-circuit, coupled to the gain stage circuit, and generating a first return based on the previous stage amplified signal The output signal of the teaching sub; and a second feedback output stage sub-circuit, coupled to the gain stage circuit, and generating a second feedback sub output signal according to the previous stage amplified signal, wherein the feedback output stage circuit provides the first One of the feedback sub-output signal and the second feedback sub-output signal is used as the feedback output signal. The driving circuit as described in item 9 of the patent application scope, wherein the feedback output stage circuit further comprises: a voltage selector coupled to the gain stage circuit and the first feedback output stage sub-circuit, the second feedback Between the sub-circuits of the teaching output stage, the amplified signal of the previous stage is provided to the first sub-circuit of the feedback output stage or the second sub-circuit of the feedback output stage. The driving circuit as described in item 10 of the patent application range, wherein the driving stage circuit includes: a first driving stage sub-circuit, coupled to the voltage selector, to generate a first polarity of the driving according to the previous stage amplified signal Output signal; a second driving stage sub-circuit, coupled to the voltage selector, generates a driving output signal of a second polarity according to the previous stage amplified signal, wherein the first polarity is complementary to the second polarity. The driving circuit as described in item 11 of the patent application range, wherein the first driving stage sub-circuit receives a first power source as an operating power source, receives a second power source as a reference power source, and the second driving stage sub-circuit receives the second The power supply is an operation power supply, and a third power supply is received as a reference ground power supply, wherein the first power supply is greater than the second power supply, and the second power supply is greater than the third power supply. The driving circuit according to item 9 of the patent application scope, wherein the gain stage circuit includes: at least one first differential pair, receiving the input signal and the feedback output signal; at least one second differential pair, and the at least one A first differential pair is complementary in form and receives the input signal and the feedback output signal; a first current source coupled to the at least one first differential pair; a second current source coupled to the at least one A second differential pair; a first active load, coupled to the at least one first differential pair; a second active load, coupled to the at least one second differential pair, and the first active load Complementary forms; a first impedance provider, coupled between the first active load and the second active load; a second impedance provider, coupled between the first active load and the second active load; and A third impedance provider is coupled between the first active load and the second active load, wherein the second impedance provider or the third impedance provider generates the pre-amplified signal. The driving circuit according to item 9 of the patent application scope, wherein the gain stage circuit includes: at least one first differential pair, receiving the input signal and the feedback output signal; at least one second differential pair, and the at least one A first differential pair is complementary in form and receives the input signal and the feedback output signal; a first current source coupled to the at least one first differential pair; a second current source coupled to the at least one A second differential pair; a first active load, coupled to the at least one first differential pair; a second active load, coupled to the at least one second differential pair, and the first active load Complementary form; a first impedance provider, coupled between the first active load and the second active load; and a second impedance provider, coupled between the first active load and the second active load, It is used to generate the pre-amplifier signal.