TWM528459U - Data storage systems and electronic device - Google Patents

Abstract

The present invention provides a data storage system, including a first storage unit and a storage module. The first storage unit stores a first lookup table. The storage module includes a second storage unit and a controller. The second storage unit stores a second lookup table and data corresponding to a storing instruction. An access speed of the second storage unit is lower than the access speed of the first storage unit. The controller receives the storing instruction and the data from a host, stores the data to the second storage unit according to logic block addresses in the storing instruction, and stores the logic block addresses to a first lookup table or a second lookup table. When size of the data and/or size of continuous data are less than a predetermined value, the logic black addresses are stored to the first lookup table. When the size of the data and/or the size of the continuous data are greater than the predetermined value, the logic black addresses are stored to the second lookup table.

Description

Data storage system and electronic device

The present invention relates to a data storage system and an electronic device, and more particularly to a data storage system and an electronic device for determining a storage location corresponding to a logical block address of a data according to the size of the data and the logical block address.

With the advancement of information technology, the frequency with which users use electronic devices in their daily lives has also increased. In order to pursue better processing efficiency, the demand for data access speed of electronic devices has also become higher and higher. In order to achieve the above objectives, in recent years, a Flash Translation Layer (FTL) technology has been used on a solid-state hard disk to speed up data access. However, in the flash memory conversion layer technology, the ratio of the storage capacity of the external dynamic random access memory to the storage capacity of the solid state hard disk is about 1:1000, but as the storage space of the solid state hard disk becomes more and more Large, the capacity requirements of dynamic random access memory are also increasing. Under the limitation of the process technology of the dynamic random access memory, the storage capacity of a single dynamic random access memory may not be sufficient to meet the demand of the solid state hard disk. Therefore, how to maintain the access speed of the storage device under the limitation of the storage capacity of the single dynamic random access memory is a problem to be solved currently.

To solve the above problem, an embodiment of the present invention provides a data storage system including a first storage unit and a storage module. The first storage unit is configured to store a first lookup table. The storage module includes a second storage unit and a controller. The second storage unit is configured to store a second lookup table and data corresponding to a storage instruction, wherein the access speed of the second storage unit is less than the access speed of the first storage unit. The controller is configured to receive the storage instruction and the data corresponding to the storage instruction from a host end, store the data to the second storage unit according to the logical block address in the storage instruction, and store the logical block address corresponding to the data to The first lookup table and one of the second lookup tables, wherein the store instruction further includes a size of the data. When the sum of the size of the data and/or the size of the continuous data is less than a predetermined value, the controller stores the logical block address to the first lookup table. When the sum of the size of the data and/or the size of the continuous data is greater than a predetermined value, the controller stores the logical block address to the second lookup table.

Another embodiment of the present invention provides an electronic device including a processor and a data storage system. The processor is configured to execute a plurality of function threads, and output a storage instruction and data corresponding to the storage instruction. The data storage system includes a first storage unit and a storage module. The first storage unit is configured to store a first lookup table. The storage module includes a second storage unit and a controller. The second storage unit is configured to store a second lookup table and data corresponding to a storage instruction. The access speed of the second storage unit is less than the access speed of the first storage unit. The controller is configured to receive the storage instruction from the processor and the data corresponding to the storage instruction, and store the data to the second according to the logical block address in the storage instruction The storage unit stores the logical block address corresponding to the data to one of the first lookup table and the second lookup table, wherein the storing instruction further includes the size of the data. When the sum of the size of the data and/or the size of the continuous data is less than a predetermined value, the controller stores the logical block address to the first lookup table. When the sum of the size of the data and/or the size of the continuous data is greater than a predetermined value, the controller stores the logical block address to the second lookup table.

100‧‧‧Data Storage System

110‧‧‧First storage unit

120‧‧‧ storage module

121‧‧‧ Controller

122‧‧‧Second storage unit

130‧‧‧ Busbars

200‧‧‧Electronic devices

210‧‧‧ processor

220‧‧‧ display unit

1 is a schematic diagram showing a data storage system according to an embodiment of the present invention; and FIG. 2 is a schematic diagram showing an electronic device according to an embodiment of the present invention.

Other ranges applicable to the system and method of this creation will be apparent from the detailed description provided below. It is to be understood that the following detailed description, as well as specific embodiments, are intended to be illustrative of the embodiments of the present invention, and are not intended to limit the scope of the present invention.

1 is a schematic diagram showing a data storage system according to an embodiment of the present invention. As shown in FIG. 1 , the data storage system 100 includes a first storage unit 110 and a storage module 120 . The first storage unit 110 is configured to store a first lookup table, and the first lookup table records a part of the logical area of the stored data. Block address. The storage module 120 further includes a controller 121 and a second storage unit 122. The controller 121 is configured to receive a storage instruction and a data corresponding to the storage instruction from the host terminal (not shown) through a bus bar 130, or receive the access instruction and output the data corresponding to the access instruction, and the first storage unit 110 Coupling. The second storage unit 122 can be divided into at least two parts, one part for storing a second lookup table and the other part for storing data corresponding to the storage instruction. The second lookup table is used to record the logical block address of another part of the stored data. The first storage unit 110 can be a memory external to the storage module 120, and the access speed is greater than the access speed of the second storage unit 122. For example, the first access unit 110 can be a dynamic random access memory, and the second storage unit 122 can be a NAND type flash memory.

According to an embodiment of the present invention, when the host side stores the data to the second storage unit 122, the storage instruction is transmitted to the controller 121 through the bus bar 130. The storage instruction includes at least the size of the data and the storage block of the data (ie, the logical block address). After receiving the storage instruction, the controller 121 stores the data in the corresponding data block according to the storage instruction, and stores the logical block address corresponding to the stored data to the first storage unit 110 according to the information in the storage instruction. Or in the second storage unit 122.

For example, in general, the size of the data that needs to be quickly accessed is usually less than 64 KB (kilobyte), so the controller 121 can determine whether the size of the data and/or the sum of the continuous data is smaller than after the storage instruction is received. 64KB to determine the storage location of the logical block address. When the sum of the size of the data or the size of the continuous data does not exceed 64 KB, the controller 121 stores the logical block address corresponding to the data to the first lookup table of the first access unit 110. The logical block address corresponding to the data can be quickly found from the first access unit 110 during access. On the other hand, when the sum of the size of the data and/or the size of the continuous data exceeds 64 KB (for example, 100 consecutive data of 4 KB in size), the controller 121 stores the logical block address corresponding to the data to the second access. The second lookup table of unit 122. It should be noted that the foregoing setting of the predetermined value is only one embodiment of the present invention, but is not limited thereto.

According to another embodiment of the present invention, when the controller 121 receives an access command from the host through the bus bar 130, the controller 121 first searches for the data corresponding to the access command in the first lookup table in the first storage unit 110. The logical block address. When the controller 121 searches for the logical block address corresponding to the data of the access instruction in the first lookup table, the corresponding data is read according to the logical block address to the second storage unit 122, and The read data is transmitted back to the host through the bus 130. On the other hand, when the controller 121 does not search for the logical block address corresponding to the data of the access instruction in the first lookup table, the controller 121 connects to the second lookup table in the second storage unit 122 to search for the corresponding storage. The logical block address of the data of the instruction is fetched, and the corresponding data is read according to the searched logical block address, and the read data is transmitted back to the host through the bus bar 130.

According to another embodiment of the present invention, when the host side wants to quickly access a specific data, a control command can be outputted to the controller 121 to specify an access location of the logical block address of the specific file. For example, the size of a specific data is greater than 64 KB. Therefore, when the specific data is stored, the controller 121 stores its corresponding logical block address in the second lookup table in the second storage unit 122. However, when the host side outputs a control command to the controller 121 to specify that the logical block address corresponding to the specific data must be stored in the first store When the first lookup table in the unit 110 is stored, the controller 121 first confirms to the first storage unit 110 whether the logical block address corresponding to the specific data is stored in the first lookup table, and if yes, continues to execute the subsequent instruction. If not, the logical block address corresponding to the specific data is moved to the first lookup table of the first storage unit 110 in the second lookup table of the controller 121 to the second storage unit 122.

According to another embodiment of the present invention, when the host side stores the data, the access location of the logical block address of the data may be directly specified according to the type of the stored data. For example, when the host side determines that the type of the stored data is video data or file file, etc., when the host side outputs the storage instruction, the host directly carries a control instruction to specify that the logical block address corresponding to the data is stored in the In the second lookup table of the second storage unit 122, the controller 121 directly stores the logical block address corresponding to the data to the second storage unit 122 after receiving the control command, that is, without performing the foregoing determining step. In the second lookup table.

2 is a schematic view showing an electronic device according to an embodiment of the present invention. The electronic device 200 includes a processor 210, a display unit 220, and a data storage system 100. The configuration of the data storage system 100 shown in FIG. 2 is the same as that of the data storage system 100 shown in FIG. 1, and will not be described here to simplify the description. The electronic device 200 can be a notebook computer, a desktop computer, or the like. The processor 210 is configured to execute a plurality of function threads and perform an action of accessing data according to a user operation. According to an embodiment of the present invention, when the user performs an access operation, the processor 210 outputs the storage instruction and the corresponding data or the read command to the data storage system 100 through the bus bar 130, and the data storage system 100 can also be used. The data corresponding to the read command is transmitted back to the processor 210 through the bus bar 130 through the bus bar 130. Display unit 220 Used to display the user interface corresponding to the function thread and accessing data.

In summary, according to the data storage system and the electronic device proposed in the embodiment of the present invention, when the controller of the storage device records the logical block address corresponding to the stored data, the data size of the stored data may be determined. The storage location of the logical block address. For a single data or continuous data with a large amount of data, searching for a logical block address in a storage unit with a slow access speed and searching for a logical block address in a storage unit with a faster access speed, The search time difference between the two is very small for the overall access time. Therefore, when the controller judges that the data size of the single data or the continuous data is larger than the predetermined value, the logical block corresponding to the data can be used. The address is recorded in the lookup table of the storage unit with slower access speed, thereby reducing the occupancy rate of the storage unit with faster access speed, and simultaneously reducing the large data to the storage unit with faster access speed. The loss can reduce the cost of the storage device and prolong the service life of the storage unit with faster access speed.

The features of many embodiments are described above to enable those of ordinary skill in the art to clearly understand the form of the specification. It will be appreciated by those of ordinary skill in the art that the present invention can be utilized to design or exemplify other processes and structures to achieve the same objectives and/or advantages over the above-described embodiments. Those skilled in the art can also understand that the equivalent constructions can be made without departing from the spirit and scope of the present invention.

100‧‧‧Data Storage System

110‧‧‧First storage unit

120‧‧‧ storage module

121‧‧‧ Controller

122‧‧‧Second storage unit

130‧‧‧ Busbars

Claims (10)

A data storage system includes: a first storage unit for storing a first lookup table; and a storage module, comprising: a second storage unit for storing a second lookup table and corresponding to a storage instruction The information that the access speed of the second storage unit is smaller than the access speed of the first storage unit; and a controller for receiving the storage instruction and the data corresponding to the storage instruction from a host end, And storing the foregoing data in the second storage unit according to the logical block address in the storage instruction, and storing the logical block address corresponding to the data to the first lookup table and one of the second lookup tables. The storage instruction further includes a size of the foregoing data; wherein, when the sum of the size of the data and/or the sum of the sizes of the consecutive data is less than a predetermined value, the controller stores the logical block address to the first a lookup table; and wherein, when the size of the above data and/or the sum of the sizes of the consecutive data is greater than the predetermined value, Said logic system will be saved to the second block address lookup table. The data storage system of claim 1, wherein when the controller receives a read command, determining whether the first lookup table has the logical block corresponding to the data of the read command. a location, when the first lookup table does not have the logical block address of the data, the controller searches the second lookup table for the foregoing corresponding to the read command The above logical block address of the data. The data storage system of claim 2, wherein the read command further comprises a predetermined logical block address for specifying the logical block address corresponding to the data of the read command. A default storage location. The data storage system of claim 3, wherein when the preset storage location is different from a current storage location of the data, the controller moves the logical block address after reading the data. To the above preset storage location. The data storage system of claim 1, wherein the first storage unit is a dynamic random access memory and the second storage unit is a NAND flash memory. An electronic device comprising: a processor for executing a plurality of function threads, and outputting a storage instruction and data corresponding to the storage instruction; and a data storage system comprising: a first storage unit for storing a first lookup table; and a storage module, comprising: a second storage unit, configured to store a second lookup table and data corresponding to a storage instruction, wherein the access speed of the second storage unit is less than An access speed of the first storage unit; and a controller for receiving the storage instruction and the data corresponding to the storage instruction from the processor, and storing the data according to the logical block address in the storage instruction The second storage unit, and the logical block address corresponding to the above data And storing, in the first lookup table, and the second lookup table, wherein the storing instruction further includes a size of the data; wherein, when the size of the data and/or the sum of consecutive data sizes is less than a predetermined value, The controller stores the logical block address to the first lookup table; and wherein, when the sum of the size of the data and/or the sum of the sizes of the data is greater than the predetermined value, the controller sets the logical block bit The address is stored in the second lookup table above. The electronic device of claim 6, wherein when the controller receives a read command from the processor, determining whether the first lookup table has the above-mentioned data corresponding to the read command a logic block address, when the first lookup table does not have the logical block address of the data, the controller searches the second lookup table for the logical region corresponding to the data of the read command Block address. The electronic device of claim 7, wherein the read command further comprises a predetermined logical block address for specifying one of the logical block addresses corresponding to the data of the read command. Preset storage location. The electronic device of claim 8, wherein when the preset storage location is different from a current storage location of the data, the controller moves the logical block address to after reading the data The above preset storage location. The electronic device of claim 6, wherein the first storage unit is a dynamic random access memory and the second storage unit is a NAND flash memory.