TWM255422U - Design of hybrid spacers for resisting high compression - Google Patents

Description

M255422 4. Creation Instructions (1) [Technical Field to which the New Type belongs] This creation is about the design of a high-pressure-resistance hybrid spacer for a liquid crystal display. [Previous technology] Liquid crystal displays have the advantages of light and thin appearance, low power consumption, and no radiation pollution, so they have been widely used in various electronic products, such as portable information such as notebook computers and personal digital assistants. Products and display screens for large automation equipment. A conventional liquid crystal display structure is composed of a filter substrate, a thin film transistor substrate, and liquid crystal filling a gap between the filter substrate and the thin film transistor substrate. The traditional liquid crystal filling method is to adhere the filter substrate to the surface of the thin-film transistor substrate, and then place the two substrates in a cavity, so that the liquid crystal is injected using the principle of capillary phenomenon. between. Because the traditional liquid crystal injection method is not only time consuming, but with the development of large-size liquid crystal displays, it is easy to produce uniformity and yield percentage problems in the process of filling liquid crystals. Therefore, a method called vacuum liquid crystal dropping (one drop fi 1 1 (ing, 0DF) technology has been highly developed to effectively solve the above and P problems, and to enable LCD displays to be used in large-sized TV markets. 0 D F technology uses a syringe or inkjet process to drop liquid crystals on the surface of a thin-film transistor substrate using air pressure, a servo motor, or other similar methods:

M255422 4. Creation instructions (2) The thin film transistor substrate and the filter substrate are then sent to a cavity to provide appropriate mechanical pressure and atmospheric pressure to press the two substrates together. Or, the gaps on the surface of the filter substrate leave a gap between the two substrates for liquid crystal molecules to exist, and the liquid crystal molecules are evenly distributed in the gap. In order to maintain a proper gap to accommodate the liquid crystal, plastic film (p 1 asticbead), glass beads or glass fibers are usually placed on the thin-film transistor substrate in a random spray manner. It may be located in the light penetrating area, or it may be unevenly distributed, causing aggregation to occur, which may cause the light to be scattered by plastic beads, reduce the light contrast intensity of the liquid crystal display, or may produce white spot defects. Seriously affect display quality and product yield. In order to avoid the above-mentioned problems that the plastic bead interstitials may cause, the photoresistive interstitials (Ph 〇t 〇spacer) formed by the lithography process are used to precisely control the size and position of the spacers and to maintain an appropriate gap size And other advantages, it has gradually replaced plastic bead spacers to maintain the gap between the filter substrate and the thin-film transistor substrate of the liquid crystal display, and improve the quality of the daytime surface. Please refer to FIG. 1. FIG. 1 is a schematic diagram of a conventional photoresistor spacer. As shown in Figure 1, the surface of a thin film transistor substrate 10 includes a plurality of perpendicularly intersecting scanning lines 12 and data lines 14 and a plurality of pictures defined by these scanning lines 1 2 and data lines 14. Prime regions 1 8 a, 1 8 b, 1 8 c, etc. In addition, the thin film transistor substrate 10 further includes a plurality of lines parallel to the scan.

M255422 IV. Creation instructions (3) The common electrode of line 1 2 spans the pixel area. For example, a common electrode 16 spans the day pixel area 18a, 18b, 18c, and the pixel area 18a, 18b. One of the daytime electrodes on the 18c surface (not shown) forms a storage capacitor. The conventional photoresistor gap 20 uses a lithography process to define the pattern and is set on the surface of a filter substrate (shown in Figure 2, number 30). In order to avoid affecting the aperture ratio of the liquid crystal display, every day element area Taking the pixel region 1 8 b as an example, at most only a single interstitial element 20 is corresponding to a region where the common electrode 16 and the data line 14 are stacked. κ Please refer to Figure 2. Figure 2 is a schematic cross-sectional view of a conventional LCD. As shown in FIG. 2, the liquid crystal display includes two parallel thin-film electrical φ crystal substrates 10, a filter substrate 30, and a liquid crystal 28 filled between the thin-film electrical crystal substrate 10 and the filter substrate 30. The surface of the thin-film transistor substrate 10 includes metal layers such as the common electrode 16 and the data line 14. A protective layer 24 covers the surface of the data line 14 and an alignment layer 26 covers the thin-film transistor substrate 10. surface. The surface of the filter substrate 30 includes a black matrix 32, a filter 34, and a gap 20 disposed above the area where the common electrode 16 and the data line 14 are stacked. The surface of the filter substrate 30 further includes an alignment layer 36 corresponding to the alignment layer 26. In the conventional spacer design, at most, a single spacer is provided only above the area where the common electrode and the data line are stacked, so that the thin film transistor substrate 10 and the filter substrate 30 are spaced apart. Can maintain the appropriate gap height for filling liquid crystal. Generally speaking, a single interstitial

P.10 M255422 IV. Creative Instructions (4)

It is relatively inadequate in performance, so the area of the spacer must be increased to improve its compression resistance, to avoid the spacer from cracking during the process of bonding two substrates using mechanical pressure and atmospheric pressure, which affects the product quality. With the increase in the area ratio of the interstitial force α, the relative space of the liquid crystal dripped on the thin film transistor substrate using the 0 D P technology will also decrease. Therefore, the process window of the liquid crystal will be insufficient, and the yield of the product will be reduced. In addition, another problem that may be brought about by increasing the area ratio of the spacers to improve the pressure resistance of the spacers is the influence of the display aperture ratio. As mentioned earlier, the gap element is set above the common electrode across the day element region, so the tolerance range of the alignment error between the two substrates will inevitably be sacrificed as the area ratio of the gap element increases. The gap is covered to a part of the pixel area, and the aperture ratio of the display is reduced. [New content] Therefore, the purpose of this creation is to provide a high pressure-resistant hybrid gap design that can provide good pressure resistance and support the gap between the two substrates of the liquid crystal display. Another purpose of this creation is to provide a high-resistance hybrid gap design, which can increase the process window for liquid crystal injection.

According to the purpose of this creation, the high-pressure-resistance hybrid spacer design includes a plurality of days defined by a plurality of perpendicularly intersecting scan lines and data lines.

Page 11 M255422 IV. Creative Instructions (5) In the prime region, at least one main gap element is set in one of the first region between one of the dioxin regions and its neighboring dioxin region, and at least one gap element is set in one of the diurnal regions. A second region between the pixel region and its adjacent day-light element region, and the height of the gap between the filter substrate and the thin film transistor substrate of the liquid crystal display in the first region The gap heights are different.

In addition to using the main gap to support the height of the gap between the filter substrate and the thin-film transistor substrate, this creation further uses the sub-spacer to provide an auxiliary support when the filter substrate is pressed to the thin-film transistor substrate. The area ratio of the sub-spacer can be appropriately increased without affecting the aperture ratio of the liquid crystal display, or an appropriate number of sub-spacers can be configured to improve the pressure resistance, avoiding the use of mechanical pressure and atmospheric pressure of the main spacer and sub-spacer Cracking occurs in the process of pressing two substrates, which affects product quality. On the other hand, the area ratio of the main gap can also be appropriately reduced to improve the problems of insufficient LCD process windows and lower LCD aperture ratio. [Embodiment]

Please refer to Figure 3, which is a schematic diagram of the setup of a photoresistor. As shown in FIG. 3, the surface of a thin-film transistor substrate 40 includes a plurality of perpendicularly intersecting scanning lines 4 2 and lean lines 4 4 ′, and a plurality of scanning lines 4 2 and data lines 4 4 defined by the scanning lines 4 2 and the data lines 4 4. The daytime prime areas 4 8 a, 4 8 b, 4 8 c, 50 a, 50 b, 50 c, etc. In the preferred embodiment of this creation, the day element

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Fourth, vuy

48b, 48c, to form a storage capacitor with one of the daylight electrodes (not shown) on the surface of the daylight region 48a, 48b, 48c. In the first embodiment and the 7th column of this creation, the 'common electrode 46 and the scanning line 4 2 are produced by the same process, that is, formed by the same metal layer. The photoresistor spacer set in this creation uses the lithography process on the surface of a filter substrate (shown in Figure 4, number 70) to define patterns such as the main spacer 5 2 and the sub-spacer 5 4 'in order to avoid affecting the liquid crystal The aperture ratio of the display, the main gap element 5 2 and the sub gap element 5 4 are arranged in the adjacent region (ie, the area indicated by the dashed line) between each day element region and its adjacent day element regions. For example, the main spacer 52 may be disposed over a region where the common electrode 46 and the data line 44 are stacked between the pixel region 48a and the day element region 4b, and the sub-spacer 54 may be disposed in the day element region Above scan line 42 between 48a and daytime region 50a. Since the surface of the thin film transistor substrate 40 corresponds to the surface of the main spacer 5 2 (including at least two metal layers such as the common electrode 46 and the data line 44), the surface of the thin film transistor substrate 40 corresponds to the surface of the secondary spacer 5 2 (only Including the scanning line 4 2 metal layer), the height of the gap between the filter substrate and the thin film transistor substrate 40 in the area where the main gap 5 2 and the sub gap 5 4 are set is different. In the preferred embodiment of this creation, the difference in height between different areas of the surface of the thin film transistor substrate 40 is used to form the filter substrate 70 and the thin film transistor substrate naturally.

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M255422_ IV. Creation instructions (7) There are different clearance heights between the 2nd and 4th sub-clearances and the 4th and 4th sub-clearances. However, the creation is not limited to this. In other embodiments, the height of the main gap 5 and the sub gap 5 4 can be further changed, or the height difference of different areas on the surface of the filter substrate 70 can be used to form the natural shape. The filter substrate 70 and the thin-film transistor substrate 40 have different gap heights at the main gaps 52 and at the sub-spacers 54. In other words, the main gap element 5 2 and the sub gap element 5 4 may have the same height or different heights. The surface height of the thin film transistor substrate 40 corresponding to the main gap element 5 2 may be aligned with the thin film transistor. The substrate 4 0 corresponds to the surface height corresponding to the sub-spacer 5 4, or the thin-film transistor substrate 40 corresponds to the surface height of the main gap 5 2 and the thin-film transistor substrate 40 corresponds to the sub-spacer 5 4 The surface heights of the filter substrates 70 are different from each other. In addition, the surface height of the filter substrate 70 at the position where the main gap 52 is provided and the surface height at which the sub-spacer 54 is provided may be the same or different. More precisely, this creation does not limit the installation positions of the main gap element 5 2 and the sub gap element 5 4, as long as it is adjacent to the area (opaque area) between different daylight elements, it can be used to set the The main gap 5 2 and the sub gap 5 4 make the height of the gap between the filter substrate 70 and the thin film transistor substrate 40 in the area where the main gap 5 2 and the sub gap 5 4 are set. Please refer to Figure 4, which is a schematic cross-sectional view of an LCD monitor. As shown in FIG. 4, the liquid crystal display includes two parallel thin film transistor substrates 40, a filter substrate 70, and a liquid crystal 62 filled between the thin film transistor substrate 40 and the filter substrate 70. Thin film transistor substrate 40 * Bread contains common electrode 46 formed by the first metal layer, scan green 4 7 u

Page 14 M255422_ IV. Creation instructions (8) The data lines 44 formed by the metal layer are stacked over the common electrode 46, and a protective layer 5 8 and an alignment layer 60 cover the surface of the thin film transistor substrate 40, respectively. Structures (not shown in the figure) between the first metal layer forming the common electrode 46 and the second metal layer forming the data line 44 may include an insulation layer and a semiconductor layer (not shown), depending on the product design. The surface of the filter substrate 70 includes a black matrix 72, a filter 74, a main gap 52 disposed above the area where the common electrode 46, the data lines 4 and 4 are stacked, and a pair of gaps 54 disposed on the scan. Line 4 2 above. The surface of the filter substrate 70 further includes an alignment layer 76 corresponding to the alignment layer 60. In the preferred embodiment of the present invention, the gap height difference between the thin film transistor substrate 40 and the filter substrate 70 at the main gap 5 2 and the sub gap 5 4 includes at least the data line 4 4 and The thickness of a semiconductor layer, the gap height difference is approximately between 0 · 5-0 · 6 microns (m), and the ratio of the set density of the main and sub-spacers is about 1: 20. Compared with the conventional photoresistor spacer design, in addition to using the main spacer 5 2 to support the gap height between the filter substrate 70 and the thin-film transistor substrate 40, this creation is further provided by the sub-spacer 54. The filter substrate 70 is pressed to the thin film transistor substrate 40 to assist the support, so the area ratio of the sub-spacer 54 can be appropriately increased or configured with an appropriate number without affecting the aperture ratio of the liquid crystal display. The sub-spacer 54 is used to improve the compression resistance and avoid the main gap and the sub-spacer from cracking during the pressing process of the two substrates using mechanical pressure and atmospheric pressure, which affects the product quality. On the other hand, the area ratio of the main spacer 52 can also be appropriately reduced to improve the problems of insufficient liquid crystal process windows and reduced aperture ratio of the liquid crystal display.

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Claims (1)

M255422_ 5. Scope of patent application 1. A high-pressure-resistant hybrid spacer design for a liquid crystal display. The liquid-crystal display includes two parallel opposite filter substrates and a thin-film transistor substrate. The high-pressure-resistant hybrid spacer design includes There are: a plurality of daylight regions defined by a plurality of vertically intersecting scan lines and data lines, at least one main gap is disposed in a first region between one of the daylight regions and a pixel region adjacent thereto; and at least A pair of spacers is disposed in a second region between one of the pixel region and the adjacent daylight region, and the height of the gap between the filter substrate and the thin film transistor substrate in the first region is related to the filter. The gap height between the substrate and the thin film transistor substrate in the second region is different. 2. The high-pressure-resistance hybrid spacer design according to item 1 of the application, wherein the main spacer and the sub-spacer are arranged on the filter substrate. 3. For the design of a high-pressure-resistance hybrid spacer in the second patent application range, wherein the primary spacer and the secondary spacer have the same height. 4. For example, the design of the high-pressure-resistance mixed-spacer in the scope of the patent application, wherein the main spacer and the sub-spacer have different heights. 5. For example, the high pressure-resistant hybrid gap design of the first patent application range, wherein the surface of the thin film transistor substrate is aligned with the thin surface on the first region. Page 18 M255422 5. Scope of patent application The film transistor substrate is on the surface of the second area. 6. For example, the design of the high-pressure-resistance hybrid spacer of the scope of the patent application, wherein the surface of the thin film transistor substrate in the first region is south of the surface of the thin film transistor substrate in the second region. 7. For example, the high-pressure-resistance hybrid spacer design of the first patent application range, wherein the surface of the filter substrate on the first region is aligned with the surface of the filter substrate on the second region. 8. For example, the high-pressure-resistance hybrid gap design of the first patent application range, wherein the surface of the filter substrate on the first region and the surface of the filter substrate on the second region have different heights. 9. For example, the high-resistance hybrid gap design of the first patent application range, wherein the thin film transistor substrate includes at least two metal layers in the first region, and the thin film transistor substrate includes in the second region. At least one metal layer 〇10. For example, the high pressure-resistant hybrid gap design of item 1 of the patent application scope, It further includes a plurality of common electrodes parallel to each of the scanning lines spanning each of the daylight regions. 11. Such as the design of the high pressure-resistant mixed gap spacer in the scope of patent application, Page 19 M255422 5. Scope of patent application Where the first area includes the area where each of the data lines and each of the common electrodes are stacked. 12. For example, the high-pressure-resistance hybrid gap design of item 1 of the patent application range, wherein the second area includes a setting area for each of the scan lines. 13. A high-resistance hybrid spacer design for a liquid crystal display, the liquid crystal display comprising two parallel opposite first substrates and a second substrate, the high-resistance hybrid spacer design including at least one main spacer and one The sub-spacer is disposed on the surface of the first substrate, and the surface of the second substrate corresponding to the main spacer and the surface of the second substrate corresponding to the sub-spacer have different heights. 14. For example, the high-pressure-resistant hybrid gapper design of item 13 in the patent application range, wherein the main gapper and the subspacer are disposed in an adjacent region between a daylight region and a nearby daylight region. 15. For example, the design of the high-pressure-resistance hybrid spacer of item 13 in the scope of the patent application, wherein the second substrate is an I-film transistor substrate, and the second substrate corresponds to the surface of the main spacer. At least two metal layers. 16. If you apply for special.阗. The design of the high-pressure-resistant hybrid spacer of the item, wherein the second and second plates are thin-film transistor substrates, and the surface of the second substrate corresponding to the 4 spacers includes at least one metal layer. Page 20 M255422 5. The scope of the patent application, the plan of stacking the phase gap of the inter-electrode type, the blending of the first pressure and the resistance of high-quality materials, 13 in the application should be applied to Fan Lili The Lord deserves it. • Mid-field 7 and sub-gap of 11-port J-I1. Inter-regional areas are mixed and placed together to resist the high-line scan. Item No. 13 Yu Dingwei should be dedicated to Fan Lizi, please apply for the vice. If so, please set a sub-gap. Face type table zygote mixed gap pressure room resistance to high should be Xiang Qi 13 cuts of the series of surrounding surface table table liko special clearance please apply for the master as the 9 in the plan. Set the height of the sub-gap with the same type, mixed surface, pressure gauge, high-gap between the sub-item, Xiang Hai 30, 1 Gukou, and the surface of the model Fan Li, special clearance, please apply for the master, the middle > 0 Page 21