TWI878217B - Silicon wafer manufacturing method - Google Patents

Abstract

The present invention is a method for manufacturing a silicon wafer, which includes a dry etching step between a rough polishing step and a fine polishing step, wherein in the dry etching step, the silicon wafer after the rough polishing step is dry-etched at an etching rate of less than 0.3 μm/min. Thus, a method for manufacturing a silicon wafer is provided, which can suppress the increase of surface defects and improve flatness even when the polishing step is reduced.

Description

Silicon wafer manufacturing method

The present invention relates to a method for manufacturing a silicon wafer.

As semiconductor devices using silicon are miniaturized, the silicon wafers used as substrates are required to have both finer surface defects and a high degree of flatness. As shown in FIG. 5 , silicon wafers are generally produced by slicing a single crystal rod pulled by, for example, the Czochralski (CZ) method, grinding it with a grind, and then performing multi-stage polishing (see Patent Document 1).

The wafer polishing step is very important for suppressing surface defects and achieving flatness. For example, surface defects such as scratches may be produced during the polishing step, and these defects may have a depth of more than 1μm depending on the polishing conditions. Furthermore, it is known that flatness may be impaired by the uneven distribution of pressure applied to the wafer during polishing.

Generally speaking, the polishing of silicon wafers is performed in multiple stages. Here, multiple stages refer to the polishing steps using different polishing cloths and abrasive grains. Generally speaking, silicon wafers are processed through more than two stages of polishing steps, and as the number of stages increases, softer polishing cloths and finer abrasive grains are used. Furthermore, by performing multiple stages of polishing, the depth of defects introduced by the polishing step gradually becomes shallower.

In this multi-stage polishing step, as long as the inequality "the maximum depth of defects introduced in any polishing step < the total processing amount of the subsequent grinding step" is not satisfied, the defects introduced in any polishing step will remain. For example, assuming the case of two-stage polishing, if the maximum depth of defects introduced in the first stage is 100nm, the polishing processing amount of the second stage must be more than 100nm. Assuming the case of three-stage polishing, if the maximum depth of defects introduced in the first stage is 100nm and the maximum depth of defects introduced in the second stage is 10nm, the total processing amount of the second and third stages must be more than 100nm and the total processing amount of the third stage must be more than 10nm. Therefore, multi-stage polishing has a necessary condition for the processing amount to prevent the deterioration of LLS (Localized light scatters).

On the other hand, if the polishing step is considered from the perspective of flatness, the fewer the number of polishing steps, the better. This is because, in each polishing step, the distribution of the processing amount in the radial direction will have extremely large and extremely small points, which is related to the deterioration of SFQR (Sight Front Least Squares Range), for example. Depending on the polishing conditions, the positions of the extremely large and extremely small points are different, so the more polishing steps there are, the more extremely large and extremely small points will appear in the radial direction, which will affect the flatness. [Prior technical literature] [Patent literature]

[Patent Document 1] Japanese Patent Application Publication No. 2008-205147

[Problem to be solved by the invention] In order to improve the flatness, it is expected to reduce the number of polishing steps, but reducing the number of polishing steps will result in insufficient processing, and the defects generated in the pre-polishing step will remain even after the final polishing step, resulting in an increase in surface defects (LLS defects).

The present invention is to solve the above-mentioned problem and aims to provide a method for manufacturing silicon wafers that can suppress the increase of surface defects and improve flatness even when reducing the polishing step. [Technical means for solving the problem]

In order to achieve the above-mentioned problem, the present invention provides a method for manufacturing a silicon wafer, which includes a dry etching step between a rough polishing step and a fine polishing step, wherein in the dry etching step, the silicon wafer after the rough polishing step is dry-etched at an etching rate of less than 0.3 μm/min.

With such a method for manufacturing a silicon wafer, the increase in surface defects can be suppressed and the flatness can be improved even when the polishing step is reduced.

Furthermore, the rough polishing step before the dry etching step is preferably a double-sided polishing step.

Furthermore, the fine polishing step after the dry etching step is preferably a single-side polishing step.

Furthermore, in the rough polishing step, it is preferred to use a polishing cloth with a higher hardness than the polishing cloth used in the fine polishing step.

By manufacturing silicon wafers under the above conditions, the increase of surface defects can be further suppressed and the flatness can be improved. [Compared with the effects of previous technologies]

As described above, the method for manufacturing a silicon wafer of the present invention can suppress the increase of surface defects and improve flatness even when the polishing step is reduced.

As described above, there is a need to develop a method for manufacturing a silicon wafer that can suppress the increase in surface defects and improve flatness even when reducing the number of polishing steps.

In order to reduce the number of polishing steps without increasing the number of surface defects, it is necessary to not perform polishing and remove the defects generated in the previous step. Therefore, the inventors of the present invention focused on replacing any polishing step other than the first rough polishing step and the final fine polishing step in the multi-stage polishing of silicon wafers with etching, especially dry etching.

However, if the dry etching rate is too fast, the plasma damage to the surface will increase, the ion damage will be introduced deep, and the micro-roughness will deteriorate, resulting in a large amount of subsequent polishing. Therefore, the inventors of the present invention have repeatedly studied and found that if the etching rate is within a specified range, even if the polishing step is reduced, the increase of surface defects can be suppressed and the roughness can be improved, and the present invention has been completed.

That is, the present invention is a method for manufacturing a silicon wafer, which includes a dry etching step between a rough polishing step and a fine polishing step, wherein in the dry etching step, the silicon wafer after the rough polishing step is dry etched at an etching rate of less than 0.3 μm/min.

The present invention is described in detail below, but the present invention is not limited to these.

[Silicon wafer manufacturing method] The silicon wafer manufacturing method of the present invention is described with reference to the drawings. FIG. 1 is a flow chart showing an example of the silicon wafer manufacturing method of the present invention. After the single crystal rod pulled by, for example, the Czochralski (CZ) method is sliced, it is polished and wheel-grinded, and then the rough polishing step, dry etching step and fine polishing step described below are passed to manufacture a silicon wafer. The crystal pulling step, slicing step, polishing and wheel-grinding step are not particularly limited, and the conventionally known methods can be used.

<Rough polishing step> Due to the fact that dry etching has no ability to improve roughness, in the present invention, a rough polishing step is provided before the dry etching step to improve the roughness, especially at long wavelengths.

After the grinding step, the wafer is subjected to a rough polishing step to mirror the front and back surfaces. The mirroring of the front and back surfaces can be performed by double-sided polishing once or several times, or by single-sided polishing once or several times. From the perspective of productivity, double-sided polishing (polishing both sides simultaneously) is preferred. If this polishing is not performed, the long-wavelength roughness will deteriorate.

This rough polishing step and the fine polishing step described below can be performed according to a known polishing method using a resin pad and a polishing slurry containing abrasive grains. The polishing agent can be a material containing silica gel as abrasive grains and an alkali.

<Dry etching step> Next, in order to prevent the roughness from deteriorating and to remove defects generated in the double-sided polishing step (rough polishing step), the wafer after the rough polishing step is cleaned and dried, and then dry etching is performed. The cleaning and drying methods are not particularly limited, and they can be performed by conventional methods.

Etching includes two types: wet etching using acid and alkali and dry etching using plasma gas. However, wet etching has a large selectivity and may enlarge defects. On the other hand, dry etching has a strong isotropic property and is suitable for evenly removing the surface without enlarging defects. Therefore, dry etching is used in the present invention.

The amount of work that should be removed by secondary polishing (second stage rough polishing) is removed by dry etching, thereby removing the defects generated in the previous step (rough polishing step). Dry etching is a processing method without contact of abrasive grains and pads with the wafer surface, so in principle, it will not generate defects deeper than 100nm.

The amount of dry etching processing depends on the defect depth caused by the conditions of the double-sided polishing step (rough polishing step), and removal of more than 0.5μm is sufficient. Dry etching uses plasma gas and is performed only on the surface of the wafer. From the perspective of flatness, it is better to supply plasma to the entire surface of the wafer and supply it evenly rather than just to a partial area on the surface of the wafer. The method of dry etching is not particularly limited. For example, _O2 gas and _CF4 gas can be supplied at flow rates of 100 and 500 sccm, respectively. Furthermore, the chamber pressure in dry etching can be 40 Pa, the output can be 500 W, and it can be performed at room temperature. In addition, the "normal temperature" in the present invention refers to the ambient temperature under normal conditions, which is usually in the range of 15 to 30°C, and typically 25°C.

In the dry etching step of the silicon wafer manufacturing method of the present invention, the etching rate must be below 0.3μm/min. When the etching rate is higher than 0.3μm/min, the plasma damage to the wafer surface will increase, the ion damage will be introduced to the deep, and the micro-roughness will deteriorate, resulting in a large amount of subsequent polishing processing. On the other hand, the etching rate is preferably above 0.1μm/min. If it is within this range, the etching of the silicon wafer can be carried out efficiently.

<Fine polishing step> Dry etching has no ability to remove micro-roughness, and although it is not like polishing, it will create shallow defects (micro defects) on the surface. Therefore, in order to remove micro-roughness and micro defects, polishing (fine polishing) is performed again in the end. The fine polishing step can be a single-sided polishing step. In this fine polishing step, it is better to use a resin pad and abrasive grains that are softer than the polishing step before dry etching. Here, the "hardness" in the present invention refers to the Shore A hardness.

According to the silicon wafer manufacturing method of the present invention as described above, even if the polishing step is omitted, the increase of LLS defects can be suppressed and the flatness can be improved.

[Examples] The present invention is specifically described below using examples and comparative examples, but the present invention is not limited to these.

[Examples 1 to 3, Comparative Examples 1 to 4] As shown in FIG. 2, a process (Comparative Example 1) is assumed in which a wafer (diameter: 300 mm) after a grinding step is subjected to three polishing steps (two rough polishing steps and one fine polishing step), and the effect of replacing the second rough polishing step with a dry etching step is verified.

The polishing amount is 5μm, 1μm, and 10nm in sequence. The process without the second rough polishing step is defined as Comparative Example 2, and the process replacing the second rough polishing step with dry etching and removing 1μm is defined as Comparative Examples 3, 4, and Examples 1 to 3. As shown in Table 1 below, the etching rates of Comparative Examples 3, 4, and Examples 1 to 3 are different. In addition, the rough polishing steps of the Examples and Comparative Examples are both performed by double-sided polishing, and the fine polishing steps are all performed by single-sided polishing.

Furthermore, in each polishing step, the polishing cloth is a resin-lined one, the polishing slurry is a silica gel with ammonia and a water-soluble high molecular polymer added thereto, and the rotation speed of the platen and the polishing head is 30 rpm.

The dry etching conditions other than the etching speed are as follows. Chamber pressure 40Pa Chamber temperature Normal temperature Output 500W _O2 gas flow rate 100sccm _CF4 gas flow rate 500sccm

【Table 1】

The flatness and defect evaluation of each silicon wafer after the fine polishing step was performed. As a flatness evaluation, the maximum value of SFQR, SFQRmax, was measured using WaferSight manufactured by KLA Tencor, and as a defect evaluation, the number of LLS defects was measured using SP3 manufactured by KLA Tencor. Furthermore, the processing amount shape in the rough polishing step 2 of Example 1 and the dry etching step of Example 1 was compared and evaluated using WaferSight manufactured by KLA Tencor.

The results of SFQRmax and the number of LLS defects of Examples 1 to 3 and Comparative Examples 1 to 4 are shown in Figure 3. In addition, SFQRmax and the number of LLS defects are relatively expressed with the comparative example of the general method being fixed at 100. In Comparative Example 2, SFQRmax is improved. This is considered to be due to the elimination of the deterioration in the rough polishing step 2. On the other hand, the LLS defects are significantly deteriorated compared to Comparative Example 1. This is considered to be because the defects caused in the rough polishing step 1 cannot be eliminated only by the processing amount of the fine polishing step 3. In Comparative Examples 3 and 4, despite the use of dry etching and sufficient etching, the LLS defects still increase. This is considered to be caused by plasma damage caused by the high etching rate. On the other hand, in Examples 1 to 3 where the etching rate is suppressed to below 0.3 μm/min, no increase in LLS defects is observed, and SFQRmax is also good due to the reduction in the polishing step.

Furthermore, as shown in FIG. 4 , the processed shape in the rough polishing step 2 of the comparison example 1 is unstable, and the flatness is lost in this step. In contrast, in the dry etching step of the embodiment 1, the processed shape is flat, indicating that the deterioration of the flatness remains at a minimum.

In addition, the present invention is not limited to the above-mentioned embodiments. The above-mentioned embodiments are for illustration only, and any object having substantially the same structure as the technical idea described in the scope of the patent application of the present invention and producing the same effect is included in the technical scope of the present invention.

without

[Figure 1] is a flowchart showing an example of a method for manufacturing a silicon wafer of the present invention. [Figure 2] is a flowchart for explaining an embodiment and a comparative example. [Figure 3] is a diagram for comparing the flatness and surface defects of silicon wafers of the embodiment and the comparative example. [Figure 4] is a diagram showing the shape of the processing amount in the rough polishing step 2 of the comparative example 1 and the dry etching step of the embodiment 1. [Figure 5] is a flowchart showing an example of a conventional method for manufacturing a silicon wafer.

Claims (5)

A method for manufacturing a silicon wafer includes a dry etching step between a rough polishing step and a fine polishing step, wherein in the dry etching step, plasma is evenly supplied to the entire surface of the wafer at an etching rate of 0.1 μm/min to 0.3 μm/min to perform dry etching on the silicon wafer after the rough polishing step. The method for manufacturing a silicon wafer as described in claim 1, wherein the rough polishing step before the dry etching step is a double-sided polishing step. The method for manufacturing a silicon wafer as described in claim 1, wherein the fine polishing step after the dry etching step is a single-sided polishing step. The method for manufacturing a silicon wafer as described in claim 2, wherein the fine polishing step after the dry etching step is a single-sided polishing step. A method for manufacturing a silicon wafer as described in any one of claims 1 to 4, wherein in the rough polishing step, a polishing cloth having a higher hardness than that used in the fine polishing step is used.