TWI877798B - Memory device and operating method thereof - Google Patents

Abstract

A memory device includes a first memory cell performing a logic operation according to a first weight bit and a first input bit. The first memory cell includes first and second switches. The first switch writes the first weight bit into a first storage node. The second switch generates a first current signal according to the first weight bit and the first input bit. The second switch receives a first bit line signal carrying the first input bit and a first word line signal. A control terminal of the second switch is coupled to the first storage node. When the first input bit has a first logic value, the first bit line signal and the first word line signal has a first voltage level. When the first input bit has a second logic value, the first bit line signal has a second voltage level smaller than the first voltage level.

Description

Memory device and operating method thereof

The present disclosure relates to a memory technology, and more particularly to a memory device and a method for operating the memory device.

The memory device includes a plurality of memory cells for storing data bits. The memory cell can be implemented by a two-transistor architecture. The data bits are stored in a storage node where the two transistors are coupled to each other. During a read operation, the logical value of the data bit can be determined by a current signal flowing through the memory cell.

An embodiment of the present invention includes a memory device. The memory device includes a first memory unit. The first memory unit is used to perform a logic operation based on a first weight bit and a first input bit. The first memory unit includes a first switch and a second switch. The first switch is used to write the first weight bit into a first storage node. The second switch is used to generate a first current signal based on the first weight bit and the first input bit. The first end of the second switch is used to receive a first bit line signal carrying the first input bit. The second end of the second switch is used to receive a first word line signal. The control end of the second switch is coupled to the first storage node. When the first input bit has a first logic value, each of the first bit line signal and the first word line signal has a first voltage level. When the first input bit has a second logic value, the first bit line signal has a second voltage level less than the first voltage level and the first word line signal has the first voltage level.

In some embodiments, when the first storage node has a third voltage level, the first current signal has a first current level, when the first storage node has a fourth voltage level and the first input bit has a first logic value, the first current signal has the first current level, and when the first storage node has a fourth voltage level and the first input bit has a second logic value, the first current signal has a second current level greater than the first current level.

In some embodiments, the logic operation is one of an AND logic operation, an OR logic operation, a NAND logic operation, and a NOR logic operation. When the logic operation is an AND logic operation or an OR logic operation, each of the fourth voltage level and the second current level corresponds to the second logic value, and when the logic operation is a NAND logic operation or a NOR logic operation, each of the fourth voltage level and the first current level corresponds to the second logic value.

In some embodiments, the memory device further includes a second memory unit. The second memory unit is used to store a second weight bit and receive a second bit line signal carrying a second input bit to perform a logic operation with the first memory unit. The second weight bit complements the first weight bit, and the second input bit complements the first input bit.

In some embodiments, the second memory unit includes a third switch and a fourth switch. The third switch is used to write the second weight bit into the second storage node. The fourth switch is used to generate a second current signal according to the second weight bit and the second input bit. The first end of the fourth switch is used to receive the second bit line signal, the second end of the fourth switch is used to receive the first word line signal, and a control end of the fourth switch is coupled to the second storage node.

In some embodiments, the memory device further includes a second memory unit, a first amplifier, a third memory unit, a fourth memory unit, and a second amplifier. The second memory unit is used to store a second weight bit and receive a second bit line signal carrying a second input bit to generate a second current signal. The first amplifier is coupled to the first node and is used to generate a first voltage signal according to the third current signal. The third memory unit is used to store a third weight bit and receive a first bit line signal to generate a fourth current signal. The fourth memory unit is used to store a fourth weight bit and receive a second bit line signal to generate a fifth current signal. The second amplifier is coupled to the second node and is used to generate a second voltage signal according to the sixth current signal. The second memory unit and the first memory unit are used to add the second current signal and the first current signal at the first node to generate a third current signal, and the third memory unit and the fourth memory unit are used to add the fourth current signal and the fifth current signal at the second node to generate a sixth current signal.

In some embodiments, the memory device further includes a second memory unit, a third memory unit, a fourth memory unit, and a first amplifier. The second memory unit is used to store a second weight bit and receive a second bit line signal carrying a second input bit to generate a second current signal. The third memory unit is used to store a third weight bit and receive a third bit line signal carrying a third input bit to generate a third current signal. The fourth memory unit is used to store a fourth weight bit and receive a fourth bit line signal carrying a fourth input bit to generate a fourth current signal. The first amplifier is used to receive a fifth current signal at the first node. The first memory unit, the second memory unit, the third memory unit and the fourth memory unit are used to add the first current signal, the second current signal, the third current signal and the fourth current signal at the first node to generate a fifth current signal, and the first weight bit, the second weight bit, the first input bit and the second input bit complement the third weight bit, the fourth weight bit, the third input bit and the fourth input bit respectively.

In some embodiments, the memory device further includes a second memory unit, a third memory unit, a fourth memory unit, a first amplifier, and a second amplifier. The second memory unit is used to store a second weight bit and receive a second bit line signal carrying a second input bit to generate a second current signal. The third memory unit is used to store a third weight bit and receive a third bit line signal carrying a third input bit to generate a third current signal. The fourth memory unit is used to store a fourth weight bit and receive a fourth bit line signal carrying a fourth input bit to generate a fourth current signal. The first amplifier is used to receive a fifth current signal at the first node. The second amplifier is used to receive a sixth current signal at the second node. The first memory unit and the second memory unit are used to add the first current signal and the second current signal at the first node to generate a fifth current signal, the third memory unit and the fourth memory unit are used to add the third current signal and the fourth current signal at the second node to generate a sixth current signal, and the first weight bit, the second weight bit, the first input bit and the second input bit complement the third weight bit, the fourth weight bit, the third input bit and the fourth input bit respectively.

An embodiment of the present invention includes an operating method of a memory device. The operation method includes: writing a first weight bit into a first storage node of a first memory unit; receiving a first bit line signal carrying a first input bit by the first memory unit; performing a logic operation according to the first input bit and the first weight bit to generate a first current signal passing through a first switch in the first memory unit; when the first storage node has a first voltage level, closing the first switch and the first current signal has a first current level; when the first storage node has a second voltage level and the first bit line signal has a third voltage level, turning on the first switch and the first current signal has a first current level; and when the first storage node has a second voltage level and the first bit line signal has a fourth voltage level, turning on the first switch and the first current signal has a second current level. The second current level is greater than the first current level, and the third voltage level is greater than the fourth voltage level.

In some embodiments, the operating method further includes: inverting the first input bit to generate a second input bit; inverting the first weight bit to generate a second weight bit; writing the second weight bit into a second storage node of a second memory unit; receiving a second bit line signal carrying the second input bit by the second memory unit; generating a second current signal through a second switch in the second memory unit based on the second input bit and the second weight bit; and adding the first current signal and the second current signal to generate a third current signal corresponding to the output of the logic operation.

In this article, when an element is referred to as "connected" or "coupled", it may refer to "electrically connected" or "electrically coupled". "Connected" or "coupled" may also be used to indicate that two or more elements cooperate with each other or interact with each other. In addition, although the terms "first", "second", etc. are used in this article to describe different elements, the terms are only used to distinguish between elements or operations described with the same technical terms. Unless the context clearly indicates otherwise, the terms do not specifically refer to or imply an order or sequence, nor are they used to limit the present case.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by ordinary technicians in the field to which this case belongs. It will be further understood that those terms as defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and this case, and will not be interpreted as an idealized or overly formal meaning unless expressly defined as such in this document.

The terms used herein are for the purpose of describing specific embodiments only and are not restrictive. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms, including "at least one". "Or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the relevant listed items. It should also be understood that when used in this specification, the terms "include" and/or "comprise" specify the presence and/or parts of the features, regions, wholes, steps, operations, elements, but do not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and/or their combinations.

The following will disclose multiple implementations of the present invention with drawings. For the purpose of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. In other words, in some implementations of the disclosed content, these practical details are not necessary. In addition, in order to simplify the drawings, some commonly used structures and components will be depicted in the drawings in a simple schematic manner.

FIG. 1 is a schematic diagram of a memory device 100 according to an embodiment of the present invention. As shown in FIG. 1 , the memory device 100 includes a memory unit 110. In some embodiments, the memory device 100 further includes a plurality of memory units (not shown) arranged in a plurality of rows and a plurality of columns.

In some embodiments, the memory cell 110 is used to receive word line signals WWL1, RWL1 and bit line signals WBL1, RBL1, and perform a logic operation according to a weight bit W11 carried by the bit line signal WBL1 and an input bit IPT1 carried by the bit line signal RBL1 to generate a current signal IS1. The weight bit W11 and the input bit IPT1 correspond to inputs of the logic operation, and the current level of the current signal IS1 corresponds to an output of the logic operation.

In some embodiments, different voltage levels of the bit line signal WBL1 correspond to different logical values of the weight bit W11, and different voltage levels of the bit line signal RBL11 correspond to different logical values of the input bit IPT1.

For example, when the bit line signal WBL1 has a voltage level VWL, the weight bit W11 has one of logical values 0 and 1, and when the bit line signal WBL1 has a voltage level VWH, the weight bit W11 has the other of logical values 0 and 1. Similarly, when the bit line signal RBL1 has a voltage level VL, the input bit IPT1 has one of logical values 0 and 1, and when the bit line signal RBL1 has a voltage level VH, the input bit IPT1 has the other of logical values 0 and 1. In some embodiments, the voltage level VWH is greater than the voltage level VWL, and the voltage level VH is greater than the voltage level VL.

As shown in FIG. 1 , the memory cell 110 includes switches T11 and T12. One end of the switch T11 is used to receive the bit line signal WBL1, the other end of the switch T11 is coupled to the storage node N11, and the control end of the switch T11 is used to receive the word line signal WWL1. One end of the switch T12 is used to receive the word line signal RWL1, the other end of the switch T12 is used to receive the bit line signal RBL1, and the control end of the switch T12 is coupled to the storage node N11.

In some embodiments, the switches T11 and T12 may be implemented by N-type metal oxide semiconductor (NMOS) transistors, floating gate (FG) transistors, silicon-oxide-nitride-oxide-silicon (SONOS) transistors, or indium gallium zinc oxide (IGZO) transistors.

In some embodiments, the memory cell 110 may further include a capacitor C11. One end of the capacitor C11 is coupled to the storage node N11, and the other end of the capacitor C11 is grounded. In various embodiments, the capacitor C11 may be implemented by one or more capacitors, or may be implemented by a parasitic capacitor of the storage node N11.

In operation, the memory unit 110 may perform a write operation to write the weight bit W11 into the storage node N11, and may perform a read operation after the write operation to generate a current signal IS1 flowing through the switch T12 according to the weight bit W11 and the input bit IPT1.

During the write operation, the word line signal WWL1 has an enable voltage level, which turns on the switch T11. At this time, the bit line signal WBL1 writes the weight bit W11 into the storage node N11 through the switch T11. When the write operation is completed, the capacitor C11 can store the voltage level corresponding to the weight bit W11.

During a read operation, the word line signal WWL1 has a disable voltage level, so that the switch T11 is closed. The switch T12 is turned on or off according to the voltage level of the storage node N11 (i.e., the logical value of the weight bit W11). When the storage node N11 has a voltage level VWL, the switch T12 is closed, so that the current signal IS1 has a current level ILL. In some embodiments, the current level ILL is approximately equal to zero. When the storage node N11 has a voltage level VWH, the switch T12 is turned on.

In addition, during the read operation, the word line signal RWL1 has a voltage level VH. Correspondingly, when the switch T12 is turned on and the bit line signal RBL1 has a voltage level VH, the voltage levels at both ends of the switch T12 are the same, so that the current signal IS1 has a current level ILL. When the switch T12 is turned on and the bit line signal RBL1 has a voltage level VL, the current signal IS1 has a current level ILH greater than the current level ILL. In some embodiments, the current signal IS1 having the current level ILL corresponds to one of the logical values 0 and 1, and the current signal IS1 having the current level ILH corresponds to the other of the logical values 0 and 1.

In some embodiments, the memory cell 110 is used to perform an AND logic operation. In the above embodiment, the voltage levels VWL and VWH of the bit line signal WBL1 correspond to logic values 0 and 1, respectively, the voltage levels VL and VH of the bit line signal RBL1 correspond to logic values 1 and 0, respectively, and the current levels ILL and ILH of the current signal IS1 correspond to logic values 0 and 1, respectively.

In some embodiments, the memory cell 110 is used to perform an OR logic operation. In the above embodiment, the voltage levels VWL and VWH of the bit line signal WBL1 correspond to logic values 1 and 0, respectively, the voltage levels VL and VH of the bit line signal RBL1 correspond to logic values 0 and 1, respectively, and the current levels ILL and ILH of the current signal IS1 correspond to logic values 1 and 0, respectively.

In some embodiments, the memory cell 110 is used to perform a NAND logic operation. In the above embodiment, the voltage levels VWL and VWH of the bit line signal WBL1 correspond to logic values 0 and 1, respectively, the voltage levels VL and VH of the bit line signal RBL1 correspond to logic values 1 and 0, respectively, and the current levels ILL and ILH of the current signal IS1 correspond to logic values 1 and 0, respectively.

In some embodiments, the memory cell 110 is used to perform a NOR logic operation. In the above embodiment, the voltage levels VWL and VWH of the bit line signal WBL1 correspond to logic values 1 and 0, respectively, the voltage levels VL and VH of the bit line signal RBL1 correspond to logic values 0 and 1, respectively, and the current levels ILL and ILH of the current signal IS1 correspond to logic values 0 and 1, respectively.

In some implementations, memory cells are used only to store data bits and are not used to perform logical operations.

Compared to the above, in the embodiment of the present disclosure, the memory unit 110 can use the input bit IPT1 and the weight bit W11 as the input of the logic operation and generate the current signal IS1 as the output of the logic operation. In this way, different logic operations such as AND, OR, NAND, and NOR can be performed by the memory unit 110.

FIG. 2 is a schematic diagram of a memory device 200 according to an embodiment of the present invention. Referring to FIG. 2 and FIG. 1, the memory device 200 is a variation of the memory device 100. Some components of the memory device 200 are numbered in the same manner as the memory device 100. For the sake of brevity, the discussion will focus on the differences between the memory device 200 and the memory device 100 rather than the similarities.

Compared to the memory device 100, the memory device 200 further includes a memory cell 210. The memory cell 210 is used to receive the word line signals WWL1, RWL1 and the bit line signals WBL2, RBL2, and perform a logic operation according to the weight bit WB11 carried by the bit line signal WBL2 and the input bit IPTB1 carried by the bit line signal RBL2 to generate a current signal IS2. The memory device 200 is further used to add the current signals IS2 and IS1 at the node N22 to generate a current signal IM2.

In some embodiments, weight bit WB11 and weight bit W11 complement each other, and input bit IPTB1 and input bit IPT1 complement each other. For example, when weight bit W11 has one of logical values 0 and 1, weight bit WB11 has the other of logical values 0 and 1. When input bit IPT1 has one of logical values 0 and 1, input bit IPTB1 has the other of logical values 0 and 1.

The relationship between the logic value of the weight bit WB11 and the input bit IPTB1 and the voltage level of the bit line signals WBL2 and RBL2 is similar to the relationship between the logic value of the weight bit W11 and the input bit IPT1 and the voltage level of the bit line signals WBL1 and RBL1, so for the sake of brevity, some descriptions will not be repeated.

In some embodiments, the memory device 200 further includes inverters NV21 and NV22. The inverter NV21 is used to receive the bit line signal RBL1 and output the bit line signal RBL2. The inverter NV22 is used to receive the bit line signal WBL1 and output the bit line signal WBL2. In other words, the inverter NV21 is used to invert the input bit IPT1 to generate the input bit IPTB1, and the inverter NV22 is used to invert the weight bit W11 to generate the weight bit WB11.

As shown in FIG. 2 , the memory cell 210 includes switches T21 and T22. One end of the switch T21 is used to receive the bit line signal WBL2, the other end of the switch T21 is coupled to the storage node N21, and the control end of the switch T21 is used to receive the word line signal WWL1. One end of the switch T22 is used to receive the word line signal RWL1, the other end of the switch T22 is used to receive the bit line signal RBL2, and the control end of the switch T22 is coupled to the storage node N21.

In some embodiments, the memory cell 210 may further include a capacitor C21. One end of the capacitor C21 is coupled to the storage node N21, and the other end of the capacitor C21 is grounded. In various embodiments, the capacitor C21 may be implemented by one or more capacitors, or may be implemented by a parasitic capacitor of the storage node N21.

In operation, the memory unit 210 may perform a write operation to write the weight bit WB11 into the node N21, and may perform a read operation after the write operation to generate a current signal IS2 flowing through the switch T22 according to the weight bit WB11 and the input bit IPTB1.

During the write operation, the word line signal WWL1 has an enabling voltage level, which turns on the switch T21. At this time, the bit line signal WBL2 writes the weight bit WB11 into the storage node N21 through the switch T21. When the write operation is completed, the capacitor C21 can store the voltage level corresponding to the weight bit WB11.

During the read operation, the word line signal WWL1 has a disable voltage level, so that the switch T21 is closed. The switch T22 is turned on or off according to the voltage level of the storage node N21. When the storage node N21 has a voltage level VWL, the switch T22 is closed, so that the current signal IS2 has a current level ILL. When the storage node N21 has a voltage level VWH, the switch T22 is turned on.

In addition, during the read operation, the word line signal RWL1 has a voltage level VH. Correspondingly, when the switch T22 is turned on and the bit line signal RBL2 has a voltage level VH, the voltage levels at both ends of the switch T22 are the same, so that the current signal IS2 has a current level ILL. When the switch T22 is turned on and the bit line signal RBL2 has a voltage level VL, the current signal IS2 has a current level ILH. In some embodiments, the current signal IS2 having the current level ILL corresponds to one of the logical values 0 and 1, and the current signal IS2 having the current level ILH corresponds to the other of the logical values 0 and 1.

Since the weight bits WB11 and W11 complement each other, and the input bits IPTB1 and IPT1 complement each other, the voltage levels of the bit line signals RBL2 and WBL2 are related to the voltage levels of the bit line signals RBL1 and WBL1.

For example, when the bit line signals RBL1 and WBL1 have voltage levels VL and VWH, respectively, the bit line signals RBL2 and WBL2 have voltage levels VH and VWL, respectively. Correspondingly, the current signals IS1 and IS2 have current levels ILH and ILL, respectively, so that the current signal IM2 has a current level ILH.

Similarly, when the bit line signals RBL1 and WBL1 have voltage levels VH and VWL, respectively, the bit line signals RBL2 and WBL2 have voltage levels VL and VWH, respectively. Correspondingly, the current signals IS1 and IS2 have current levels ILL and ILH, respectively, so that the current signal IM2 has a current level ILH.

Similarly, when the bit line signals RBL1 and WBL1 have voltage levels VL and VWL, respectively, the bit line signals RBL2 and WBL2 have voltage levels VH and VWH, respectively. Correspondingly, each of the current signals IS1 and IS2 has a current level ILL, so that the current signal IM2 has a current level ILL.

Similarly, when the bit line signals RBL1 and WBL1 have voltage levels VH and VWH, respectively, the bit line signals RBL2 and WBL2 have voltage levels VL and VWL, respectively. Correspondingly, each of the current signals IS1 and IS2 has a current level ILL, so that the current signal IM2 has a current level ILL.

In some embodiments, the memory cells 110 and 210 are used to perform logic operation together and use the current signal IM2 as the output of the logic operation. The current signal IM2 with the current level ILL corresponds to one of the logic values 0 and 1, and the current signal IM2 with the current level ILH corresponds to the other of the logic values 0 and 1.

In some embodiments, the memory device 200 is used to perform an exclusive OR (XOR) logic operation. In the above embodiment, the voltage levels VWL and VWH of the bit line signal WBL1 correspond to logic values 0 and 1, respectively, the voltage levels VL and VH of the bit line signal RBL1 correspond to logic values 1 and 0, respectively, and the current levels ILL and ILH of the current signal IM2 correspond to logic values 0 and 1, respectively.

In some embodiments, the memory device 200 is used to perform a non-exclusive OR (XNOR) logic operation. In the above embodiment, the voltage levels VWL and VWH of the bit line signal WBL1 correspond to logic values 0 and 1, respectively, the voltage levels VL and VH of the bit line signal RBL1 correspond to logic values 1 and 0, respectively, and the current levels ILL and ILH of the current signal IM2 correspond to logic values 1 and 0, respectively.

In some implementations, memory cells are used only to store data bits and are not used to perform logical operations.

Compared to the above method, in the embodiment of the present disclosure, the memory device 200 can use the input bit IPT1, the weight bit W11 and the complementary input bit IPTB1, the weight bit WB11 as the input of the logic operation, and generate the current signal IM2 as the output of the logic operation. In this way, different logic operations such as exclusive or non-exclusive or can be performed by the memory device 200.

FIG. 3 is a schematic diagram of a memory device 300 according to an embodiment of the present invention. Referring to FIG. 3 and FIG. 1, the memory device 300 is a variation of the memory device 100. Some components of the memory device 300 are labeled in the same manner as the memory device 100. For the sake of brevity, the discussion will focus on the differences between the memory device 300 and the memory device 100 rather than the similarities.

Compared to the memory device 100, the memory device 300 further includes a resistor R3. One end of the resistor R3 is used to receive the word line signal RWL1, and the other end of the resistor R3 is coupled to the switch T12 at the node N31. In other words, the switch T12 receives the word line signal RWL1 through the resistor R3.

In some embodiments, the resistor R3 is used to reduce the current signal IS1 to prevent the excessive current signal IS1 from causing abnormal circuit operation. In various embodiments, the resistance value of the resistor R3 is approximately in the range of 10 ⁵ to 10 ⁹ ohms, and the resistor R3 can be implemented by an oxide layer or a polysilicon resistor.

In some embodiments, the switch T12 has a critical voltage level VTH, and the voltage level VWH minus the voltage level VL is greater than the critical voltage level VTH. When the voltage level of the storage node N11 minus the voltage level of the bit line signal RBL1 is greater than the critical voltage level VTH, the current signal IS1 has a current level ILH. Conversely, when the voltage level of the storage node N11 minus the voltage level of the bit line signal RBL1 is less than the critical voltage level VTH, the current signal IS1 has a current level ILL.

Specifically, when the bit line signal RBL1 has a voltage level VL and the storage node N11 has a voltage level VWH, the current signal IS1 has a current level ILH. When the bit line signal RBL1 has a voltage level VH and the storage node N11 has a voltage level VWH, the current signal IS1 has a current level ILL. When the bit line signal RBL1 has a voltage level VH and the storage node N11 has a voltage level VWL, the current signal IS1 has a current level ILL. When the bit line signal RBL1 has a voltage level VL and the storage node N11 has a voltage level VWL, the current signal IS1 has a current level ILL.

In some embodiments, the voltage levels VL and VH of the bit line signal RBL1 correspond to the logic values 1 and 0 of the input bit IPT1, respectively, the voltage levels VWL and VWH of the storage node N11 correspond to the logic values 0 and 1 of the weight bit W11, respectively, and the current levels ILL and ILH of the current signal IS1 have logic values 0 and 1, respectively.

FIG. 4 is a schematic diagram of a memory device 400 according to an embodiment of the present invention. Referring to FIG. 4 and FIG. 3, the memory device 400 is a variation of the memory device 300. Some components of the memory device 400 are labeled in the same manner as the memory device 300. For the sake of brevity, the discussion will focus on the differences between the memory device 400 and the memory device 300 rather than the similarities.

Compared to the memory device 300, the memory device 400 further includes memory units 411-417 and amplifiers 451 and 452. In some embodiments, the memory units 110 and 411-413 are used to perform a first multiply and accumulate (MAC) logic operation to generate a current signal IM41 as an output of the first multiply and accumulate operation. The memory units 414-417 are used to perform a second multiply and accumulate operation to generate a current signal IM42 as an output of the second multiply and accumulate operation. The amplifier 451 is used to generate a voltage signal S41 according to the current signal IM41. The amplifier 452 is used to generate a voltage signal S42 according to the current signal IM42. In some embodiments, the amplifiers 451 and 452 may be implemented by sensing amplifiers (SA).

As shown in FIG. 4 , the memory cell 411 includes switches T41, T42 and a resistor R41. One end of the switch T41 is used to receive the bit line signal WBL2, the other end of the switch T41 is coupled to the storage node N41, and the control end of the switch T41 is used to receive the word line signal WWL1. One end of the switch T42 is coupled to the resistor R41, the other end of the switch T42 is used to receive the bit line signal RBL2, and the control end of the switch T42 is coupled to the storage node N41. One end of the resistor R41 is coupled to the switch T42, and the other end of the resistor R41 is used to receive the word line signal RWL1.

Similarly, the memory cell 412 includes switches T43, T44 and a resistor R42. One end of the switch T43 is used to receive the bit line signal WBL3, the other end of the switch T43 is coupled to the storage node N42, and the control end of the switch T43 is used to receive the word line signal WWL1. One end of the switch T44 is coupled to the resistor R42, the other end of the switch T44 is used to receive the bit line signal RBL3, and the control end of the switch T44 is coupled to the storage node N42. One end of the resistor R42 is coupled to the switch T44, and the other end of the resistor R42 is used to receive the word line signal RWL1.

Similarly, the memory cell 413 includes switches T45, T46 and a resistor R43. One end of the switch T45 is used to receive the bit line signal WBL4, the other end of the switch T45 is coupled to the storage node N43, and the control end of the switch T45 is used to receive the word line signal WWL1. One end of the switch T46 is coupled to the resistor R43, the other end of the switch T46 is used to receive the bit line signal RBL4, and the control end of the switch T46 is coupled to the storage node N43. One end of the resistor R43 is coupled to the switch T46, and the other end of the resistor R43 is used to receive the word line signal RWL1.

Similarly, the memory cell 414 includes switches T47, T48 and a resistor R44. One end of the switch T47 is used to receive the bit line signal WBL1, the other end of the switch T47 is coupled to the storage node N44, and the control end of the switch T47 is used to receive the word line signal WWL2. One end of the switch T48 is coupled to the resistor R44, the other end of the switch T48 is used to receive the bit line signal RBL1, and the control end of the switch T48 is coupled to the storage node N44. One end of the resistor R44 is coupled to the switch T48, and the other end of the resistor R44 is used to receive the word line signal RWL2.

Similarly, the memory cell 415 includes switches T49, T410 and a resistor R45. One end of the switch T49 is used to receive the bit line signal WBL2, the other end of the switch T49 is coupled to the storage node N45, and the control end of the switch T49 is used to receive the word line signal WWL2. One end of the switch T410 is coupled to the resistor R45, the other end of the switch T410 is used to receive the bit line signal RBL2, and the control end of the switch T410 is coupled to the storage node N45. One end of the resistor R45 is coupled to the switch T410, and the other end of the resistor R45 is used to receive the word line signal RWL2.

Similarly, the memory unit 416 includes switches T411, T412 and a resistor R46. One end of the switch T411 is used to receive the bit line signal WBL3, the other end of the switch T411 is coupled to the storage node N46, and the control end of the switch T411 is used to receive the word line signal WWL2. One end of the switch T412 is coupled to the resistor R46, the other end of the switch T412 is used to receive the bit line signal RBL3, and the control end of the switch T412 is coupled to the storage node N46. One end of the resistor R46 is coupled to the switch T412, and the other end of the resistor R46 is used to receive the word line signal RWL2.

Similarly, the memory unit 417 includes switches T413, T414 and a resistor R47. One end of the switch T413 is used to receive the bit line signal WBL4, the other end of the switch T413 is coupled to the storage node N47, and the control end of the switch T413 is used to receive the word line signal WWL2. One end of the switch T414 is coupled to the resistor R47, the other end of the switch T414 is used to receive the bit line signal RBL4, and the control end of the switch T414 is coupled to the storage node N47. One end of the resistor R47 is coupled to the switch T414, and the other end of the resistor R47 is used to receive the word line signal RWL2.

In some embodiments, the memory cells 411-417 further include capacitors C41-C47, respectively. The capacitors C41-C47 are coupled to nodes N41-N47, respectively. In some embodiments, the configuration of the capacitors C41-C47 is similar to the configuration of the capacitor C11, and the configuration of the resistors R41-R47 is similar to the configuration of the resistor R3. Therefore, for the sake of brevity, some descriptions are not repeated.

As shown in FIG. 4 , bit line signals RBL1 to RBL4 are used to carry input bits IPT1 to IPT4, respectively. Bit line signal WBL1 is used to carry weight bits W11 and W21. Bit line signal WBL2 is used to carry weight bits W12 and W22. Bit line signal WBL3 is used to carry weight bits W13 and W23. Bit line signal WBL4 is used to carry weight bits W14 and W24.

In some embodiments, the relationship between the logic values of the input bits IPT1-IPT4, the weight bits W11-W14, W21-W24, and the voltage levels of the bit line signals RBL1-RBL4, WBL1-WBL4 is similar to the relationship between the logic value of the input bit IPT1, the weight bit W11, and the voltage levels of the bit line signals RBL1, WBL1. Therefore, for the sake of brevity, some descriptions are not repeated.

In operation, the memory units 110 and 411-413 may perform a first write operation to write the weight bits W11-W14 into the storage nodes N11 and N41-N43, respectively. After the first write operation, the memory units 414-417 may perform a second write operation to write the weight bits W21-W24 into the storage nodes N44-N47, respectively.

During the first write operation, word line signals WWL1 and WWL2 have an enable voltage level and a disable voltage level, respectively, so that switches T11, T41, T43 and T45 are turned on, and switches T47, T49, T411 and T413 are turned off. At this time, bit line signals WBL1-WBL4 have weight bits W11-W14, respectively, so that storage nodes N11 and N41-N43 can write weight bits W11-W14. When the first write operation is completed, capacitors C11 and C41-C43 can store voltage levels corresponding to weight bits W11-W14.

During the second write operation, the word line signals WWL1 and WWL2 have a disable voltage level and an enable voltage level, respectively, so that the switches T11, T41, T43 and T45 are closed, and the switches T47, T49, T411 and T413 are turned on. At this time, the bit line signals WBL1-WBL4 have weight bits W21-W24, respectively, so that the storage nodes N44-N47 can write the weight bits W21-W24. When the second write operation is completed, the capacitors C11 and C44-C47 can store the voltage levels corresponding to the weight bits W21-W24.

In some embodiments, after the second write operation, the memory device 400 may perform more write operations to write other weight bits into other rows of memory cells (not shown). After the above write operation, the memory device 400 may perform a read operation to generate current signals IS1 and IS41-IS47 according to the weight bits W11-W14, W21-W24 and the input bits IPT1-IPT4. The current signals IS41-IS47 flow through switches T42, T44, T46, T48, T410, T412 and T414 respectively.

During the read operation, each of the word line signals WWL1 and WWL2 has a disable voltage level, so that the switches T11, T41, T43, T45, T47, T49, T411 and T413 are turned off. The switches T12, T42, T44, T46, T48, T410, T412 and T414 are turned on or off according to the voltage levels of the storage nodes N11 and N41-N47 (i.e., the logic values of the weight bits W11-W14 and W21-W24), respectively.

When one or more of the storage nodes N11 and N41-N47 have a voltage level VWL, a corresponding one or more of the switches T12, T42, T44, T46, T48, T410, T412 and T414 are turned off, so that the current signal IS1 and a corresponding one or more of IS41-IS47 have a current level ILL.

When one or more of the storage nodes N11 and N41-N47 have a voltage level VWH, a corresponding one or more of the switches T12, T42, T44, T46, T48, T410, T412 and T414 are turned on, so that the current signals IS1 and a corresponding one or more of IS41-IS47 have a current level corresponding to a corresponding one or more of the input bits IPT1-IPT4.

For example, input bits IPT1-IPT4 have logic values 1, 1, 0, 0, respectively, wherein logic values 1 and 0 correspond to voltage levels VL and VH, respectively. Weight bits W11-W14 and W21-W24 have logic values 1, 0, 1, 0, 0, 1, 0, 1, respectively, wherein logic values 1 and 0 correspond to voltage levels VWH and VWL, respectively.

In the above example, in response to the logic value 1 of the weight bits W11, W13, W22 and W24, the storage nodes N11, N42, N45 and N47 have a voltage level VWH, so that the switches T12, T44, T410 and T414 are turned on. At this time, in response to the logic value 1 of the input bits IPT1 and IPT2, the current signals IS1 and IS45 have a current level ILH. On the other hand, the current signals IS41~IS44 and IS46~IS47 have a current level ILL. At this time, the memory device 400 adds the current signals IS1 and IS41-IS43 at the node N48 to generate the current signal IM41 having the current level ILH, and adds the current signals IS44-IS47 at the node N49 to generate the current signal IM42 having the current level ILH, so that the amplifiers 451 and 452 generate the voltage signals S41 and S42 corresponding to the current level ILH.

For another example, input bits IPT1-IPT4 have logical values 1, 1, 1, 0, respectively. Weight bits W11-W14 and W21-W24 have logical values 1, 1, 0, 1, 0, 0, 0, 1, respectively.

In the above example, in response to the logic value 1 of the weight bits W11, W12, W14 and W24, the storage nodes N11, N41, N43 and N47 have a voltage level VWH, so that the switches T12, T42, T46 and T414 are turned on. At this time, in response to the logic value 1 of the input bits IPT1~IPT3, the current signals IS1 and IS41 have a current level ILH. On the other hand, the current signals IS42~IS47 have a current level ILL. At this time, the memory device 400 adds the current signals IS1 and IS41~IS43 at the node N48 to generate the current signal IM41 with the current level 2×ILH, and adds the current signals IS44~IS47 at the node N49 to generate the current signal IM42 with the current level ILL, so that the amplifier 451 generates the voltage signal S41 corresponding to the current level 2×ILH, and the amplifier 452 generates the voltage signal S42 corresponding to the current level ILL.

In some embodiments, the voltage level of the voltage signal S41 corresponds to the result of adding the products of the input bits IPT1-IPT4 multiplied by the weight bits W11-W14. For example, when IPT1×W11+IPT2×W12+IPT3×W13+IPT4×W14=1, the current signal IM41 has a current level ILH, so that the voltage signal S41 has a voltage level VL corresponding to the logical value 1. Similarly, the voltage level of the voltage signal S42 corresponds to the result of adding the products of the input bits IPT1-IPT4 multiplied by the weight bits W21-W24. For example, when IPT1×W21+IPT2×W22+IPT3×W23+IPT4×W24=0, the current signal IM42 has a current level ILL, so that the voltage signal S42 has a voltage level VH corresponding to a logical value of 0.

In summary, the memory device 400 multiplies the input bits IPT1-IPT4 by the weight bits W11-W14, and adds the currents IS1 and IS41-IS43 as products to generate the current signal IM41. The memory device 400 also multiplies the input bits IPT1-IPT4 by the weight bits W21-W24, and adds the currents IS44-IS47 as products to generate the current signal IM42. In this way, the memory device 400 can achieve the multiplication and accumulation logic operation of the input bits IPT1-IPT4 and the weight bits W11-W14, W21-W24.

FIG. 5 is a schematic diagram showing further details of a memory device 400 according to an embodiment of the present invention. Referring to FIG. 5 and FIG. 4, in some variations, the memory device 400 may further include memory cells 511 to 514 and amplifiers 551 and 552. The memory cells 511 and 512 are used to perform a third product-accumulation operation on the voltage signals S41 and S42 to generate a current signal IM51. The memory cells 513 and 514 are used to perform a fourth product-accumulation operation on the voltage signals S41 and S42 to generate a current signal IM52. The amplifier 551 is used to generate a voltage signal S51 according to the current signal IM51. The amplifier 552 is used to generate a voltage signal S52 according to the current signal IM52.

As shown in FIG. 5 , the memory cell 511 includes switches T51, T52 and a resistor R51. One end of the switch T51 is used to receive the bit line signal WBL51, the other end of the switch T51 is coupled to the storage node N51, and the control end of the switch T51 is used to receive the word line signal WWL51. One end of the switch T52 is coupled to the resistor R51, the other end of the switch T52 is used to receive the voltage signal S41, and the control end of the switch T52 is coupled to the storage node N51. One end of the resistor R51 is coupled to the switch T52, and the other end of the resistor R51 is used to receive the word line signal RWL51.

Similarly, the memory cell 512 includes switches T53, T54 and a resistor R52. One end of the switch T53 is used to receive the bit line signal WBL52, the other end of the switch T53 is coupled to the storage node N52, and the control end of the switch T53 is used to receive the word line signal WWL51. One end of the switch T54 is coupled to the resistor R52, the other end of the switch T54 is used to receive the voltage signal S42, and the control end of the switch T54 is coupled to the storage node N52. One end of the resistor R52 is coupled to the switch T54, and the other end of the resistor R52 is used to receive the word line signal RWL51.

Similarly, the memory cell 513 includes switches T55, T56 and a resistor R53. One end of the switch T55 is used to receive the bit line signal WBL51, the other end of the switch T55 is coupled to the storage node N53, and the control end of the switch T55 is used to receive the word line signal WWL52. One end of the switch T56 is coupled to the resistor R53, the other end of the switch T56 is used to receive the voltage signal S41, and the control end of the switch T56 is coupled to the storage node N53. One end of the resistor R53 is coupled to the switch T56, and the other end of the resistor R53 is used to receive the word line signal RWL52.

Similarly, the memory cell 514 includes switches T57, T58 and a resistor R54. One end of the switch T57 is used to receive the bit line signal WBL52, the other end of the switch T57 is coupled to the storage node N54, and the control end of the switch T57 is used to receive the word line signal WWL52. One end of the switch T58 is coupled to the resistor R54, the other end of the switch T58 is used to receive the voltage signal S42, and the control end of the switch T58 is coupled to the storage node N54. One end of the resistor R54 is coupled to the switch T58, and the other end of the resistor R54 is used to receive the word line signal RWL52.

In some embodiments, the memory cells 511-514 further include capacitors C51-C54, respectively. The capacitors C51-C54 are coupled to nodes N51-N54, respectively. In some embodiments, the configuration of the capacitors C51-C54 is similar to the configuration of the capacitor C11, and the configuration of the resistors R51-R54 is similar to the configuration of the resistor R3. Therefore, for the sake of brevity, some descriptions are not repeated.

In some embodiments, the bit line signal WBL51 is used to carry weight bits W51 and W53. The bit line signal WBL52 is used to carry weight bits W52 and W54. The memory units 511-514 can perform third and fourth multiplication and accumulation logic operations on the weight bits W51-W54 and the voltage signals S41 and S42 (i.e., the outputs of the first and second multiplication and accumulation logic operations) to generate current signals IM51 and IM52.

In operation, memory units 511 and 512 may perform a first write operation to write weight bits W51 and W52 into storage nodes N51 and N52, respectively. After the first write operation, memory units 513 and 514 may perform a second write operation to write weight bits W53 and W54 into nodes N53 and N54, respectively.

During the first write operation, word line signals WWL51 and WWL52 have an enable voltage level and a disable voltage level, respectively, so that switches T51 and T53 are turned on, and switches T52 and T54 are turned off. At this time, bit line signals WBL51 and WBL52 have weight bits W51 and W52, respectively, so that storage nodes N51 and N52 can write weight bits W51 and W52. When the first write operation is completed, capacitors C51 and C52 can store voltage levels corresponding to weight bits W51 and W52.

During the second write operation, word line signals WWL51 and WWL52 have a disable voltage level and an enable voltage level, respectively, so that switches T51 and T53 are closed, and switches T52 and T54 are turned on. At this time, bit line signals WBL51 and WBL52 have weight bits W53 and W54, respectively, so that storage nodes N53 and N54 can write weight bits W53 and W54. When the second write operation is completed, capacitors C53 and C54 can store voltage levels corresponding to weight bits W53 and W54.

After the second write operation, the memory device 400 can perform a read operation to generate current signals IS51-IS54 according to the weight bits W51-W54 and the voltage signals S41 and S42. The current signals IS51-IS54 flow through switches T52, T54, T56 and T58 respectively.

During the read operation, each of the word line signals WWL51 and WWL52 has a disable voltage level, so that switches T51, T53, T55 and T57 are closed. Switches T52, T54, T56 and T58 are turned on or off according to the voltage level of the storage nodes N51-N54 (i.e., the logical value of the weight bits W51-W54).

For example, when weight bits W51~W54 have logic values 1, 0, 0, 1 respectively, switches T52 and T58 are turned on in response to the logic value 1 of weight bits W51 and W54, and switches T54 and T56 are turned off in response to the logic value 0 of weight bits W52 and W53.

At this time, if the voltage signals S41 and S42 respectively have a voltage level VL corresponding to a logic value of 1 and a voltage level VH corresponding to a logic value of 0, the current signal IS51 has a current level ILH, and the current signals IS52-IS54 have a current level ILL. Correspondingly, the memory cells 511 and 512 add the current signals IS51 and IS52 at the node N55 to generate a current signal IM51 having a current level ILH, and the memory cells 513 and 514 add the current signals IS53 and IS54 at the node N56 to generate a current signal IM52 having a current level ILL.

In summary, the memory device 400 multiplies the logic values of the voltage signals S41 and S42 by the weight bits W51 and W52, respectively, and adds the currents IS51 and IS52 as the product to generate the current signal IM51. The memory device 400 also multiplies the logic values of the voltage signals S41 and S42 by the weight bits W53 and W54, respectively, and adds the currents IS53 and IS54 as the product to generate the current signal IM52. In this way, the memory device 400 can achieve the product accumulation logic operation of the voltage signals S41 and S42 and the weight bits W51~W54.

4 and 5 , after the memory units 110 and 411 - 417 perform the first and second product accumulation logic operations to generate voltage signals S41 and S42, the memory units 511 - 514 perform the third and fourth product accumulation logic operations on the voltage signals S41 and S42 to generate voltage signals S51 and S52.

In application, memory cells 110 and 411-417 may be included in the first layer of the convolutional layer of the neural network, and voltage signals S41 and S42 correspond to the output of the first layer. Memory cells 511-514 may be included in the second layer of the convolutional layer of the neural network, voltage signals S41 and S42 correspond to the input of the second layer, and voltage signals S51 and S52 correspond to the output of the second layer.

FIG. 6 is a schematic diagram of a memory device 600 according to an embodiment of the present invention. Referring to FIG. 6 and FIG. 4 , the memory device 600 is a variation of the memory device 400. Some components of the memory device 600 are labeled in the same manner as the memory device 400. For the sake of brevity, the discussion will focus on the differences between the memory device 600 and the memory device 400 rather than the similarities.

Compared to the embodiment shown in FIG. 4, in the embodiment shown in FIG. 6, bit line signals RBL3 and RBL4 are used to carry input bits IPTB1 and IPTB2, respectively, instead of input bits IPT3 and IPT4. Bit line signal WBL3 is used to carry weight bits WB11 and WB21, instead of weight bits W13 and W23. Bit line signal WBL4 is used to carry weight bits WB12 and WB22, instead of weight bits W14 and W24. The input bits IPTB1, IPTB2 and weight bits WB11, WB21, WB12, WB22 complement the input bits IPT1, IPT2 and weight bits W11, W21, W12, W22, respectively.

In some embodiments, the memory device 600 further includes inverters NV61 and NV62. The inverter NV61 is used to receive the bit line signal RBL1 and output the bit line signal RBL3. The inverter NV62 is used to receive the bit line signal RBL2 and output the bit line signal RBL4. In other words, the inverter NV61 is used to invert the input bit IPT1 to generate the input bit IPTB1, and the inverter NV62 is used to invert the input bit IPT2 to generate the input bit IPTB2.

In response to the bit line signal WBL3 carrying the weight bits WB11 and WB21 and the bit line signal WBL4 carrying the weight bits WB12 and WB22, the storage nodes N42, N43, N46 and N47 are used to store the voltage levels corresponding to the weight bits WB11, WB12, WB21 and WB22 respectively.

In operation, the memory device 600 can perform a search logic operation. Specifically, the memory device 600 is used to compare input bits and weight bits. When the similarity between the input bits and the weight bits increases, the current level of the current signal generated by the memory device 600 increases.

For example, when input bits IPT1 and IPT2 have logic values 1 and 0, respectively, bit line signals RBL1-RBL4 have voltage levels VL, VH, VH, VL, respectively. If weight bits W11 and W12 also have logic values 1 and 0, respectively, input bits IPT1, IPT2 and weight bits W11, W12 have 100% similarity. At this time, storage nodes N11 and N41-N43 have voltage levels VWH, VWL, VWL, VWH, respectively. Correspondingly, current signals IS11 and IS41-IS43 have current levels ILH, ILL, ILL, and ILH, respectively, so that current signal IM41 has a current level 2×ILH.

For another example, when the input bits IPT1 and IPT2 have logic values 1 and 0 respectively and the weight bits W21 and W22 have logic values 0 and 1 respectively, the input bits IPT1 and IPT2 and the weight bits W21 and W22 have 0% similarity. At this time, the bit line signals RBL1-RBL4 have voltage levels VL, VH, VH, VL respectively, and the storage nodes N44-N47 have voltage levels VWL, VWH, VWH, VWL respectively. Correspondingly, each of the current signals IS44-IS47 has a current level ILL, so that the current signal IM42 has a current level ILL.

As another example, when the input bits IPT1 and IPT2 have logic values 1 and 0 respectively and the weight bits W21 and W22 have logic values 1 and 1 respectively, the input bits IPT1 and IPT2 and the weight bits W21 and W22 have a similarity of 50%. At this time, the bit line signals RBL1-RBL4 have voltage levels VL, VH, VH, VL respectively, and the storage nodes N44-N47 have voltage levels VWH, VWH, VWL, VWL respectively. Correspondingly, the current signals IS44-IS47 have current levels ILH, ILL, ILL, ILL respectively, so that the current signal IM42 has a current level ILH.

In summary, in response to the similarity between the input bit and the weight bit being 0%, 50% and 100%, the current signal generated by the memory device 600 has current levels ILL, ILH and 2×ILH respectively. In this way, the similarity between the input bit and the weight bit can be determined by the current level to implement the search logic operation.

FIG. 7 is a schematic diagram of a memory device 700 according to an embodiment of the present invention. Referring to FIG. 7 and FIG. 6 , the memory device 700 is a variation of the memory device 600. Some components of the memory device 700 are labeled in the same manner as the memory device 600. For the sake of brevity, the discussion will focus on the differences between the memory device 700 and the memory device 600 rather than the similarities.

Compared to the memory device 600, in the memory device 700, the memory units 110, 411, 414, 415 and the memory units 412, 413, 416, 417 are arranged in different memory arrays. In addition, compared to the memory device 600, the memory device 700 further includes amplifiers 751-754 instead of amplifiers 451 and 452.

As shown in FIG. 7 , amplifier 751 couples resistors R3 and R41 to node N71. Amplifier 752 couples resistors R44 and R45 to node N72. Amplifier 753 couples resistors R42 and R43 to node N73. Amplifier 754 couples resistors R46 and R47 to node N74.

In operation, memory cells 110 and 411 are used to add current signals IS11 and IS41 at node N71 to generate current signal IM71. Amplifier 751 is used to generate voltage signal S71 according to current signal IM71. Memory cells 414 and 415 are used to add current signals IS44 and IS45 at node N72 to generate current signal IM72. Amplifier 752 is used to generate voltage signal S72 according to current signal IM72.

Similarly, memory cells 412 and 413 are used to add current signals IS42 and IS43 at node N73 to generate current signal IM73. Amplifier 753 is used to generate voltage signal S73 according to current signal IM73. Memory cells 416 and 417 are used to add current signals IS46 and IS47 at node N74 to generate current signal IM74. Amplifier 754 is used to generate voltage signal S74 according to current signal IM74.

In some embodiments, when one of the current signals IM71-IM74 has a current level ILH corresponding to a logic value of 1, the corresponding one of the voltage signals S71-S74 has a voltage level VL corresponding to a logic value of 1. When one of the current signals IM71-IM74 has a current level ILL corresponding to a logic value of 0, the corresponding one of the voltage signals S71-S74 has a voltage level VH corresponding to a logic value of 0.

In some embodiments, a processor (not shown) is used to determine the similarity between input bits IPT1, IPT2 and weight bits W11, W12 based on voltage signals S71 and S72, and to determine the similarity between input bits IPT1, IPT2 and weight bits W21, W22 based on voltage signals S73 and S74.

As shown in FIG7 and FIG6, the configuration of the memory device 700 or 600 can achieve search logic operation through the same or different memory arrays. In this way, the design can be carried out according to different specification requirements, so that the degree of freedom is improved.

Although the contents of this disclosure have been disclosed as above by way of embodiments, they are not intended to limit the contents of this disclosure. Any person with ordinary knowledge in the relevant technical field may make some changes and modifications without departing from the spirit and scope of the contents of this disclosure. Therefore, the protection scope of the contents of this disclosure shall be subject to the scope defined by the attached patent application.

100, 200, 300, 400, 600, 700: memory devices 110, 210, 411~417, 511~514: memory cells WWL1, RWL1, WWL2, RWL2, WWL51, RWL51, WWL52, RWL52: word line signals WBL1~WBL4, RBL1~RBL4, WBL51, WBL52: bit line signals W11~W14, W21~W24, WB11, WB12, WB21, WB22, W51~W54: weight bits IPT1~IPT4, IPTB1, IPTB2: input bits IS1, IS2, IM41, IM42, IS41~IS47, IS51~IS54 IM51, IM52, IM71~IM74: current signal T11, T12, T21, T22, T41~T414, T51~T58: switch N11, N21, N31, N41~N47, N51~N54: storage node M48, N49, N55, N56, N71~N74: node C11, C21, C41~C47, C51~C54: capacitor NV21, NV22, NV61, NV62: inverter R3, R41~R47, R51~R54: resistor 451, 452, 551, 552, 751~754: amplifier S41, S42, S51, S52, S71~S74: voltage signal

FIG. 1 is a schematic diagram of a memory device according to one embodiment of the present invention. FIG. 2 is a schematic diagram of a memory device according to one embodiment of the present invention. FIG. 3 is a schematic diagram of a memory device according to one embodiment of the present invention. FIG. 4 is a schematic diagram of a memory device according to one embodiment of the present invention. FIG. 5 is a schematic diagram of further details of a memory device according to one embodiment of the present invention. FIG. 6 is a schematic diagram of a memory device according to one embodiment of the present invention. FIG. 7 is a schematic diagram of a memory device according to one embodiment of the present invention.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

100: Memory device

110: Memory unit

WWL1, RWL1: word line signal

WBL1, RBL1: bit line signal

W11: Weight bit

IPT1: Input bits

IS1: Current signal

T11, T12: switch

N11: Storage Node

C11: Capacitor

Claims (10)

A memory device includes a first memory unit, the first memory unit is used to perform a logic operation according to a first weight bit and a first input bit, the first memory unit includes: a first switch, used to write the first weight bit into a first storage node; and a second switch, used to generate a first current signal according to the first weight bit and the first input bit, wherein a first end of the second switch is used to receive a first bit line signal carrying the first input bit, a second end of the second switch is used to receive a first word line signal, a control end of the second switch is coupled to the first storage node, When the first input bit has a first logic value, each of the first bit line signal and the first word line signal has a first voltage level, and When the first input bit has a second logic value, the first bit line signal has a second voltage level less than the first voltage level and the first word line signal has the first voltage level. A memory device as described in claim 1, wherein when the first storage node has a third voltage level, the first current signal has a first current level, when the first storage node has a fourth voltage level and the first input bit has the first logical value, the first current signal has the first current level, and when the first storage node has the fourth voltage level and the first input bit has the second logical value, the first current signal has a second current level greater than the first current level. A memory device as described in claim 2, wherein the logic operation is one of an AND logic operation, an OR logic operation, a NAND logic operation, and a NOR logic operation, When the logic operation is the AND logic operation or the OR logic operation, each of the fourth voltage level and the second current level corresponds to the second logic value, and When the logic operation is the NAND logic operation or the NOR logic operation, each of the fourth voltage level and the first current level corresponds to the second logic value. The memory device as described in claim 1 further comprises: a second memory unit for storing a second weight bit and receiving a second bit line signal carrying a second input bit to perform the logic operation together with the first memory unit, wherein the second weight bit complements the first weight bit, and the second input bit complements the first input bit. A memory device as described in claim 4, wherein the second memory unit comprises: a third switch for writing the second weight bit into a second storage node; and a fourth switch for generating a second current signal according to the second weight bit and the second input bit, wherein a first end of the fourth switch is used to receive the second bit line signal, a second end of the fourth switch is used to receive the first word line signal, and a control end of the fourth switch is coupled to the second storage node. The memory device as described in claim 1 further comprises: a second memory unit for storing a second weight bit and receiving a second bit line signal carrying a second input bit to generate a second current signal; a first amplifier coupled to a first node and used to generate a first voltage signal according to a third current signal; a third memory unit for storing a third weight bit and receiving the first bit line signal to generate a fourth current signal; a fourth memory unit for storing a fourth weight bit and receiving the second bit line signal to generate a fifth current signal; and a second amplifier coupled to a second node and used to generate a second voltage signal according to a sixth current signal, The second memory unit and the first memory unit are used to add the second current signal and the first current signal at the first node to generate the third current signal, and the third memory unit and the fourth memory unit are used to add the fourth current signal and the fifth current signal at the second node to generate the sixth current signal. The memory device as described in claim 1 further comprises: a second memory unit for storing a second weight bit and receiving a second bit line signal carrying a second input bit to generate a second current signal; a third memory unit for storing a third weight bit and receiving a third bit line signal carrying a third input bit to generate a third current signal; a fourth memory unit for storing a fourth weight bit and receiving a fourth bit line signal carrying a fourth input bit to generate a fourth current signal; and a first amplifier for receiving a fifth current signal at a first node, The first memory unit, the second memory unit, the third memory unit and the fourth memory unit are used to add the first current signal, the second current signal, the third current signal and the fourth current signal at the first node to generate the fifth current signal, and the first weight bit, the second weight bit, the first input bit and the second input bit complement the third weight bit, the fourth weight bit, the third input bit and the fourth input bit respectively. The memory device as described in claim 1 further comprises: a second memory unit for storing a second weight bit and receiving a second bit line signal carrying a second input bit to generate a second current signal; a third memory unit for storing a third weight bit and receiving a third bit line signal carrying a third input bit to generate a third current signal; a fourth memory unit for storing a fourth weight bit and receiving a fourth bit line signal carrying a fourth input bit to generate a fourth current signal; and a first amplifier for receiving a fifth current signal at a first node; and a second amplifier for receiving a sixth current signal at a second node, The first memory unit and the second memory unit are used to add the first current signal and the second current signal at the first node to generate the fifth current signal, the third memory unit and the fourth memory unit are used to add the third current signal and the fourth current signal at the second node to generate the sixth current signal, and the first weight bit, the second weight bit, the first input bit and the second input bit complement the third weight bit, the fourth weight bit, the third input bit and the fourth input bit respectively. A method for operating a memory device, comprising: Writing a first weight bit into a first storage node of a first memory unit; Receiving a first bit line signal carrying a first input bit through the first memory unit; Performing a logic operation according to the first input bit and the first weight bit to generate a first current signal passing through a first switch in the first memory unit; When the first storage node has a first voltage level, closing the first switch and the first current signal has a first current level; When the first storage node has a second voltage level and the first bit line signal has a third voltage level, turning on the first switch and the first current signal has the first current level; and When the first storage node has the second voltage level and the first bit line signal has a fourth voltage level, the first switch is turned on and the first current signal has a second current level, wherein the second current level is greater than the first current level, and the third voltage level is greater than the fourth voltage level. The operation method as described in claim 9 further includes: Inverting the first input bit to generate a second input bit; Inverting the first weight bit to generate a second weight bit; Writing the second weight bit into a second storage node of a second memory unit; Receiving a second bit line signal carrying the second input bit through the second memory unit; Generating a second current signal through a second switch in the second memory unit based on the second input bit and the second weight bit; and Adding the first current signal and the second current signal to generate a third current signal corresponding to the output of the logic operation.

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