TWI876385B - Resistive random-access memory devices with compound non-reactive electrodes - Google Patents

Abstract

The present invention relates to a resistive random access memory (RRAM) device. In some embodiments, the RRAM device includes a first electrode, a second electrode including a first conductive material, and a switching oxide layer located between the first electrode and the second electrode. The switching oxide layer includes at least one transitional metal oxide. The first electrode includes a metal nitride layer including a metal nitride and a metal layer fabricated on the metal nitride layer. The metal layer includes a metal that does not react with the at least one transitional metal oxide. In some embodiments, the metal nitride in the first electrode includes titanium nitride and/or tantalum nitride. The metal layer includes a noble metal layer, such as platinum, palladium, iridium, or ruthenium.

Description

Resistive random access memory device with compound non-reactive electrode

Embodiments of the present invention generally relate to a resistive random access memory (RRAM), and more particularly, to a RRAM device having a compound non-reactive electrode.

RRAM devices are two-terminal passive devices with adjustable and non-volatile resistance. The resistance of the RRAM device can be electrically switched between a high resistance state (HRS) and a low resistance state (LRS) by applying a suitable programming signal to the RRAM device. RRAM devices can be used to form a crossbar array, which can be used to implement in-memory computing applications, non-volatile solid-state storage, image processing applications, neural networks, etc.

The following is a brief summary of the invention, which is used to provide a basic understanding of some aspects of the invention. The invention content is not a broad overview of the invention. The invention content is not intended to identify the key or important elements of the invention, nor is it intended to illustrate any scope of a specific implementation of the invention or any scope of the scope of the patent application. The sole purpose of the invention content is to simplify some concepts of the invention as a language for a more detailed description presented later.

According to one or more aspects of the present invention, a resistive random access memory (RRAM) device includes: a first electrode, a second electrode including a first conductive material; and a switching oxide layer located between the first electrode and the second electrode. The first electrode includes a metal nitride layer including a metal nitride and a metal layer fabricated on the metal nitride layer. The switching oxide layer includes at least one transitional metal oxide. In some embodiments, the metal layer includes a metal that does not react with the at least one transitional metal oxide.

In some embodiments, the metal nitride includes at least one of titanium nitride or titanium nitride.

In some embodiments, the metal that does not react with the at least one transition metal oxide includes at least one of platinum, palladium, iridium, or ruthenium.

In some embodiments, the metal layer is thinner than the metal nitride layer.

In some embodiments, the thickness of the metal layer is between 3 nm and 10 nm.

In some embodiments, the thickness of the metal nitride layer is between 20 nm and 50 nm.

In some embodiments, the at least one transitional metal oxide includes at least one of HfOx or TaOy, where x≤2.0 and y≤2.5.

In some embodiments, the conductive material in the second electrode includes tantalum.

In some embodiments, the RRAM device further comprises an interface layer between the switching oxide layer and the second electrode. In some embodiments, the interface layer comprises aluminum oxide.

In some embodiments, the RRAM device further includes an adhesion layer of at least one selected from titanium or tantalum, wherein the metal nitride layer is fabricated on the adhesion layer.

According to one or more methods disclosed in the present invention, a method for manufacturing a resistive random access memory (RRAM) device includes: manufacturing a first electrode; manufacturing the switching oxide layer on the first electrode; and manufacturing a second electrode including a conductive material on the switching oxide layer. The switching oxide layer includes at least one transitional metal oxide. The first electrode includes: a metal nitride layer and a metal layer. The metal nitride layer includes a metal nitride. The metal layer is manufactured on the metal nitride layer. In some embodiments, the metal layer includes a metal that does not react with the at least one transitional metal oxide.

In some embodiments, the metal nitride includes at least one of titanium nitride or titanium nitride.

In some embodiments, the metal that does not react with the at least one transition metal oxide includes at least one of platinum, palladium, iridium, or ruthenium.

In some embodiments, the metal layer is thinner than the metal nitride layer.

In some embodiments, the thickness of the metal layer is between 3 nm and 10 nm.

In some embodiments, the thickness of the metal nitride layer is between 20 nm and 50 nm.

In some embodiments, the at least one transitional metal oxide includes at least one of HfOx or TaOy, where x≤2.0 and y≤2.5.

In some embodiments, the method further includes fabricating an interface layer on the switching oxide layer, wherein the interface layer is located between the switching oxide layer and the second electrode, and the interface layer includes aluminum oxide.

In some embodiments, the method further includes fabricating an adhesion layer comprising at least one of titanium or tantalum, wherein the metal nitride layer is fabricated on the adhesion layer.

According to one or more aspects of the present invention, a method for manufacturing a non-reactive electrode includes: manufacturing an adhesion layer including at least one of titanium or tantalum; manufacturing a metal nitride layer including at least one metal nitride on the adhesion layer, wherein the metal nitride includes at least one of titanium nitride or tantalum nitride; manufacturing a metal layer including a noble metal on the metal nitride layer; and selectively removing one or more portions of the adhesion layer, the metal nitride layer, and the metal layer to manufacture the non-reactive electrode.

Various aspects of the present invention provide RRAM devices and methods for making RRAM devices. An RRAM device is a two-terminal passive device with adjustable resistance. The RRAM device may include a first electrode, a second electrode, and a switching oxide layer located between the first electrode and the second electrode. In some embodiments, the first electrode and the second electrode may be the bottom electrode and the top electrode of the RRAM device, respectively. In some embodiments, the first electrode and the second electrode may be the top electrode and the bottom electrode of the RRAM device, respectively. The first electrode may include a non-reactive metal, such as platinum (Pt), palladium (Pd), ruthenium (Ru), etc. The second electrode may include a reactive metal, such as tantalum (Ta). An electrode including a non-reactive metal may also be referred to as a "non-reactive electrode". Electrodes comprising reactive metals may also be referred to as "reactive electrodes". The switching oxide layer may include a transition metal oxide, such as tantalum oxide (HfOx) or tantalum oxide (TaOx). The RRAM device may be in an initial state or a primitive state and have an initial high resistance before it receives an appropriate electrical stimulus (e.g., a voltage or current signal applied to the RRAM device). The RRAM device may be converted from the primitive state to a low resistance state by a formation process, or may be switched from a high resistance state to a low resistance state by a setup process. The formation process refers to programming the device from the primitive state. The setup process refers to programming the device from a high resistance state (HRS). After the reactive metal electrode is deposited on the switching oxide, the reactive metal can absorb oxygen ions from the switching oxide layer, creating oxygen vacancies in the switching oxide layer, and the oxygen ions can migrate in the switching oxide through a vacancy mechanism. During the formation process, an appropriate programming signal (e.g., a voltage or current signal) applied to the RRAM device can cause the oxygen ions to drift from the switching oxide to the reactive electrode. As a result, a conductive channel or conductive filament can pass through the switching oxide layer (e.g., from the reactive electrode to the non-reactive electrode). Then, the RRAM device can be reset to a high-resistance state by applying a reset signal (e.g., a voltage signal, a current signal) to the RRAM device. Applying the reset signal to the RRAM device can cause the oxygen ions to migrate back to the switching oxide layer, thereby possibly interrupting the conductive filament. By applying an appropriate programming signal (e.g., a voltage signal, a current signal) to the RRAM device, the RRAM device can be electrically switched between a high resistance state and a low resistance state. In a crossbar array circuit, the programming signal can be provided to a designated RRAM device through a selector, such as a transistor or a diode.

RRAM devices containing platinum (Pt) in a non-reactive electrode can provide RRAM high performance, such as reliability, durability, multi-level, retention, etc. In an RRAM device including a bottom electrode containing platinum, a switching oxide layer including tantalum oxide, and Ta (also referred to as a "Pt/TaOx/Ta system"), Ta filaments in TaOx exhibit excellent linearity, analog, retention, and durability. In a Pt/HfOx/Ta system, Ta can migrate into HfOx to form Ta-rich filaments in HfOx, and exhibit excellent linearity, analog, retention, and durability in IMC applications. However, the material and processing costs of platinum are high, and major manufacturers may not be ready to incorporate platinum in their production processes.

According to some embodiments of the present invention, the compound non-reactive electrode of the RRAM device may include a metal nitride layer and a metal layer. The metal nitride layer may include one or more metal nitrides, such as TiN, TaN, etc. The metal layer may include a non-reactive metal, such as Pt, Pd, Ru, Ir, etc. The metal layer may be much thinner than the metal nitride. For example, in some embodiments, the metal nitride layer may be between about 20nm and 25nm, and the metal layer may be between about 3nm and about 8nm.

Both TiN and TaN are conductive materials and are also compatible with CMOS processes, can be mass-produced, and have a much lower production cost than Pt. RRAM devices containing TiN or TaN in non-reactive electrodes can exhibit specific characteristics required for IMC applications, such as multi-level switching resistance and/or analog behavior. RRAM devices with non-reactive electrodes containing Pt can have better performance than RRAM devices with non-reactive electrodes that include TiN or TaN alone, but may be more expensive. By bonding a metal nitride layer and a metal layer that is much thinner than the metal nitride layer (e.g., a layer of Pt, Pd, Ru, Ir, etc.), the manufacturing compound non-reactive electrode described in this article provides an economical and efficient solution for manufacturing RRAM devices with desired switching and analog resistance behavior.

Compared with conventional RRAM devices using Pt-based non-reactive electrodes, the RRAM device using compound non-reactive electrodes of the present invention has lower material and manufacturing costs, can be used in CMOS processes, and can be mass-produced. The RRAM device of the present invention exhibits appropriate performance and capabilities in multi-level switching and analog behavior.

Fig. 1 is a schematic diagram showing an example 100 of a crossover switch circuit according to some embodiments of the present invention. As shown in the figure, the crossover switch circuit 100 may include a plurality of interconnected conductive lines for a crossover array of n rows by m columns, such as one or more row lines 111a, 111b, ..., 111i, ..., 111n, and column lines 113a, 113b, ..., 113j, ..., 113m. The crossover switch circuit 100 may further include crosspoint devices 120a, 120b, ..., 120z, etc. Each crosspoint device may connect a row line and a column line. For example, a crosspoint device 120ij may connect a row line 111i and a column line 113j. In some embodiments, the crossbar switch circuit 100 may further include a digital-to-analog converter (DAC, not shown), an analog-to-digital converter (ADC, not shown), a switch (not shown), and one or more appropriate circuit components for implementing a crossbar-based device. The number of column lines 113a-m and the number of row lines 111a-n may be the same or different.

The row lines 111 may include a first row line 111a, a second row line 111b, ..., 111i, ..., and an nth row line 111n. Each row line 111a, ..., 111n may be and/or include any suitable conductive material. In some embodiments, each row line 111a-n may be a metal line.

The column lines 113 may include a first column line 113a, a second column line 113b, ... and an mth column line 113m. Each column line 113a-m may be and/or include any suitable conductive material. In some embodiments, each column line 113a-m may be a metal line.

Each cross-point device 120 may be and/or include any suitable device having an adjustable resistance, such as a memory resistor, a phase change memory (PCM) device, a floating gate, a spintronic device, a resistive random access memory (RRAM), a static random access memory (SRAM), etc. In some embodiments, one or more of the cross-point devices 120 may include an RRAM device as described in conjunction with FIGS. 3A-9C .

The cross-switch circuit 100 can perform parallel weighted voltage multiplication and current summation. For example, an input voltage signal can be applied to one or more rows (e.g., one or more selected rows) of the cross-switch circuit 100. The input signal can flow through the cross-point devices of the rows of the cross-switch circuit 100. The conductance of the cross-point device can be adjusted to a specific value (also referred to as a "weighted value"). According to Ohm's law, the input voltage is multiplied by the cross-point conductance and generates a current flowing through the cross-point device. Through Kirchhoff's law, the sum of the currents through the devices on each column generates a current as an output signal, which can be read from the column (e.g., the output of an ADC). According to Ohm's law and Kirchhoff's current law, the input-output relationship of the crossbar array can be expressed as I=VG, where I is the output signal matrix, expressed as current; V is the input signal matrix, expressed as voltage; and G is the conductivity matrix of the crosspoint device. Therefore, the input signal is weighted by its conductivity at each crosspoint device according to Ohm's law. The weighted current is output through each column line and accumulated according to Kirchhoff's current law. This can be achieved by implementing in-memory computing (IMC) through parallel multiplication and summation in the crossbar array.

FIG2 is a schematic diagram showing an example 200 of a cross-point device according to an embodiment of the present invention. As shown, the cross-point device 200 can connect a bit line (BL) 211, a select line (SEL) 213, and a word line (WL) 215. The bit line 211 and the word line 215 shown can be a column line and a row line as described in FIG1, respectively.

The cross-point device 200 may include a RRAM device 201 and a transistor 203. A transistor is a three-terminal device that may be labeled as a gate (G), a source (S), and a drain (D). The transistor 203 may be connected in series to the RRAM device 201. As shown in FIG. 2 , a first electrode of the RRAM device 201 may be connected to a drain of the transistor 203. A second electrode of the RRAM device 201 may be connected to a bit line 211. A source of the transistor 203 may be connected to a word line 215. A gate of the transistor 203 may be connected to a select line 213. The RRAM device 201 may include one or more RRAM devices in combination as described in FIGS. 3A-9C below. The cross-point device 200 may also be referred to as a one-transistor-one-resistor (1T1R) configuration. The transistor 203 can be used as a selector as well as a current controller, which can set the current compliance of the RRAM device 201 during programming. The gate voltage of the transistor 203 can set the current compliance of the cross-point device 200 during programming, and thus control the conductance and analog behavior of the cross-point device 200. For example, when the cross-point device 200 is set from a high-resistance state to a low-resistance state, a set signal (e.g., a voltage signal, a current signal) can be provided through the bit line (BL) 211. Another voltage, also referred to as a select voltage or gate voltage, can be applied to the transistor gate through the select line (SEL) 213 to open the gate and set the current compliance, and the word line (WL) 215 can be set to ground. When the cross-point device 200 is reset from a low resistance state to a high resistance state, a gate voltage can be applied to the gate of the transistor through the select line 213 to turn on the transistor gate. At the same time, a reset signal can be sent to the RRAM device 201 through the word line 215, and the bit line 211 can be set to ground.

3A, 3B, and 3C illustrate cross-sectional views of example RRAM devices 300a, 300b, and 300c according to some embodiments of the present invention. The RRAM devices 300b and 300c may correspond to a low resistance state and a high resistance state of the RRAM device 300a, respectively.

As shown in FIG. 3A , the RRAM device 300 a may include a substrate 310, a first electrode 320 fabricated on the substrate 310, a switching oxide layer 330, and a second electrode 340. The switching oxide layer 330 is fabricated between the first electrode 320 and the second electrode 340. The substrate 310 may include one or more layers of any suitable material that may be used for a RRAM device substrate, such as silicon (Si), silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), aluminum nitride (AlN), etc. In some embodiments, the substrate 310 may include a diode, a transistor, an interconnect, an integrated circuit, etc. In some embodiments, the substrate may include a driver circuit including one or more circuits (e.g., a circuit array) that can be individually controlled. In some embodiments, the driver circuit may include one or more complementary metal oxide semiconductor (CMOS) drivers.

The first electrode 320 may include a metal nitride that is conductive and non-reactive to the fabricated switching oxide layer. The metal nitride may have suitable chemical stability so that it does not react with oxygen during RRAM switching. The metal nitride may include, for example, titanium nitride (TiN), tantalum nitride (TaN), etc. The first electrode 320 may also include a non-reactive metal that has electronic conductivity and does not react with oxygen during RRAM switching, such as platinum (Pt), palladium (Pd), iridium (Ir), ruthenium (Ru), etc. RRAM devices having metal nitrides and non-reactive metals at their non-reactive electrodes have multi-level resistance and analog behavior required for IMC applications.

In some embodiments, the first electrode 320 may be and/or include a compound bottom electrode as described in conjunction with FIG. 4. For example, the first electrode 320 may include a metal nitride layer including one or more metal nitrides (e.g., TiN, TaN, etc.). The first electrode 320 further includes a metal layer including one or more precious metals (e.g., Pt, Pb, Ir, Ru, etc.) fabricated on the metal nitride layer. In some embodiments, the metal layer is thinner than the metal nitride layer.

In some embodiments, a Ta and/or Ti layer may be fabricated between the first electrode and the substrate 310 to enhance adhesion between the substrate 310 and the RRAM device 320 assembly.

The switching oxide layer 330 may include one or more transition metal oxides among binary oxides, ternary oxides, and higher oxides, such as _TaOx , _HfOx , _TiOx , _NbOx , _ZrOx , etc. In some embodiments, the chemical stability of the non-reactive material in the first electrode 320 may be higher than the chemical stability of the transition metal oxide in _the switching oxide layer 330. In some embodiments, the transitional metal oxide includes at least one of _HfOx or _TaOx , where x can be used to indicate that the oxide is oxygen-deficient compared to its complete (or terminal) oxide, and the value of x can vary depending on the ratio of oxygen and metal atoms in the stoichiometry of its complete oxide, for example, for _HfOx (where _HfO2 is a complete oxide), x≤2.0, and for _TaOx (where _Ta2O5 is a complete _oxide ), x≤2.5.

The second electrode 340 may include any suitable metal material that is electronically conductive and reactive to the switching oxide. For example, the metal material in the second electrode 340 may include Ta, Hf, Ti, TiN, TaN, etc. The second electrode 340 may react with the switching oxide and have a suitable oxygen solubility so that oxygen can be absorbed from the switching oxide layer 330 and oxygen vacancies can be generated in the switching oxide layer 330. In other words, the reactive metal material in the second electrode 340 may have a suitable oxygen solubility and/or oxygen mobility. In some embodiments, the second electrode 340 may not only generate oxygen vacancies in the switching oxide layer 330 (e.g., by scavenging oxygen), but may also serve as an oxygen reservoir or oxygen source for the switching oxide layer 330 during cell programming.

The RRAM device 330a may have an initial resistance (also referred to herein as "original resistance") after fabrication. The initial resistance of the RRAM device 300a may be changed, and the RRAM device 300a may be switched to a lower resistance state through a formation process. For example, an appropriate voltage or current may be applied to the RRAM device 300a. The voltage applied to the RRAM device 300a may cause the metal material in the second electrode to absorb oxygen from the switching oxide layer 330 and generate oxygen vacancies in the switching oxide layer. As a result, a conductive channel (e.g., a conductive filament) rich in oxygen vacancies may be formed in the switching oxide layer 330. For example, as shown in FIG. 3B , a conductive channel 335a may be formed in the switching oxide layer. As shown, the conductive path 335a can cross the switching oxide layer 330 from the second electrode 340 to the first electrode 320. The RRAM device 300b can be reset to a high resistance state. For example, a reset signal (e.g., a voltage signal or a current signal) can be applied to the RRAM device 300b during the reset process. In some embodiments, the set signal and the reset signal can have opposite polarities, such as a positive signal and a negative signal, respectively. The application of the reset signal can cause oxygen to drift back to the switching oxide layer 330 and recombine with one or more oxygen vacancies. For example, during the reset process, an interrupted conductive path 335b as shown in Figure 3C can be formed in the switching oxide layer 330. As shown, the conductive channel may be interrupted by an oxide gap between the interrupted conductive channel 335b and the first electrode 320. The lateral dimension of the interrupted conductive channel 335b may be smaller than the lateral dimension of the conductive channel 335a. In some embodiments, the interrupted conductive channel 335b does not continuously connect the first electrode 320 and the second electrode 340. The RRAM devices 300a-c may be electrically switched between a high resistance state and a low resistance state by applying an appropriate programming signal (e.g., a voltage signal, a current signal, etc.) to the RRAM device.

In one embodiment, the second electrode 340 may include one or more alloys. Each alloy may include two or more metal elements. Each alloy may include a binary alloy (e.g., an alloy containing two metal elements), a ternary alloy (e.g., an alloy containing three metal elements), a quaternary alloy (e.g., an alloy containing four metal elements), a quinary alloy (e.g., an alloy containing five metal elements), and/or a high-order alloy (e.g., an alloy containing six or more metal elements). In some embodiments, the second electrode 340 may include one or more alloys containing a first metal element and one or more second metal elements. Each second metal element has a reactivity to the transitional metal oxide in the switching oxide layer that is less than or greater than the first metal element. In some embodiments, the first metal element may be Ta. The second metal element may include one or more of tungsten (W), niobium (Hf), molybdenum (Mo), niobium (Nb), zirconium (Zr), etc. In some embodiments, the ratio of the first metal element to the second metal element of the alloy in the second electrode 340 may be 50 atomic percent. In some embodiments, the appropriate ratio of the first metal element to the second metal element in the alloy may be optimized from the entire composition range. During the formation process, the second metal element may produce fewer oxygen vacancies in the switching oxide layer than the first metal element. Therefore, the lateral size of the conductive filament formed in the RRAM device including the second electrode containing the alloy may be smaller than the lateral size of the conductive filament formed in the RRAM device including the second electrode made of only the first metal.

In one embodiment, the second electrode 340 may include multiple layers of different metal materials. For example, the second electrode 340 may include a titanium (Ti) layer and a tantalum (Ta) layer. The Ti layer may be much thinner than the Ta layer. For example, the thickness of the Ti layer may be between about 0.2nm and 5nm. The thickness of the Ta layer may be about 50nm. In some embodiments, the thickness of the Ti layer may be between 0.3nm and 2nm. Both Ti and Ta can capture and release oxygen during device operation. Adding a thin Ti layer to a RRAM device can change the original resistance of the RRAM device, resulting in a less obtrusive formation process, lower formation voltage, lower reset current, and lower voltage and/or current requirements in subsequent operations.

FIG4 shows a cross-sectional view of an example of a compound non-reactive electrode 400 according to another embodiment of the present invention.

As shown, the non-reactive electrode 400 may include a metal nitride layer 410 and a metal layer 420. The metal layer 420 may be fabricated on the metal nitride layer 410. The metal nitride layer 410 may include one or more layers of one or more metal nitrides. Examples of the metal nitrides may include TiN, TaN, etc. The metal layer 420 may include one or more precious metals (e.g., Pt, Pb, Ru, etc.). In some embodiments, the metal layer 420 may be thinner than the metal nitride layer 410. In some embodiments, the thickness of the metal nitride layer 410 may be between about 20 nm and about 25 nm. In some embodiments, the thickness of the metal nitride layer 410 may be between about 20 nm and about 50 nm. In some embodiments, the thickness of the metal nitride layer 410 may be between about 20 nm and about 30 nm. The thickness of the metal layer 420 may be between about 3 nm and about 10 nm. In some embodiments, the metal layer 420 may be thicker than 2-3 nm and may include a continuous film of a noble metal covering the metal nitride layer 410.

FIG. 5 illustrates a cross-sectional view of an example RRAM device 500 including a compound non-reactive electrode according to one embodiment of the present invention.

The RRAM device 500 may include an adhesion layer 510, a first electrode 520, a switching oxide layer 530, an interface layer A (ILA) 550, and a second electrode 540. The first electrode 520, the switching oxide layer 530, and the second electrode 540 may be respectively the same as the first electrode 320, the switching oxide layer 330, and the second electrode 340 described in conjunction with FIG. 3A. As shown, the first electrode 520 may include the metal nitride layer 410 and the metal layer 420 described in conjunction with FIG. 4. In some embodiments, the adhesion layer 510 may be considered as a part of the first electrode 520.

The adhesion layer 510 may include one or more suitable metal materials that may enhance adhesion between the substrate and the RRAM device 500 assembly. In some embodiments, the adhesion layer 510 may include one or more layers of Ti, Ta, etc.

The ILA 550 (also referred to as a "first interface layer") may include a first material that is more chemically stable than the transition metal oxide in the switching oxide layer. The first material may include, for example, _Al2O3 , _MgO , _Y2O3 , _La2O3 , _{etc. The} ILA 550 may include a non-continuous film of the first material and/or a continuous film of the first material. In some embodiments, the thickness of the ILA 550 may be between about 0.2nm and about 0.5nm. In some embodiments, the ILA 550 may include _{an Al2O3} film having a thickness equal to or less than 0.5nm. In some embodiments, the ILA 550 may be and/or include _{an Al2O3} film having a thickness less than 1nm. In the case where the ILA 550 includes aluminum oxide, the RRAM device may be a high resistance and annealing resistant RRAM device.

FIG. 6 illustrates a cross-sectional view of an example RRAM device 600 including a compound non-reactive electrode according to a further embodiment of the present invention.

The RRAM device 600 may include an adhesion layer 610, a first electrode 620, an interface layer B (ILB) 660, a switching oxide layer 630, an interface layer A (ILA) 650, and a second electrode 640. The first electrode 620, the switching oxide layer 630, and the second electrode 640 may be the same as the first electrode 320, the switching oxide layer 330, and the second electrode 340 described in conjunction with FIG. 3A, respectively. The adhesion layer 610 may be the same as the adhesion layer 510 in FIG. 5. The ILA 650 may be the same as the ILA 550 in FIG. 5. In some embodiments, the RRAM device 600 may further include a substrate (not shown) as described in conjunction with FIG. 3A.

The ILB 660 may include a second material that is more chemically stable than the transition metal oxide in the switching oxide layer 630. The second material may include, for example, Al ₂ O ₃ , MgO, Y ₂ O ₃ , La ₂ O ₃ , etc. The ILB 660 may include a non-continuous film of the second material and/or a continuous film of the second material. In some embodiments, the thickness of the ILB 660 may be between about 0.2 nm and about 0.5 nm. In some embodiments, the ILB 660 may include an Al ₂ O ₃ film having a thickness equal to or less than 0.5 nm. In some embodiments, the ILB 660 may be and/or include an Al 2 O 3 film having a thickness less than 1 nm. With the first interface layer and the second interface layer, the RRAM device may be a high resistance and annealing resistant RRAM device.

In some embodiments, the ILA 650 may be omitted from the RRAM device 600. For example, as shown in FIG7 , the RRAM device 700 may include the adhesion layer 610, the first electrode 620, the interface layer B (ILB) 660, the switching oxide layer 630, and the second electrode 640 described in conjunction with FIG6 .

8A, 8B, 8C, 8D, 8E and 8F are schematic diagrams showing cross-sectional views of structures of non-reactive electrodes in manufacturing RRAM devices according to some embodiments of the present invention.

As shown in FIG8A , a substrate 810 may be provided. The substrate 810 may include one or more layers of any suitable material that may be used to fabricate a substrate for an RRAM device, such as silicon (Si), silicon dioxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), etc. In some embodiments, the substrate 810 may include diodes, transistors, interconnects, integrated circuits, etc. The substrate 810 may include a driver circuit that may individually control one or more circuits (e.g., a circuit array). In some embodiments, the driver circuit may include one or more complementary metal oxide semiconductor (CMOS) drivers. In some embodiments, substrate 810 may include one or more dielectric layers, interconnect layers, transistors, and/or any other suitable components (not shown) for fabricating cross-circuit circuits. Each interconnect layer may include one or more metal pads and/or metal vias, and may provide electrical connections between devices fabricated on substrate 810.

As shown in FIG8A , substrate 810 may include an interconnect layer of one or more metal interconnects (e.g., metal pads and/or metal vias). For example, a first interconnect layer may include metal interconnects 811a and 811b (also referred to as “first metal interconnects” and “second metal interconnects”). In some embodiments, metal interconnects 811a and 811b may be metal pads containing tungsten (W), Al, Cu, and any other suitable metal. In some embodiments, metal interconnects 811a and 811b may be metal vias containing aluminum (Al), copper (Cu), tungsten (W), etc. Each of metal interconnects 811a and 811b may be connected to other components (not shown), such as transistors, diodes, etc. In some embodiments, metal interconnects 811a-b may include tungsten (W) holes and doped polysilicon (poly-Si) terminals, where the poly-Si terminals may be connected to transistor or diode terminals (not shown).

8B, an adhesion layer 821 may be fabricated on metal interconnects 811a and 811b and substrate 810. Adhesion layer 821 may include a Ta layer, a Ti layer, and/or a layer of any suitable material that may enhance adhesion of substrate 810 and other components in a RRAM device fabricated on substrate 810.

8C, a metal nitride layer 823 may be fabricated on the adhesion layer 821. The metal nitride layer 823 may include one or more layers of one or more metal nitrides that are electronically conductive and non-reactive to switching oxide in the RRAM device fabricated on the substrate 810. The metal nitride may include, for example, TiN, TaN, etc.

As shown in FIG8D , a metal layer 825 may be fabricated on the metal nitride layer 823. The metal layer 825 may include one or more layers of one or more suitable metals (also referred to as “non-reactive metals”) that are electronically conductive and non-reactive to switching oxides in RRAM devices fabricated on the substrate 810. Examples of the non-reactive metals may include Pt, Pd, Ir, Ru, etc.

One or more portions of the adhesion layer 821, the metal nitride layer 823, and the metal layer 825 may be selectively removed to fabricate one or more bottom electrodes. For example, as shown in FIG8E, by patterning and etching the adhesion layer 821, the metal nitride layer 823, and the metal layer 825, a first bottom electrode 820a and a second bottom electrode 820b may be fabricated on the metal interconnect 811a and the metal interconnect 811b, respectively. The first bottom electrode 820a may include a first adhesion layer 821a, a first metal nitride layer 823a, and a first metal layer 825a. The second bottom electrode 820b may include a second adhesion layer 821b, a second metal nitride layer 823b, and a second metal layer 825b. The first adhesion layer 821a and 821b may correspond to the etched adhesion layer 821. The first metal nitride layer 823a and the second metal nitride layer 823b may correspond to the etched metal nitride layer 822. The first metal layer 825a and the second metal layer 825b may correspond to the etched metal layer 825. In some embodiments, the lateral dimensions of the bottom electrodes 820a-b may be greater than the lateral dimensions of the metal interconnects 811a-b. The first bottom electrode 820a may directly contact the metal interconnect 811a to form an ohmic contact. The second bottom electrode 820b may directly contact the metal interconnect 811b to form an ohmic contact. The first bottom electrode 820a and the second bottom electrode 820b may further contact one or more portions of the substrate 810, such as one or more portions of the surface 801 of the substrate 810 (eg, the top surface of the substrate 810).

As shown in FIG8F, RRAM stack 830a and RRAM stack 830b can be fabricated on first bottom electrode 820a and second bottom electrode 820b, respectively. Each of RRAM stacks 830a and 830b can include a switching oxide layer, a top electrode, and one or more interface layers as described above in conjunction with FIGS. 3A-7. In some embodiments, RRAM stacks 830a and 830b can be fabricated using techniques described in U.S. Patent Application Nos. 17/654,476 and 17/936,830, which are incorporated herein by reference.

FIG. 9A shows a characteristic graph 900A of I-V (current-voltage) characteristics of an example RRAM device including a compound non-reactive electrode according to some embodiments of the present invention. FIG. 9B shows a characteristic graph 900B of an I-V curve showing simulated behavior of the RRAM device. FIG. 9C shows a characteristic graph 900C of a device read current characteristic of an example RRAM device over time.

As shown in FIG. 9A , the RRAM device provides repeatable and expected set-reset operation for multiple switches (e.g., switch 1, switch 2, and switch 3), demonstrating the stability of multiple switch behaviors. As shown in FIG. 9B , the RRAM device exhibits expected analog behavior. That is, the device resistance can be adjusted to multiple levels (or analog behavior) by controlling the current compliance, and the current is linearly proportional to the voltage (or linear behavior) in each resistance state. As shown in FIG. 9C , the characteristic curve graph 900C can represent the results of a device retention test of the ability of the RRAM device to maintain the resistance level over time, and the results of a read stability test when the RRAM device is in a constant read (with a read voltage of 0.2V) due to its ability to maintain the resistance level over time. As shown in FIG. 9C , the RRAM device exhibits the desired device read stability over time.

FIG. 10 shows a flow chart of an example method 1000 for manufacturing an RRAM device (eg, the RRAM devices 500 , 600 , and 700 shown in FIGS. 5 , 6 , and 7 ) according to some embodiments of the present invention.

In 1010, a first electrode may be fabricated on a substrate. Fabricating the first electrode may include depositing one or more layers of a metal nitride, such as TiN or TaN. For example, fabricating the first electrode may include depositing one or more layers of TiN using an atomic layer deposition (ALD) technique, a physical vapor deposition (PVD) technique, a Ti reactive sputtering technique, and/or any other suitable deposition technique. Fabricating the first electrode may further include depositing one or more non-reactive metals on the metal nitride. The first electrode may be and/or include a compound non-reactive electrode as described above in conjunction with FIG. 4 . In some embodiments, fabricating the first bottom electrode may involve performing one or more operations as described below in FIG. 11 .

In 1020, an interface layer B (ILB) can be fabricated on the first electrode. The ILB can include _a material that is more chemically stable than the transition metal oxide (e.g., _AlOx , such as _Al2O3 ) in the switching oxide layer described later. For example, fabricating the interface layer B can include depositing _AlOx using an atomic layer deposition (ALD) technique, a physical vapor deposition (PVD) technique, an Al reactive sputtering technique, and/or any other suitable deposition technique. The interface layer B can be and/or include the ILB 660 described above in conjunction with FIG. 6. In some embodiments, step 1020 can be omitted from the manufacturing method example 1000.

In 1030, the switching oxide layer including one or more transitional metal oxides may be fabricated on the interface layer B. The transitional metal oxide may include, for example, HfOx. For example, fabricating the switching oxide layer may include depositing HfOx using an atomic layer deposition (ALD) technique, a physical vapor deposition (PVD) technique, a reactive sputtering technique of Hf, and/or any other suitable deposition technique. The switching oxide layer may be and/or include the switching oxide layer 630 described above in conjunction with FIG. 6 .

In 1040, an interface layer A (ILA) may be fabricated on the switching oxide layer. The ILA may include a metal that is more chemically stable than the transition metal oxide in the switching oxide layer, such as _AlOx , such as _Al2O3 . For example, fabricating the interface layer A may include depositing _AlOx using an atomic layer deposition ( _ALD ) technique, a physical vapor deposition (PVD) technique, an Al reactive sputtering technique, and/or any other suitable deposition technique. The interface layer A may be and/or include the ILA 650 described above in conjunction with FIG. 6.

In 1050, a second electrode may be fabricated on the interface layer A. Fabricating the second electrode may involve fabricating one or more layers of one or more metal materials that are electronically conductive and reactive to the switching oxide. For example, fabricating the second electrode may include depositing one or more Ta layers using physical vapor deposition (PVD) techniques and/or any other suitable deposition techniques. The second electrode may be and/or include the second electrode 640 described above in conjunction with FIG. 6 .

11 shows a flow chart of an example method 1100 for manufacturing a non-reactive electrode according to some embodiments of the present invention, such as the non-reactive electrode described in conjunction with FIG. 4 and FIGS. 8A-8F .

In 1110, an adhesive layer may be fabricated on the substrate. Fabricating the adhesive layer may include depositing a metal layer, such as Ta, Ti, etc., which may enhance adhesion between the substrate and the bottom electrode and/or other components of the RRAM device fabricated on the substrate. In some embodiments, fabricating the adhesive layer may involve depositing a Ti film or a Ta film with a thickness between about 2 nm and 5 nm. The adhesive layer may be deposited using a suitable PVD technique and/or any other suitable deposition technique for depositing metals. In some embodiments, step 1110 may be omitted from the manufacturing method example 1100.

In 1120, a metal nitride layer may be fabricated on the adhesion layer. Fabricating the metal nitride layer may involve depositing a metal nitride layer that is non-reactive to the transitional metal oxide in the switching oxide layer fabricated on the bottom electrode. For example, fabricating the metal nitride layer may include depositing a layer of TiN, TaN, etc. using ALD, PVD, reactive sputtering techniques, or any other suitable deposition technique.

In 1130, a metal layer may be fabricated on the metal nitride layer. Fabricating the metal layer may include depositing one or more non-reactive metals described herein. In some embodiments, fabricating the metal layer may include depositing Pt, Pd, Ir, Ru, etc. on the metal nitride layer using PVD techniques or any other suitable deposition techniques. In some embodiments, fabricating the metal layer may include depositing a Pt, Pd, Ir, Ru layer having a thickness between about 3 nm and about 10 nm.

In some embodiments, one or more portions of the adhesion layer, the metal nitride layer, and the metal layer may be selectively removed to fabricate one or more bottom electrodes in 1140. For example, the adhesion layer, the metal nitride layer, and the metal layer may be patterned and etched to fabricate the first bottom electrode 820a and the second bottom electrode 820b as described in conjunction with FIG. 8E.

For simplicity of illustration, the method of the present invention is depicted and described as a series of actions. However, the actions according to the present invention can occur in various orders and/or simultaneously, and with other actions not proposed and described in the present invention. In addition, not all illustrated actions may be required to implement the method according to the invented subject matter. In addition, those skilled in the art will understand and recognize that the method can alternatively be represented as a series of inter-states via state diagrams or events.

As used herein, the terms "approximately," "about," and "substantially" may mean within a normal tolerance range in the art, such as within 2 standard deviations of the mean, within ±20% of a target size in some embodiments, within ±10% of a target size in some embodiments, within ±5% of a target size in some embodiments, within ±2% of a target size in some embodiments, within ±1% of a target size in some embodiments, and within ±0.1% of a target size in some embodiments. The terms "approximately" and "about" may include target sizes. Unless otherwise specified or apparent from the context, all numerical values described herein are modified by the term "about."

As used herein, a range includes all values within the range. For example, a range of 1 to 10 may include any number, combination of numbers, sub-ranges of numbers from 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10, and fractions thereof.

The present invention has been described in many details in the above description. However, it is obvious that the present invention can be implemented without these specific details. In some examples, in order to highlight the content of the present invention, well-known structures and devices are shown in the form of block diagrams rather than specific details.

The terms "first", "second", "third", "fourth", etc. used in this document are used to distinguish different components and may not necessarily have the ordinal meaning of the numerical numbers used.

The words "example" or "exemplary" as used herein refer to serving as an example, instance or illustration. Any aspect or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. On the contrary, the purpose of using the words "example" or "exemplary" is to present the concept in a concrete way. In this application, the term "or" means inclusive "or" rather than exclusive "or". That is, unless otherwise specified or clear from the context, "X includes A or B" means any natural inclusive permutation combination. That is, if X includes A; X includes B; or X includes both A and B, then in any of the above cases, "X includes A or B" is satisfied. In addition, "a" and "an" used in this application and the appended application patent scope should generally be understood as "one or more" unless otherwise specified or the context clearly indicates that it is directed to the singular form. The "one embodiment" or "an embodiment" mentioned in this specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment. Therefore, the phrases "one embodiment" or "an embodiment" appearing in different places in this specification do not necessarily refer to the same embodiment.

As used herein, when an element or layer is referred to as being “on” another element or layer, it can be directly on the other element or layer, or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly on” another element or layer, there are no intervening elements or layers present.

Although it is obvious to a person skilled in the art that additional changes and modifications to the content of the present invention are made after understanding the above description, it should be understood that any specific embodiment shown and described in an illustrative manner should not be considered as limiting. Therefore, the details of the various embodiments are not intended to limit the scope of the patent application, and the scope of the patent application itself only describes the technical features of the invention.

100: cross-switch circuit 111a, 111b, 111i, 111n: row lines 113a, 113b, 113j, 113m: column lines 120a, 120b, 120ij, 120z: cross-point device 200: cross-point device 201: RRAM device 203: transistor 211: bit line 213: select line 215: word line G: gate S: source D: drain 300a, 300b, 330c: RRAM device 310: substrate 320: first electrode 330: switching oxide layer 340: second electrode 335a: conductive channel 335b: interrupt conductive channel 400: non-reactive electrode 410: metal nitride layer 420: metal layer 500: RRAM device 510: adhesive layer 520: first electrode 530: switching oxide layer 540: second electrode 550: interface layer A (ILA) 600: RRAM device 610: adhesive layer 620: first electrode 630: switching oxide layer 640: second electrode 650: interface layer A (ILA) 660: interface layer B (ILB) 700: RRAM device 801: surface 810: substrate 811a, 811b: metal interconnects 820a: first bottom electrode 820b: second bottom electrode 821: adhesive layer 823: metal nitride layer 823a: first metal nitride layer 823b: second metal nitride layer 825: metal layer 825a: first metal layer 825b: second metal layer 821a: first adhesive layer 821b: second adhesive layer 830a, 830b: RRAM stack 900A: characteristic curve 900B: characteristic curve 900C: characteristic curve 1000: manufacturing method example 1010, 1020, 1030, 1040, 1050: steps 1100: Example of manufacturing method 1110, 1120, 1130, 1140: Steps

The present invention will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present invention. However, the accompanying drawings should not be used to limit the present invention to specific embodiments, but only for explanation and understanding. FIG. 1 is a schematic diagram showing an example of a cross-switch circuit according to some embodiments of the present invention. FIG. 2 is a schematic diagram showing an example of a cross-point device according to some embodiments of the present invention. FIG. 3A shows a cross-sectional view of an example RRAM device according to some embodiments of the present invention. FIG. 3B and FIG. 3C respectively show cross-sectional views of the RRAM device in FIG. 3A in a low resistance state and a high resistance state. FIG. 4 shows a cross-sectional view of an example 400 of a compound non-reactive electrode according to another embodiment of the present invention. FIG. 5, FIG. 6 and FIG. 7 show cross-sectional views of example RRAM devices according to some embodiments of the present invention. Figures 8A, 8B, 8C, 8D, 8E and 8F are schematic diagrams of structural cross-sectional views of non-reactive electrodes for manufacturing RRAM devices according to some embodiments of the present invention. Figure 9A shows the I-V (current-voltage) characteristics of the RRAM device according to some embodiments of the present invention; Figure 9B is an I-V curve showing the simulated behavior of the RRAM device according to some embodiments of the present invention; Figure 9C is a diagram showing the device read current characteristics of the example RRAM device over time according to some embodiments of the present invention. Figure 10 is a flow chart showing an example method for manufacturing RRAM devices according to some embodiments of the present invention. Figure 11 is a flow chart showing an example method for manufacturing non-reactive electrodes according to some embodiments of the present invention.

810: Lining

811a, 811b: Metal interconnection

820a: first bottom electrode

820b: Second bottom electrode

823a: First metal nitride layer

823b: Second metal nitride layer

825a: First metal layer

825b: Second metal layer

821a: First adhesive layer

821b: Second adhesive layer

830a, 830b: RRAM stack

Claims (20)

A resistive random access memory (RRAM) device comprises: a first electrode, the first electrode comprises: a metal nitride layer and a metal layer, the metal nitride layer comprises at least one metal nitride, and the metal layer is manufactured on the metal nitride layer; a second electrode, the second electrode comprises a conductive material; and a switching oxide layer, the switching oxide layer is located between the first electrode and the second electrode, the switching oxide layer comprises at least one transitional metal oxide; wherein the metal layer comprises a metal that does not react with the at least one transitional metal oxide; the metal nitride layer and the metal layer have the same width. An RRAM device as described in claim 1, wherein the metal nitride includes at least one of titanium nitride or tantalum nitride. The RRAM device as described in claim 1, wherein the metal that does not react with the at least one transitional metal oxide includes at least one of platinum, palladium, iridium or ruthenium. An RRAM device as described in claim 3, wherein the metal layer is thinner than the metal nitride layer. An RRAM device as described in claim 4, wherein the thickness of the metal layer is between 3nm and 10nm. An RRAM device as described in claim 5, wherein the thickness of the metal nitride layer is between 20nm and 50nm. The RRAM device of claim 1, wherein the at least one transition metal oxide comprises at least one of HfOx or TaOy, wherein x

2.0 and y

2.5. An RRAM device as described in claim 1, wherein the conductive material in the second electrode includes tantalum. The RRAM device as described in claim 1 further comprises: an interface layer located between the switching oxide layer and the second electrode, wherein the interface layer comprises aluminum oxide. The RRAM device as described in claim 1 further comprises: an adhesive layer, the adhesive layer comprising at least one of titanium or tantalum, wherein the metal nitride layer is fabricated on the adhesive layer. A method for manufacturing a resistive random access memory (RRAM) device, comprising: manufacturing a first electrode, comprising: manufacturing a metal nitride layer, wherein the metal nitride layer includes at least one metal nitride; manufacturing a metal layer on the metal nitride layer; manufacturing a switching oxide layer on the first electrode, wherein the switching oxide layer includes at least one transitional metal oxide, wherein the metal layer includes a metal that does not react with the at least one transitional metal oxide; and manufacturing a second electrode on the switching oxide layer, wherein the second electrode includes a conductive material; the metal nitride layer and the metal layer have the same width. A method as described in claim 11, wherein the metal nitride comprises at least one of titanium nitride or tantalum nitride. The method of claim 12, wherein the metal that does not react with the at least one transition metal oxide includes at least one of platinum, palladium, iridium or ruthenium. A method as described in claim 13, wherein the metal layer is thinner than the metal nitride layer. The method as claimed in claim 14, wherein the thickness of the metal layer is between 3nm and 10nm. The method as claimed in claim 15, wherein the thickness of the metal nitride layer is between 20nm and 50nm. The method of claim 11, wherein the at least one transition metal oxide comprises at least one of HfOx or TaOy, wherein x

2.0 and y

2.5. The method as described in claim 11 further comprises: manufacturing an interface layer on the switching oxide layer, wherein the interface layer is located between the switching oxide layer and the second electrode, and the interface layer comprises aluminum oxide. The method of claim 11 further comprises manufacturing an adhesive layer comprising at least one of titanium or tantalum, wherein the metal nitride layer is manufactured on the adhesive layer. A method for manufacturing a non-reactive electrode, comprising: manufacturing an adhesive layer, the adhesive layer comprising at least one of titanium or tantalum; manufacturing a metal nitride layer on the adhesive layer, wherein the metal nitride layer comprises at least one metal nitride, the at least one metal nitride comprising at least one of titanium nitride or tantalum nitride; and manufacturing a metal layer on the metal nitride layer, the metal layer comprising a noble metal; and selectively removing one or more portions of the adhesive layer, the metal nitride layer and the metal layer to manufacture the non-reactive electrode; the metal nitride layer and the metal layer have the same width.