TWI875149B - Optoelectronic semiconductor device - Google Patents

Abstract

An optoelectronic semiconductor device is provided, including: a base; a stack of semiconductor layer located on the base, the stack of semiconductor layer including a second semiconductor structure; an adhesive layer located between the base and the stack of semiconductor layer and the adhesive layer having a flat surface located between the adhesive layer and the stack of semiconductor layer; and a release layer located between the adhesive layer and the base and in direct contact with the base; wherein the release layer includes an inorganic insulating material; wherein the stack of semiconductor layer has a first mesa portion, a second mesa portion and a lower portion, wherein the lower portion locates between the first mesa portion and the second mesa portion and exposes the second semiconductor structure.

Description

Optoelectronic semiconductor components

The present disclosure relates to a photoelectric semiconductor device, and more particularly to a micro photoelectric semiconductor device.

Semiconductor components have a wide range of uses, and the development and research of related materials is also ongoing. For example, III-V semiconductor materials containing group III and group V elements can be applied to various optoelectronic semiconductor components such as light-emitting chips (e.g., light-emitting diodes or laser diodes), light-absorbing chips (photodetectors or solar cells) or non-light-emitting chips (e.g., power components of switches or rectifiers), which can be used in lighting, medical, display, communication, sensing, power supply systems and other fields.

With the advancement of technology, the size of optoelectronic semiconductor components has gradually developed towards miniaturization. In recent years, due to the breakthrough in the size of light-emitting diode (LED) manufacturing, micro-LED displays, which are made by arranging LEDs in arrays, have gradually gained attention in the market. Compared with organic light-emitting diode (OLED) displays, micro-LED displays are more power-saving, have better reliability, longer service life, better contrast performance, and can be visible in sunlight. With the development of technology, there are still many technical research and development needs for optoelectronic semiconductor components. Although existing optoelectronic semiconductor devices have generally met various requirements, they are not satisfactory in all aspects and still need further improvement.

Some embodiments of the present disclosure provide a photoelectric semiconductor element, including a substrate, a semiconductor stack, a bonding layer and a release layer. The semiconductor stack is located on the substrate and includes a second semiconductor structure, the semiconductor stack has a first high platform portion, a second high platform portion and a platform portion, wherein the platform portion is located between the first high platform portion and the second high platform portion and exposes the second semiconductor structure. The bonding layer is located between the substrate and the semiconductor stack and has a flat surface between the bonding layer and the semiconductor stack. The release layer is located between the bonding layer and the substrate and is in direct contact with the substrate, and the release layer includes an inorganic insulating material.

The present disclosure provides a photoelectric semiconductor element, including a substrate, a semiconductor stack and a dissociation layer. The semiconductor stack is located on the substrate and includes a second semiconductor structure, a first high platform portion, a second high platform portion and a platform portion, wherein the platform portion is located between the first high platform portion and the second high platform portion and exposes the second semiconductor structure. The dissociation layer is located between the semiconductor stack and the substrate and has a patterned surface morphology, and the dissociation layer has an energy gap or is an amorphous material.

The present disclosure provides a photoelectric semiconductor element, including a substrate, a semiconductor stack, a bonding layer and a release layer. The semiconductor stack is located on the substrate and includes a second semiconductor structure, a first high platform portion, a second high platform portion and a platform portion, wherein the platform portion is located between the first high platform portion and the second high platform portion and exposes the second semiconductor structure. In addition, the semiconductor stack has a roughened structure facing the substrate. The bonding layer is located between the substrate and the semiconductor stack, and the release layer has a flat surface and is located between the semiconductor stack and the substrate, and the release layer is in direct contact with the substrate.

The following disclosure provides a number of embodiments or examples for implementing different elements of the subject matter provided. Specific examples of each element and its configuration are described below to simplify the description of the disclosed embodiments. Of course, these are merely examples and are not intended to limit the disclosed embodiments. For example, if the description refers to a first element formed on a second element, it may include an embodiment in which the first and second elements are directly in contact, and it may also include an embodiment in which additional elements are formed between the first and second elements so that they are not directly in contact. In addition, the disclosed embodiments may use repeated element symbols in various examples. Such repetition is for the purpose of simplicity and clarity, and is not used to indicate the relationship between the different embodiments and/or configurations discussed.

Furthermore, spatially relative terms such as "below," "below," "below," "above," "above," and similar terms may be used herein to describe the relationship between an element or component and other elements or components as shown in the figures. These spatial terms are intended to include different orientations of the device in use or operation in addition to the orientations shown in the drawings. For example, if the device in the figure is reversed, an element originally described as "below" or "below" other elements or components will be turned "above" other elements or components. Therefore, the exemplary term "below" can have both "above" and "below" orientations. When the device is rotated to other orientations (rotated 90° or other orientations), the spatially relative descriptions used herein can also be interpreted based on the rotated orientation.

Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meanings as those understood by those of ordinary skill in the art to which the present disclosure belongs. It should be understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the present disclosure embodiments.

The composition, dopant and defects of each layer included in the semiconductor device disclosed in the present invention can be analyzed by any suitable method, such as secondary ion mass spectrometer (SIMS), transmission electron microscopy (TEM) or scanning electron microscope (SEM); the thickness of each layer can also be analyzed by any suitable method, such as transmission electron microscopy (TEM) or scanning electron microscope (SEM).

Generally speaking, micro-LEDs can be mass-transferred by laser-liftoff (LLO) process to separate the semiconductor stack of the micro-LED from the substrate. A sacrificial layer is required between the semiconductor stack and the substrate in the micro-LED. Since a high temperature process (e.g., 300°C to 500°C) is required to form an ohmic contact structure during the micro-LED manufacturing process, the sacrificial layer needs to be a material that can undergo a laser lift-off process and withstand high temperature processes. Conventional technologies generally use semiconductor materials (e.g., GaN) or organic materials (e.g., benzocyclobutene (BCB)) to bond the semiconductor stack to the substrate and serve as a release layer for the subsequent laser liftoff (LLO) process.

However, when the release layer is a semiconductor material, epitaxial defects are often generated during the crystal growth period, resulting in a low yield rate of the bonding process; and when the release layer is an organic material, it often cannot withstand high temperatures, resulting in a low yield rate of the high-temperature alloy process. According to some embodiments of the present disclosure, the release layer formed by the inorganic insulating material can be subjected to the laser stripping process and can withstand the high-temperature process. In addition, no epitaxial defects are generated, so the yield rate of the bonding process can be improved, thereby improving the light-emitting efficiency of the optoelectronic semiconductor device.

Referring to FIG. 1A and FIG. 1B , FIG. 1A is a top view of a photoelectric semiconductor device according to an embodiment of the present disclosure, and FIG. 1B is a cross-sectional view of the photoelectric semiconductor device 10 along the line segment A-A′ of FIG. 1A . In this embodiment, the photoelectric semiconductor device 10 includes a substrate 100, a release layer 200, a bonding layer 300, and a semiconductor stack 400. As shown in FIG. 1B , the semiconductor stack 400 is located on the substrate 100 , the bonding layer 300 is located between the semiconductor stack 400 and the substrate 100 , and the release layer 200 is located between the bonding layer 300 and the substrate 100 and directly contacts the substrate 100 . In other words, the semiconductor stack 400 and the substrate 100 are bonded to each other via the bonding layer 300 and the release layer 200 .

It should be understood that when forming the optoelectronic semiconductor element 10, a semiconductor stack 400 is first formed on another growth substrate (not shown) by, for example, metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), liquid-phase epitaxy (LPE), vapor phase epitaxy (VPE), or other suitable epitaxial growth processes, and then the growth substrate is inverted and bonded to the base 100 through the bonding layer 300, and then the growth substrate is removed. Therefore, in various embodiments of the present disclosure, the upper and lower order of the elements in various schematic diagrams does not represent the actual formation order.

In some embodiments, as shown in FIG. 1B , the semiconductor stack 400 includes a first semiconductor structure 410, a second semiconductor structure 420, and an active region 430, wherein the active region 430 is located between the first semiconductor structure 410 and the second semiconductor structure 420. The semiconductor stack 400 can be divided into a first plateau portion 400A, a second plateau portion 400C, a first platform portion 400B, a second platform portion 400D, and a third platform portion 400E. The first platform portion 400B is located between the first platform portion 400A and the second platform portion 400C, the second platform portion 400D and the third platform portion 400E are located on opposite sides of the first platform portion 400B, the first platform portion 400A is located between the first platform portion 400B and the second platform portion 400D, and the second platform portion 400C is located between the first platform portion 400B and the third platform portion 400E. From a top view, the first platform portion 400A and the second platform portion 400C are surrounded by the platform portion (e.g., the first platform portion 400B, and/or the second platform portion 400D, and/or the third platform portion 400E), and the first platform portion 400B is surrounded by the first platform portion 400A and the second platform portion 400C. The top surface 400a1 of the first high platform portion 400A and the top surface 400a1 of the second high platform portion 400C are coplanar, and the top surface 400a2 of the first platform portion 400B is lower than the active region 430. The thickness of the high platform portions 400A and 400C is greater than the thickness of the platform portions 400B, 400D, and 400E. In other embodiments, the second semiconductor structure 420 has a lower surface 420a away from the first semiconductor structure 410, and the lower surface 420a has a roughening structure (not shown), and the roughening structure can be regular roughening or irregular roughening, thereby increasing the light extraction efficiency of the optoelectronic semiconductor device 10.

In some embodiments, the substrate 100 is a transparent material. The term "transparent" herein refers to a material having a high transmittance for the wavelength used in the subsequent laser stripping process. Specifically, the substrate 100 has a transmittance of 80% to 99.99% for a wavelength of 200nm to 700nm, for example, a transmittance greater than 95%. The substrate 100 may be sapphire, glass, epoxy, quartz, acrylic resin, or other transparent materials. In another embodiment, the substrate 100 is sapphire. In one embodiment, the substrate 100 has a first upper surface 100a facing the semiconductor stack 400, the bonding layer 300 includes a second upper surface 300a facing the semiconductor stack 400, the first upper surface 100a includes a patterned pattern (not shown), so that the release layer 200 can have a corresponding surface morphology according to the patterned pattern of the substrate 100, and the second upper surface 300a is a flat surface. The flat second upper surface 300a can increase the adhesion between the semiconductor stack 400 and the substrate 100.

The optoelectronic semiconductor element 10 may be a micro light emitting diode (Micro LED), and has a length L and a width W in the top view (FIG. 1A). In other words, the semiconductor stack 400 (or the second semiconductor structure 420) has a length L and a width W. The length L is not greater than 150 microns, for example, 20 microns to 150 microns, for example, 20 microns to 60 microns, 60 microns to 150 microns. The width W is not greater than 100 microns, for example, 10 microns to 100 microns, for example, 10 microns to 30 microns, 30 microns to 75 microns.

The debonding layer 200 is an inorganic insulating material that can withstand subsequent high-temperature processes (350°C to 500°C) and has a band gap between 3eV and 6eV, for example, 3.5 eV to 5.5eV, 4eV to 5.2eV, so that the debonding layer 200 has a high absorption rate for the UV light band (for example, 200nm to 400nm) used in the laser stripping process, so as to effectively separate the substrate 100 and the semiconductor stack 400, and does not cause damage to the semiconductor stack 400 during the separation process, thereby improving the process yield. Specifically, the dissociation layer 200 material may have an absorption coefficient greater than or equal to 10 ² cm ^-1 , such as 1×10 ² cm ^-1 to 1×10 ⁵ cm ^-1 , for a wavelength of 200 nm to 300 nm. In the present embodiment, the dissociation layer 200 may be silicon nitride (SiN _x ), aluminum nitride (AlN), silicon oxynitride (SiNO), or indium tin oxide glass (ITO) or a combination thereof. In some embodiments, the dissociation layer 200 may be an amorphous material.

In some embodiments, as shown in FIG. 1B , the release layer 200 has a thickness T ranging from 30Å to 1000Å, such as 50Å to 500Å, 60Å to 300Å, or 80Å to 200Å. If the thickness T of the release layer 200 is less than 30Å, it may be difficult to control the uniformity of the process, resulting in a lower bonding yield. If the thickness T of the release layer 200 is greater than 1000Å, it may result in an inability to effectively separate the semiconductor stack 400 from the substrate 100 in the subsequent separation process, and after the laser stripping process, there may be a portion of the residual release layer 200 on the semiconductor stack 400, thereby causing damage to the device and affecting the yield.

In some embodiments, since the dissociation layer 200 disclosed herein is an inorganic insulating material, the dissociation layer 200 can be formed on the substrate 100 by a deposition process, and the aforementioned problem of epitaxial defects caused when the dissociation layer is a semiconductor material, which leads to a lower yield of the bonding process, can be avoided. The above-mentioned deposition process is, for example, chemical vapor deposition (CVD), subatmospheric CVD (SACVD), flowable CVD (FCVD), spin coating, and/or other suitable processes.

In some embodiments, the first semiconductor structure 410 and the second semiconductor structure 420 may be doped by in-situ doping during epitaxial growth and/or by implanting the dopant after epitaxial growth. The first semiconductor structure 410 may include a first dopant to have a first conductivity type, and the second semiconductor structure 420 may include a second dopant to have a second conductivity type. The first semiconductor structure 410 and the second semiconductor structure 420 have different conductivity types, that is, the first conductivity type is different from the second conductivity type. The first conductivity type is, for example, p-type and the second conductivity type is, for example, n-type, or the first conductivity type is, for example, n-type and the second conductivity type is, for example, p-type. When the optoelectronic semiconductor device is a light-emitting device, in operation, the first semiconductor structure 410 and the second semiconductor structure 420 provide holes and electrons, or provide electrons or holes, respectively, to be combined in the active region 430 to emit light. In one embodiment, the first dopant or the second dopant may be magnesium (Mg), zinc (Zn), silicon (Si), carbon (C), or tellurium (Te).

In the disclosed embodiment, the first semiconductor structure 410, the second semiconductor structure 420, and the active region 430 may include III-V semiconductor materials, such as aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P), or indium (In). Specifically, in the disclosed embodiment, the III-V semiconductor materials may be binary compound semiconductors (such as GaAs, GaP, or GaN), ternary compound semiconductors (such as InGaAs, AlGaAs, InGaP, AlInP, InGaN, or AlGaN), or quaternary compound semiconductors (such as AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaAsN, or AlGaAsP).

In the disclosed embodiment, the semiconductor stack 400 may include a multi-quantum well structure (MQWs) (not shown) to emit infrared light with a peak wavelength of 700 nm to 1700 nm or red light with a peak wavelength of 610 nm to 700 nm, blue light or deep blue light with a peak wavelength between 400 nm and 490 nm, or green light with a peak wavelength between 490 nm and 550 nm.

In this embodiment, the optoelectronic semiconductor device 10 further includes an intermediate structure 900 located between the semiconductor stack 400 and the bonding layer 300. The intermediate structure 900 can be used to optimize the adhesion between the semiconductor stack 400 and the bonding layer 300, and/or increase the probability of light from the semiconductor stack 400 to the substrate 100 being reflected back away from the substrate 100. The material of the intermediate structure 900 can be a conductive material or a non-conductive material. Specifically, the intermediate structure 900 can be an inorganic insulating material (e.g., silicon nitride ( _SiNx ), silicon oxide ( _SiO2 ) etc.), transparent conductive materials (e.g., indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO) or indium zinc oxide (IZO)). In one embodiment, the intermediate structure 900 includes a Bragg reflector structure (DBR), which is formed by alternately stacking two or more materials with different refractive indices. In this embodiment, the intermediate structure 900 and the debonding layer 200 have the same material, and the thickness of the intermediate structure 900 is greater than the thickness of the debonding layer 200.

As described above, although the semiconductor stack 400 is shown in FIG. 1B as being located above the substrate 100, in one embodiment, the semiconductor stack 400 and the bonding layer 300 are actually first formed on another growth substrate (not shown) and then invertedly bonded to the substrate 100. In other words, the first semiconductor structure 410, the active region 430, the second semiconductor structure 420, the intermediate structure 900 and a portion of the bonding layer 300 are sequentially formed on the growth substrate, and the release layer 200 and another portion of the bonding layer 300 are formed on the substrate 100, and then the substrate 100 and the semiconductor stack 400 are connected by bonding the bonding layers 300 on both sides, and then the growth substrate is removed.

After the semiconductor stack 400 is connected to the substrate 100 through the bonding layer 300 and the release layer 200, a portion of the semiconductor stack 400 can be etched by an etching process to expose the second semiconductor structure 420 for subsequent electrical connection. The etching process can be, for example, a dry etching process, a wet etching process, or a combination thereof. For example, the dry etching process can include plasma etching (PE), reactive ion etching (RIE), and inductively coupled plasma reactive ion etching (ICP-RIE); the wet etching process can use an acidic solution or an alkaline solution. In addition, the above etching process defines the semiconductor stack 400 into a platform portion (400B, 400D, and 400E) and a plateau portion (400A and 400C), the platform portions 400B, 400D, and 400E only include the second semiconductor structure 420, and the plateau regions 400A and 400C include the first semiconductor structure 410, the active region 430, and the second semiconductor structure 420. In this embodiment, the width of the semiconductor stack 400 is smaller than that of the substrate 100, and a portion of the intermediate structure 900 is exposed. In other words, the semiconductor stack 400 does not cover a portion of the intermediate structure 900. In other embodiments, a portion of the intermediate structure 900, the bonding layer 300 or the release layer 200 may be removed by the etching process to expose a portion of the bonding layer 300, the release layer 200 or the substrate 100.

Continuing to refer to FIG. 1B , the optoelectronic semiconductor device 10 selectively includes an insulating layer 500, and the insulating layer 500 conformably covers the semiconductor stack 400 to protect the semiconductor stack 400. The insulating layer 500 has a first opening 510 and a second opening 520 on the first high platform portion 400A and the first platform portion 400B of the semiconductor stack 400, respectively. In the embodiment disclosed herein, the insulating layer 500 may include an oxide insulating material, a non-oxide insulating material, or a combination thereof. For example, the oxide insulating material may include silicon oxide (SiO _x ); the non-oxide insulating material may include silicon nitride (SiN _x ), benzocyclobutene (BCB), cycloolefin copolymer (COC) or fluorocarbon polymer, calcium fluoride (CaF ₂ ) or magnesium fluoride (MgF ₂ ). In one embodiment, the insulating layer 500 may have a reflective function and include a distributed bragg reflector structure (DBR), which is formed by alternately stacking two or more semiconductor materials with different refractive indices, such as silicon nitride ( _SiNx ), aluminum oxide ( _AlOx ), silicon oxide ( _SiOx ), magnesium fluoride ( _MgFx ), titanium oxide ( _TiO2 ) or _niobium oxide ( _Nb2O5 ).

Continuing to refer to FIG. 1B , the optoelectronic semiconductor device 10 selectively includes a first contact structure 610 and a second contact structure 620. The first contact structure 610 and the second contact structure 620 may be respectively located in the first opening 510 and the second opening 520 of the insulating layer 500. In this embodiment, the first contact structure 610 has a first width W1, and the second contact structure 620 has a second width W2 greater than or equal to the first width W1. The width W3 of the first opening 510 is greater than the first width W1. Therefore, when the first contact structure 610 is located on the first semiconductor structure 410, a portion of the top surface 400a1 of the semiconductor stack 400 is exposed, that is, a portion of the top surface 400a1 of the semiconductor stack 400 is not covered by the first contact structure 610. Similarly, The width W4 of the second opening 520 is greater than the second width W2, so when the second contact structure 620 is located on the second semiconductor structure 420, a portion of the top surface 400a2 of the semiconductor stack 400 will be exposed, that is, a portion of the top surface 400a2 of the semiconductor stack 400 will be exposed and not covered by the second contact structure 620. The first contact structure 610 directly contacts and is electrically connected to the first semiconductor structure 410, and the second contact structure 620 directly contacts and is electrically connected to the second semiconductor structure 420. The first contact structure 610 and the second contact structure 620 may form ohmic contacts with the first semiconductor structure 410 and the second semiconductor structure 420 respectively, thereby reducing the forward voltage (Vf) of the optoelectronic semiconductor device 10.

The first opening 510 and the second opening 520 can be formed by etching a portion of the insulating layer 500 through an etching process, and the first opening 510 and the second opening 520 respectively expose the first contact structure 610 and a portion of the first semiconductor structure 410, the second contact structure 620 and the second semiconductor structure 420. The etching process can be a dry etching process or a wet etching process. In the disclosed embodiment, the first contact structure 610 and the second contact structure 620 can each include a metal material, an alloy material, a metal oxide material, etc. The metal material may be a metal material such as germanium (Ge), benzium (Be), zinc (Zn), gold (Au), nickel (Ni) or copper (Cu); the alloy material may include an alloy of at least two of the above metals, such as germanium gold nickel (GeAuNi), benzium gold (BeAu), germanium gold (GeAu), or zinc gold (ZnAu); the metal oxide material may include indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO) or indium zinc oxide (IZO), etc. In one embodiment, the first contact structure 610 and the second contact structure 620 are GeAu alloy and BeAu alloy respectively.

The first opening 510 and the second opening 520 may have the same or different shapes, and the first contact structure 610 and the second contact structure 620 may also have the same or different shapes, such as circular, square or polygonal. The shape of the first opening 510 and the shape of the first contact structure 610 may be selected to be the same or different shapes, and/or the shape of the second opening 520 and the shape of the second contact structure 620 may be selected to be the same or different shapes.

1B , the optoelectronic semiconductor device 10 includes a first electrode 710 and a second electrode 720. The first electrode 710 is located on the insulating layer 500 and the first contact structure 610, and is electrically connected to the first semiconductor structure 410 through the first contact structure 610, and the first electrode 710 covers a portion of the top surface 400a1 of the semiconductor stack 400; the second electrode 720 conformingly covers the insulating layer 500 and the second contact structure 620, and is electrically connected to the second semiconductor structure 420 through the second contact structure 620, and the second electrode 720 completely covers the top surface 400a2 of the semiconductor stack 400. In this embodiment, the top surface 710a of the first electrode 710 and the top surface 720a of the second electrode 720 located on the first high platform portion 400A and the second high platform portion 400C are coplanar. The first electrode 710 and the second electrode 720 can be used to electrically connect the optoelectronic semiconductor element 10 to an external power source. The current can be conducted in the optoelectronic semiconductor element 10 through the first electrode 710 and the second electrode 720, and drive the carriers (electrons and holes) in the semiconductor stack 400 to recombine and emit light, and the light can be emitted toward the substrate 100 or emitted in a direction away from the substrate 100.

In the disclosed embodiment, the materials of the first electrode 710 and the second electrode 720 may be the same or different, and may each include a metal oxide material, a metal or an alloy. The metal oxide material includes, for example, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO) or indium zinc oxide (IZO). The metal may be germanium (Ge), benzium (Be), zinc (Zn), gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), nickel (Ni), indium (In), tin (Sn), silver (Ag) or copper (Cu). The alloy may include at least two selected from the group consisting of the above metals, such as gold-tin (AuSn), tin-silver-copper alloy, tin alloy, gold-indium (AuIn), germanium-gold-nickel (GeAuNi), benzium-gold (BeAu), germanium-gold (GeAu), zinc-gold (ZnAu).

In some embodiments, the first electrode 710 and the second electrode 720 may be formed by a deposition process, which will not be described in detail herein. In one embodiment, a planarization process (e.g., a chemical mechanical planarization (CMP) process) may be performed to make the top surface 710a of the first electrode 710 and the top surface 720a of the second electrode 720 coplanar, so as to provide a flat surface so that the first electrode 710 and the second electrode 720 can be connected to an external circuit at the same level, thereby improving yield and reliability.

FIG. 2 is a cross-sectional view of a photoelectric semiconductor device 20 according to another embodiment of the present disclosure. The photoelectric semiconductor device 20 has a structure similar to that of the photoelectric semiconductor device 10 (FIG. 1B), except that the photoelectric semiconductor device 20 has a reflective layer 800 located between the semiconductor stack 400 and the release layer 200. Specifically, the reflective layer 800 is located between the bonding layer 300 and the release layer 200. The reflective layer 800 can reflect the light emitted by the active region 430, so that the light is emitted out of the photoelectric semiconductor device 20 in a direction away from the substrate 100, thereby improving the light emission efficiency. In the disclosed embodiment, the reflective layer 800 may include semiconductor materials, such as III-V semiconductor materials; metal materials, including but not limited to copper (Cu), aluminum (Al), tin (Sn), gold (Au), or silver (Ag); or alloy materials thereof. In other embodiments, the reflective layer 800 may also include a distributed bragg reflector structure (DBR), which is formed by alternately stacking two or more semiconductor materials or insulating materials with different refractive indices, such as AlAs/GaAs, AlGaAs/GaAs, InGaP/GaAs, SiO ₂ /TiO ₂ . In some embodiments, after forming the release layer 200 on the substrate 100, the reflective layer 800 is formed on the release layer 200, and then the semiconductor stack 400 is connected to the substrate 100 by bonding the reflective layer 800 and the adhesive layer 300; or, the adhesive layer 300 and the reflective layer 800 are sequentially formed on the semiconductor stack 400, and the release layer 200 is formed on the substrate 100, and then the semiconductor stack 400 is connected to the substrate 100 by bonding the reflective layer 800 and the release layer 200.

FIG. 3A is a top view of a photoelectric semiconductor device according to another embodiment of the present disclosure. FIG. 3B is a cross-sectional view along the line segment A-A' in FIG. 3A. The photoelectric semiconductor device 30 has a structure similar to that of the photoelectric semiconductor device 20 (FIG. 2), but the difference is that the photoelectric semiconductor device 30 does not have the second platform portion 400D and the third platform portion 400E.

As shown in FIG. 3A and FIG. 3B , the semiconductor stack 400 can be divided into a first high platform portion 400A, a second high platform portion 400C, and a first platform portion 400B. The first platform portion 400B is located between the first high platform portion 400A and the second high platform portion 400C. The first high platform portion 400A and the second high platform portion 400C are respectively located on opposite sides of the first platform portion 400B. Compared with the optoelectronic semiconductor device 20 of the embodiment shown in FIG. 2 , since the present embodiment does not have the second platform portion 400D and the third platform portion 400E, the device area can be further reduced to obtain a smaller optoelectronic semiconductor device 30.

In summary, the optoelectronic semiconductor device disclosed herein provides a release layer 200 that has high tolerance to high temperature processes, has no epitaxial defects, and can be used in a subsequent laser stripping process. Specifically, the release layer 200 disclosed herein is an inorganic insulating material, which can effectively remove the substrate 100 through a laser stripping process without damaging the optoelectronic semiconductor device, thereby improving the process yield.

The above summarizes the components of several embodiments so that those with ordinary knowledge in the art to which the present disclosure belongs can more easily understand the perspectives of the embodiments of the present disclosure. Those with ordinary knowledge in the art to which the present disclosure belongs should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purpose and/or advantages as the embodiments introduced herein. Those with ordinary knowledge in the art to which the present disclosure belongs should also understand that such equivalent processes and structures do not violate the spirit and scope of the present disclosure, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present disclosure.

10: Photoelectric semiconductor element 20: Photoelectric semiconductor element 30: Photoelectric semiconductor element 100: Substrate 100a: First upper surface 200: Debonding layer 300: Adhesive layer 300a: Second upper surface 400: Semiconductor stack 400a1: Top surface 400a2: Top surface 400A: First platform 400B: First platform 400C: Second platform 400D: Second platform 400E: Third platform 410: First semiconductor structure 420: Second semiconductor structure 430: Active region 500: Insulating layer 510: First opening 520: Second opening 610: first contact structure 620: second contact structure 710: first electrode 710a: top surface 720: second electrode 720a: top surface 800: reflective layer 900: intermediate structure L: length T: thickness W: width AA’: line segment W1: first width W2: second width W3, W4: width

The disclosed embodiments are best understood by the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale and are for illustration purposes only. In fact, the sizes of the various components may be arbitrarily enlarged or reduced to clearly illustrate the features of the disclosed embodiments. FIG. 1A is a top view of a photoelectric semiconductor component according to an embodiment of the disclosed embodiment. FIG. 1B is a cross-sectional view along the line segment A-A’ in FIG. 1A according to an embodiment of the disclosed embodiment. FIG. 2 is a cross-sectional view of a photoelectric semiconductor component according to another embodiment of the disclosed embodiment. FIG. 3A is a top view of a photoelectric semiconductor component according to yet another embodiment of the disclosed embodiment. FIG. 3B is a cross-sectional view along the line segment A-A’ in FIG. 3A according to another embodiment of the present disclosure.

10: Optoelectronic semiconductor components

100: Base

100a: first upper surface

200: Decomposition layer

300: Adhesive layer

300a: Second upper surface

400:Semiconductor stacking

400a1: Top surface

400a2: Top surface

400A: First platform

400B: First platform department

400C: Second high platform

400D: Second platform section

400E: Third platform department

410: First semiconductor structure

420: Second semiconductor structure

430: Active zone

500: Insulation layer

510: First opening

520: Second opening

610: First contact structure

620: Second contact structure

710: First electrode

710a: top surface

720: Second electrode

720a: Top surface

900: Middle structure

T:Thickness

AA’: line segment

W1: First width

W2: Second width

W3, W4: Width

Claims (10)

A photoelectric semiconductor element comprises: a substrate; a semiconductor stack located on the substrate, the semiconductor stack comprising a second semiconductor structure; a bonding layer located between the substrate and the semiconductor stack and having a flat surface between the bonding layer and the semiconductor stack; and a release layer located between the bonding layer and the substrate and in direct contact with the substrate; wherein the release layer comprises an inorganic insulating material; wherein the semiconductor stack has a first high platform portion, a second high platform portion and a platform portion, wherein the platform portion is located between the first high platform portion and the second high platform portion and exposes the second semiconductor structure. A photoelectric semiconductor element comprises: a substrate; a semiconductor stack located on the substrate, the semiconductor stack comprising a second semiconductor structure; and a debonding layer located between the semiconductor stack and the substrate and having a patterned surface morphology; wherein the debonding layer has an energy gap or is an amorphous material; wherein the semiconductor stack has a first high platform portion, a second high platform portion and a platform portion, wherein the platform portion is located between the first high platform portion and the second high platform portion and exposes the second semiconductor structure. A photoelectric semiconductor element comprises: a substrate; a semiconductor stack located on the substrate, the semiconductor stack comprising a second semiconductor structure and having a roughened structure facing the substrate; a bonding layer located between the substrate and the semiconductor stack; and a release layer having a flat surface and located between the semiconductor stack and the substrate, and the release layer is in direct contact with the substrate; wherein the semiconductor stack has a first high platform portion, a second high platform portion and a platform portion, wherein the platform portion is located between the first high platform portion and the second high platform portion and exposes the second semiconductor structure. The optoelectronic semiconductor device of claim 1, 2 or 3 further comprises a first contact structure located on the first high platform portion and a second contact structure located on the platform portion. The optoelectronic semiconductor element of claim 1, 2 or 3 further includes an intermediate structure located between the semiconductor stack and the desorption layer, and the intermediate structure is an inorganic insulating material or a transparent conductive material. A photoelectric semiconductor device as claimed in claim 5, wherein the intermediate structure and the debonding layer have the same material. The optoelectronic semiconductor device of claim 1, 2 or 3 further comprises a reflective layer located between the semiconductor stack and the debonding layer. The optoelectronic semiconductor element of claim 1, 2 or 3 further includes an insulating layer located on the semiconductor stack and having a first opening located on the first high platform portion and a second opening located on the platform portion. The optoelectronic semiconductor element of claim 8 further includes a first electrode and a second electrode respectively disposed in the first opening and the second opening, and the second electrode covers the platform portion and a portion of the second high platform portion. A photoelectric semiconductor element as claimed in claim 9, wherein the first electrode has a first top surface, and the second electrode has a second top surface coplanar with the first top surface.