TWI871691B - Semiconductor structure and method for manufacturing the same - Google Patents

Abstract

A semiconductor structure includes a substrate, a dielectric layer, and a capacitor structure. The dielectric layer is disposed on the substrate. The dielectric layer has a trench. The capacitor structure is located in the trench of the dielectric layer. The trench has a first width and a second width. The first width is a maximum width of the trench. The second width is the width of the trench at a top surface of the dielectric layer. A difference between a first width and the second width is smaller than 2 nanometers.

Description

Semiconductor structure and method for manufacturing the same

The present disclosure relates to a semiconductor structure and a method for manufacturing the same, and in particular to a dynamic random access memory structure.

With the development of the semiconductor industry, the critical dimensions of semiconductor components are shrinking rapidly. The density of components in integrated circuits is increasing. The error requirements for capacitor array manufacturing are becoming more stringent. In a high aspect ratio columnar capacitor structure, even a slight difference in the width of the trench that holds the capacitor structure will seriously affect the yield of the capacitor array.

In view of this, how to propose a semiconductor structure and a manufacturing method that can solve the above problems is one of the problems that the industry is eager to invest research and development resources to solve.

One technical aspect of the present disclosure is a semiconductor structure.

In one embodiment, the semiconductor structure includes a substrate, a dielectric layer, and a capacitor structure. The dielectric layer is disposed on the substrate. The dielectric layer has a trench. The capacitor structure is located in the trench of the dielectric layer. The trench has a first width and a second width, the first width is the maximum width of the trench, and the second width is the width of the trench on the upper surface of the dielectric layer. The difference between the first width and the second width is less than 2 nanometers.

In one embodiment, the dielectric layer includes an oxide layer and a nitride layer. The oxide layer is located above the substrate. The nitride layer is located above the oxide layer. The oxide layer and the nitride layer together form a trench sidewall, and the trench sidewall surrounds the capacitor structure.

In one embodiment, the dielectric layer has a first position, the trench has a first width at the first position, and the first position is located at one end of the oxide layer close to the nitride layer.

In one embodiment, the dielectric layer has a second position, the trench has a second width at the second position, and the second position is located at an end of the nitride layer far from the oxide layer.

Another technical aspect of the present disclosure is a semiconductor structure.

In one embodiment, a method for manufacturing a semiconductor structure includes patterning a dielectric layer on a substrate to form an opening; forming a capping layer on the dielectric layer and in the opening; etching the capping layer and the dielectric layer to deepen the opening into a trench; and forming a capacitor structure in the trench.

In one embodiment, the dielectric layer includes an oxide layer and a nitride layer located above the oxide layer, wherein the step of patterning the dielectric layer located on the substrate to form an opening further includes making the opening penetrate the nitride layer, and the depth of the opening is less than the thickness of the dielectric layer.

In one embodiment, the step of forming a capping layer on the dielectric layer and in the opening further includes forming the capping layer to cover the oxide layer around the opening.

In one embodiment, patterning the dielectric layer on the substrate to form the opening further includes making the distance from the lower surface of the nitride layer to the bottom of the opening range from 100 nm to 400 nm.

In one embodiment, the step of forming the capping layer on the dielectric layer and in the opening is performed by an atomic layer deposition process.

In one embodiment, the step of etching the capping layer and the dielectric layer to deepen the opening into a trench further includes providing the trench with a first width and a second width, wherein the first width is the maximum width of the trench, the second width is the width of the trench on the upper surface of the dielectric layer, and the difference between the first width and the second width is less than 2 nanometers.

In the above-mentioned embodiments, the semiconductor device disclosed herein can reduce the difference between the first width and the second width of the trench, thereby reducing the probability of capacitor leakage and improving the yield. In other words, the semiconductor device disclosed herein can reduce the curvature of the trench sidewall of the trench, making the trench closer to vertical. The manufacturing method of the semiconductor device disclosed herein protects the opening sidewall of the opening, especially the oxide layer around the opening in the dielectric layer, by a covering layer, thereby reducing the probability of capacitor leakage and improving the yield.

The following will disclose multiple embodiments of the present invention with drawings. For the purpose of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is to say, in some embodiments of the present invention, these practical details are not necessary. In addition, in order to simplify the drawings, some commonly used structures and components will be depicted in the drawings in a simple schematic manner. And for the sake of clarity, the thickness of the layers and regions in the drawings may be exaggerated, and the same element symbols represent the same elements in the description of the drawings.

FIG. 1 is a schematic diagram of a semiconductor structure 100 according to an embodiment of the present disclosure. FIG. 1 is a cross-sectional view. The semiconductor structure 100 includes a substrate 110, a dielectric layer 120, and a capacitor structure 130. The semiconductor structure 100 is a dynamic random access memory (DRAM) structure.

The dielectric layer 120 is disposed on the substrate 110 along a first direction D1. The first direction D1 is a vertical direction. The dielectric layer 120 has a trench TR. The trench TR penetrates the dielectric layer 120 and exposes the landing pad 112 from the trench TR.

The capacitor structure 130 is located in the trench TR of the dielectric layer 120. The capacitor structure 130 extends in the first direction D1.

For example, the substrate 110 includes silicon, doped silicon, silicon germanium, silicon on insulator, silicon on sapphire, silicon germanium on insulator, silicon carbide, germanium, gallium arsenide, gallium phosphide, gallium arsenide phosphide, indium phosphide, or indium gallium phosphide.

The substrate 110 also includes an active region, an isolation region, and structures such as word lines and bit lines located in the active region. The substrate 110 also includes contacts electrically connecting the word lines and the bit lines. For ease of explanation, the above structural features are omitted in the figure, and only the landing pad 112 (or plug) electrically connected to the capacitor structure 130 is shown as an example.

The dielectric layer 120 includes an oxide layer 122 and a nitride layer 124. The oxide layer 122 is located between the substrate 110 and the nitride layer 124. The nitride layer 124 is located above the oxide layer 122. The material of the oxide layer 122 is silicon oxide, and the material of the nitride layer 124 is silicon nitride.

The trench TR penetrates the oxide layer 122 and the nitride layer 124. The oxide layer 122 and the nitride layer 124 together form a trench sidewall 120S. The trench sidewall 120S surrounds the capacitor structure 130 in the trench TR. The trench sidewall 120S is the interface between the dielectric layer 120 and the capacitor structure 130 in the trench TR.

The trench TR has a first width W1 and a second width W2 along a second direction D2. The second direction D2 is perpendicular to the first direction D1. The second direction D2 is a horizontal direction. The first width W1 is the maximum width of the trench TR. The second width W2 is the width of the trench TR at the upper surface 1242 of the dielectric layer 120. The difference between the first width W1 and the second width W2 is less than 2 nanometers.

The dielectric layer 120 has a first position P1 and a second position P2. The maximum width (first width W1) of the trench TR is located at the first position P1 of the dielectric layer 120, and the second width W2 of the trench TR is located at the second position P2 of the dielectric layer 120. The first position P1 is located at one end of the oxide layer 122 close to the nitride layer 124. The second position P2 is the position of the upper surface 1242 of the nitride layer 124 (equivalent to the upper surface 1242 of the dielectric layer 120), which can also be said that the second position P2 is located at one end of the nitride layer 124 far from the oxide layer 122.

Generally speaking, due to the difference in material properties and the etching process selection ratio, the oxide layer 122 of the dielectric layer 120 is etched to a greater extent at the first position P1. The trench TR accommodating the capacitor structure 130 is more likely to be over-etched at the first position P1, causing the trench TR to present an obvious bow profile or bottle-shaped profile. As a result, the electrical insulation ability between adjacent capacitors will decrease and leakage will occur. Therefore, the semiconductor structure 100 disclosed in the present invention can reduce the difference between the first width W1 and the second width W2 of the trench TR, thereby reducing the probability of capacitor leakage and improving the yield. In other words, the semiconductor structure 100 disclosed herein can reduce the curvature of the trench sidewall 120S of the trench TR, making the trench TR closer to vertical.

The capacitor structure 130 in the trench TR also has a third width W3 and a fourth width W4 along the second direction D2. The third width W3 is the maximum width of the capacitor structure 130. The third width W3 is substantially equal to the first width W1 of the trench TR, and the fourth width W4 is substantially equal to the second width W2 of the trench TR. The difference between the third width W3 and the fourth width W4 is less than 2 nanometers.

Specifically, the actual structure of the capacitor structure 130 and the trench TR is extremely narrow, and the maximum width (first width W1) of the trench TR is near the top of the entire capacitor structure 130 and the trench TR. For example, the first depth DE1 of the trench TR from the upper surface 1242 of the nitride layer 124 to the lower surface 1222 between the oxide layer 122 and the substrate 110 is approximately 1000 nanometers. The distance L3 between the first position P1 and the second position P2 is approximately in the range of 15 nanometers to 30 nanometers. For the convenience of explanation, the proportion of the upper half of the capacitor structure 130 is enlarged in the diagram of the present disclosure to highlight the technical features of the dielectric layer 120 and the capacitor structure 130 of the present invention. The dielectric layer 120 forms a container for accommodating the capacitor structure 130, and the nitride layer 124 has a relatively high strength and can support the narrow and elongated capacitor structure 130 and the trench TR.

The capacitor structure 130 includes a bottom electrode 132, a capacitor insulating layer 134, and a top electrode 136. In the present embodiment, the bottom electrode 132 includes titanium nitride (TiN). In other embodiments, the bottom electrode 132 includes titanium silicon nitride (TiSiN). In the present embodiment, the capacitor insulating layer 134 is a high-k layer including zirconium oxide (ZrO2), helium oxide (HfO2), titanium oxide (TiO2), or a combination thereof. In some embodiments, the top electrode 136 includes titanium nitride. In other embodiments, the top electrode 136 includes titanium silicon nitride (TiSiN). The structures and materials of the various layers of the capacitor structure 130 are not intended to limit the present disclosure.

In the cross-sectional view of FIG. 1 , the trench sidewalls 120S located on both sides of the capacitor structure 130 have a first distance L1 along the second direction D2 at a first position P1, and the first distance L1 is equal to the first width W1. The trench sidewalls 120S located on both sides of the capacitor structure 130 have a second distance L2 along the second direction D2 at a second position P2. The second distance L2 is equal to the second width W2.

It should be understood that the previously described element connection relationship, materials and functions will not be repeated, and are described first. In the following description, the manufacturing method of the semiconductor structure 100 will be described.

FIG. 2 is a flow chart of a method for manufacturing a semiconductor structure 100 according to an embodiment of the present disclosure. FIG. 3 to FIG. 6 are schematic diagrams of intermediate steps of the manufacturing method of FIG. 2.

Refer to FIG. 2 and FIG. 3 at the same time. The manufacturing method of the semiconductor structure 100 starts at step S1. A patterned mask layer 140 is formed on the dielectric layer 120 to define the position of the trench TR (see FIG. 1).

Refer to FIG. 2 and FIG. 4 at the same time. Then, the step S2 of the manufacturing method of the semiconductor structure 100 is performed. The dielectric layer 120 located on the substrate 110 is patterned to form an opening OP. The dielectric layer 120 is etched to form the pattern of the patterned mask layer 140 in the dielectric layer 120 to form the opening OP in the dielectric layer 120.

The opening OP penetrates the nitride layer 124. There is a second depth DE2 between the opening bottom 126 of the opening OP and the upper surface 1242 of the dielectric layer 120 (equal to the upper surface 1242 of the nitride layer 124). The second depth DE2 of the opening OP is less than the thickness T of the dielectric layer 120. In other words, step S2 is to partially etch the dielectric layer 120. The thickness T of the dielectric layer 120 is equal to the first depth DE1. The second depth DE2 of the opening OP is slightly greater than the distance L3 between the first position P1 and the upper surface 1242 of the nitride layer 124. The distance L4 from the lower surface 1244 of the nitride layer 124 to the opening bottom 126 of the opening OP is in the range of 100 nm to 400 nm.

In step S2, the etching step is performed by a plasma etching process. The plasma gas is a fluorine-containing etching gas, such as carbon tetrafluoride ( _CF4 ), hexafluoroethane ( _C2F6 ), octafluorocyclobutane ( _C4F8 ), _{octafluorocyclopentene} ( _C5F8 ) or hexafluoro-1,3-butadiene ( _C4F6 ), but not limited thereto. The plasma etching process has a high selectivity for the oxide layer 122 and the nitride layer ₁₂₄ , _which is _beneficial for etching the oxide layer 122.

The plasma etching process causes the patterned mask layer 140 to have an oblique angle 142. The oblique angle 142 causes ion scattering during the plasma etching process, so that the etching degree of the opening sidewall 128 in the horizontal direction of the second direction D2 increases. If the plasma etching process is continued until the opening OP penetrates the dielectric layer 120, the ions scattered in the opening OP will cause the dielectric layer 120 to be over-etched at the first position P1. Therefore, the plasma etching step is stopped when the second depth DE2 of the opening OP is slightly greater than the distance between the first position P1 and the upper surface 1242 of the nitride layer 124.

Refer to FIG. 2 and FIG. 5 at the same time. Then, the step S3 of the manufacturing method of the semiconductor structure 100 is performed. A capping layer 150 is formed on the dielectric layer 120 and in the opening OP. The step of forming the capping layer 150 is performed by an atomic layer deposition (ALD) process. The material of the capping layer 150 is silicon nitride.

The capping layer 150 covers the patterned mask layer 140 having the bevel 142, the opening bottom 126 of the opening OP, and the opening sidewall 128. In some embodiments, the capping layer 150 can reduce the inclination angle of the bevel 142 or fill the bevel 142, so that the degree of ion scattering during plasma etching is reduced.

Refer to FIG. 2, FIG. 5 and FIG. 6 at the same time. Then, step S4 of the method for manufacturing the semiconductor structure 100 is performed. The cap layer 150 and the dielectric layer 120 are etched to deepen the opening OP into a trench TR. In this step, the plasma etching is continued until the substrate 110 is exposed from the trench TR. The plasma etching step in step S4 is the same as that in step S2.

Refer to Figures 5 and 6 at the same time. The cover layer 150 covering the opening OP is completely etched in step S4. In the step shown in Figure 4, the deposition amount of the cover layer 150 is adjusted so that the cover layer 150 is completely removed when the trench TR is formed in step S4.

In the process of the opening OP being continuously etched and deepened, the plasma etching process has a high selectivity ratio between the capping layer 150 covering the opening OP and the oxide layer 122. Therefore, the capping layer 150 can protect the opening sidewall 128 of the opening OP, especially the oxide layer 122 around the opening OP of the dielectric layer 120. In some embodiments, since the capping layer 150 reduces the degree of ion scattering during the plasma etching process, the etching amount of the opening sidewall 128 of the opening OP in the horizontal direction is reduced, which can prevent the first position P1 of the dielectric layer 120 from being over-etched. Thereby, the trench TR has a first width W1 and a second width W2 at the first position P1 and the second position P2 respectively, and the difference between the first width W1 and the second width W2 is less than 2 nanometers.

In one embodiment, the method can reduce the first width W1 of the trench TR from 36.4 nm to 35.4 nm, and increase the yield from 7.69% to 51.1%. In another embodiment, the method can reduce the first width W1 of the trench TR from 36.4 nm to 36.1 nm, and increase the yield from 7.69% to 39.26%.

Refer to FIG. 1, FIG. 2 and FIG. 6 at the same time. Finally, step S5 is performed to form a capacitor structure 130 in the trench TR. In this step, the remaining patterned mask layer 140 is first removed. Subsequently, the bottom electrode 132, the capacitor insulating layer 134 and the top electrode 136 of the capacitor structure 130 are formed in the trench TR and above the trench TR. The above capacitor structure 130 is only for illustration, and its specific structure can be appropriately adjusted according to needs.

In summary, the semiconductor device disclosed herein can reduce the difference between the first width and the second width of the trench, thereby reducing the probability of capacitor leakage and improving the yield. In other words, the semiconductor device disclosed herein can reduce the curvature of the trench sidewall of the trench, making the trench closer to vertical. The manufacturing method of the semiconductor device disclosed herein protects the opening sidewall of the opening, especially the oxide layer around the opening in the dielectric layer, by a covering layer, thereby reducing the probability of capacitor leakage and improving the yield.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined in the attached patent application.

100:Semiconductor structure

110: Base

112: Landing pad

120: Dielectric layer

120S: Groove side wall

122: Oxide layer

1222: Lower surface

124: Nitride layer

1242: Upper surface

1244: Lower surface

126: Opening bottom

128: Opening side wall

130: Capacitor structure

132: Bottom electrode

134: Capacitor insulation layer

136: Top electrode

140: Patterned mask layer

142: Bevel

150: Covering layer

D1: First direction

D2: Second direction

TR: Groove

W1: First width

W2: Second width

W3: Third width

W4: Fourth width

P1: First position

P2: Second position

L1: First distance

L2: Second distance

L3, L4: distance

OP: Open mouth

DE1: First Depth

DE2: Second Depth

T:Thickness

S1~S5: Steps

FIG. 1 is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. FIG. 2 is a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. FIG. 3 to FIG. 6 are schematic diagrams of intermediate steps of the manufacturing method of FIG. 2.

100: semiconductor structure 110: substrate 112: landing pad 120: dielectric layer 120S: trench sidewall 122: oxide layer 1222: lower surface 124: nitride layer 1242: upper surface 130: capacitor structure 132: bottom electrode 134: capacitor insulating layer 136: top electrode D1: first direction D2: second direction TR: trench W1: first width W2: second width W3: third width W4: fourth width P1: first position P2: second position L1: first distance L2: second distance L3: distance DE1: First Depth

Claims (9)

A semiconductor structure comprises: a substrate; a dielectric layer disposed on the substrate, the dielectric layer having a trench; and a capacitor structure located in the trench of the dielectric layer, the trench having a first width and a second width, the first width being the maximum width of the trench, the second width being the width of the trench on an upper surface of the dielectric layer, the difference between the first width and the second width being less than 2 nanometers, and a width of the trench at an end close to the substrate being less than the first width. A semiconductor structure as described in claim 1, wherein the dielectric layer comprises: an oxide layer located above the substrate; and a nitride layer located above the oxide layer, wherein the oxide layer and the nitride layer together form a trench sidewall, and the trench sidewall surrounds the capacitor structure. A semiconductor structure as described in claim 2, wherein the dielectric layer has a first position, the trench has the first width at the first position, and the first position is located at one end of the oxide layer close to the nitride layer. A semiconductor structure as described in claim 2, wherein the dielectric layer has a second position, the trench has the second width at the second position, and the second position is located at an end of the nitride layer away from the oxide layer. A method for manufacturing a semiconductor structure comprises: patterning a dielectric layer on a substrate to form an opening; forming a capping layer on the dielectric layer and in the opening; etching the capping layer and the dielectric layer to deepen the opening into a trench, wherein the trench has a first width and a second width, the first width being the maximum width of the trench, the second width being the width of the trench at a top end of the dielectric layer, a difference between the first width and the second width being less than 2 nanometers, and a width of the trench at an end close to the substrate being less than the first width; and forming a capacitor structure in the trench. A method for manufacturing a semiconductor structure as described in claim 5, wherein the dielectric layer comprises an oxide layer and a nitride layer located above the oxide layer, wherein the step of patterning the dielectric layer located on the substrate to form the opening further comprises: making the opening penetrate the nitride layer, and the depth of the opening is less than a thickness of the dielectric layer. The method for manufacturing a semiconductor structure as described in claim 6, wherein the step of forming the covering layer on the dielectric layer and in the opening further includes: making the covering layer cover the oxide layer around the opening. The method for manufacturing a semiconductor structure as described in claim 6, wherein the step of patterning the dielectric layer on the substrate to form the opening further includes: making the distance between the lower surface of the nitride layer and the bottom of the opening in the range of 100 nanometers to 400 nanometers. A method for manufacturing a semiconductor structure as described in claim 5, wherein the step of forming the capping layer on the dielectric layer and in the opening is performed by an atomic layer deposition process.

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