TWI868691B - Optimization method and optimization device for integrated circuit layout - Google Patents

Abstract

An optimization method and an optimization device for integrated circuit layout are provided. The optimization method includes: obtaining to-be-optimized routing data defining a target circuit that includes a plurality of differential signal line pairs and a plurality of ground guard traces, each of which includes an initial ground line and a plurality of ground vias; obtaining the differential signal line pairs that meet a strong coupling condition and the corresponding grounding guard traces; for each of the obtained grounding guard traces, remove a part of the ground vias, and replace a part of the ground guard trace where the ground vias are removed from with a modified ground trace segment, so as to generate a plurality of modified ground guard traces; adjusting positions of the differential signal line pairs and the corrected ground guard traces according to a corrected line width; and generating an optimized routing data.

Description

Optimization method and optimization device for integrated circuit layout

The present invention relates to an optimization method and an optimization device, and in particular to an optimization method and an optimization device for integrated circuit layout.

The packaging design of multiple pairs of high-speed signal lines must use limited wiring area and number of layers, and at the same time, it must strike a balance between quality and design cost. Optimized design can be achieved by effectively controlling the electrical quality of high-speed signal lines, the coupling effect between differential signal line pairs, and the width of the ground shield line.

In general, in order to avoid half-wave resonance caused by the ground shield line between high-speed signal pairs, multiple ground vias are set in the ground shield line at a predetermined distance (for example, 1000μm). For specific packaging process specifications, there are certain requirements for the line width of the differential signal line, the line spacing of the differential signal line pair, the distance between the differential signal line and the ground shield line, the line width of the ground shield line, and the size of the ground via on the ground shield line. Such a design can ensure that the crosstalk interference between pairs is within the allowable range, and the distance between the ground via in the ground shield line can also avoid half-wave resonance and affect the high-speed signal.

In contrast, a wiring width that is too large requires a larger wiring area. For high-speed signal lines, it is also necessary to route through through holes to different wiring layers.

The technical problem to be solved by the present invention is to provide an optimization method and an optimization device for integrated circuit layout that can effectively reduce the wiring area in view of the shortcomings of the prior art.

In order to solve the above technical problems, one of the technical solutions adopted by the present invention is to provide an optimization method for integrated circuit layout, including: obtaining wiring data to be optimized, which defines a target circuit, including a circuit board, a plurality of differential signal line pairs arranged in a first wiring layer of the circuit board, and a plurality of ground protection lines arranged between the differential signal line pairs adjacent to each other. The ground protection lines each include an initial ground line and a plurality of ground through holes arranged along the initial ground line with an initial spacing, and the initial ground line has an initial line width for accommodating the ground through holes. The optimization method also includes finding the differential signal line pairs that meet the strong coupling condition and the corresponding ground protection lines; for each of the found ground protection lines, removing a portion of the corresponding ground through holes, and replacing the portion of the initial ground line from which the ground through holes have been removed with a revised ground line segment to generate a plurality of revised ground protection lines, wherein the revised ground line has a revised line width that is smaller than the initial line width; adjusting the positions of the differential signal line pairs and the revised ground protection lines according to the revised line width; and generating optimized wiring data.

In order to solve the above technical problems, another technical solution adopted by the present invention is to provide an optimization device for integrated circuit layout, including a memory and a processor. The memory is configured to store a plurality of computer executable instructions. The processor is electrically coupled to the memory and configured to capture and execute the computer executable instructions to execute an optimization method, which includes: obtaining a wiring data to be optimized, which defines a target circuit, including a circuit board, a plurality of differential signal line pairs arranged in a first wiring layer of the circuit board, and a plurality of ground protection lines arranged between the differential signal line pairs adjacent to each other. The ground protection lines each include an initial ground line and a plurality of ground through-holes arranged along the initial ground line at an initial spacing, and the initial ground line has an initial line width for accommodating the ground through-holes. The optimization method also includes: finding the differential signal line pairs that meet the strong coupling condition and the corresponding ground protection lines; for each of the found ground protection lines, removing a portion of the corresponding ground through-holes, and replacing the portion of the initial ground line from which the ground through-holes have been removed with a revised ground line segment to generate a plurality of revised ground protection lines, wherein the revised ground line has a revised line width that is smaller than the initial line width; adjusting the positions of the differential signal line pairs and the revised ground protection lines according to the revised line width; and generating optimized wiring data.

One of the beneficial effects of the present invention is that the optimization method and optimization device for integrated circuit layout provided by the present invention can remove part of the grounding vias of the grounding shield line that meets the strong coupling condition, reduce the required width of the grounding shield line, and effectively reduce the area occupied by multiple differential signal line pairs without affecting the signal transmission quality.

To further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are only used for reference and description and are not used to limit the present invention.

The following is an explanation of the implementation of the "optimization method and optimization device for integrated circuit layout" disclosed in the present invention through specific concrete embodiments. Those skilled in the art can understand the advantages and effects of the present invention from the contents disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed in various ways based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only for simple schematic illustrations and are not depicted according to actual sizes. Please note in advance. The following implementation will further explain the relevant technical contents of the present invention in detail, but the disclosed contents are not intended to limit the scope of protection of the present invention. In addition, the term "or" used herein may include any one or more combinations of the associated listed items as appropriate.

FIG1 is a functional block diagram of an optimization device for integrated circuit layout according to an embodiment of the present invention. Referring to FIG1 , the present invention provides an optimization device 1 for integrated circuit layout, which includes a memory 10, a processor 11, a network unit 12, a storage unit 13, and an input/output interface 14. The above components can communicate with each other through, for example, but not limited to, a bus 15.

The memory 10 is any storage device for storing data, such as, but not limited to, random access memory (RAM), read only memory (ROM), flash memory, hard disk or other storage devices for storing data. The memory 10 at least stores a plurality of computer readable instructions 100. In one embodiment, the memory 10 can also be used to store temporary data generated when the processor 11 performs operations.

The processor 11 is electrically coupled to the memory 10 and is configured to access the computer readable instructions 100 from the memory 10 to control the components in the optimization device 1 to perform the functions of the optimization device 1 .

The network unit 12 is configured to access the network under the control of the processor 11. The storage unit 13 may be, for example, but not limited to, a disk or an optical disk to store data or instructions under the control of the processor 11. The input/output unit 14 is operable by a user to communicate with the processor 11 to input and output data.

FIG2 is a flow chart of an optimization method for integrated circuit layout according to an embodiment of the present invention. FIG2 provides an optimization method for integrated circuit layout, which can be applied to the optimization device 1 shown in FIG1, or implemented by other hardware components such as a database, a general processor, a computer, a server, or other unique hardware devices with specific logic circuits or devices with specific functions, such as integrating program code and a processor/chip into a unique hardware. In more detail, the optimization method can be implemented using a computer program to control each component of the optimization device 1. The computer program may be stored in a non-transitory computer-readable recording medium, such as a read-only memory, a flash memory, a floppy disk, a hard disk, an optical disk, a flash drive, a tape, a database accessible via a network, or any other computer-readable recording medium having the same function that can be easily imagined by those skilled in the art.

Referring to Figure 2, the optimization method for integrated circuit layout includes the following steps:

Step S200: Obtain wiring data to be optimized. In this step, the wiring data to be optimized may be, for example, an integrated circuit design file 102 defining a target circuit. In some embodiments, the integrated circuit design file 102 may be stored in the memory 10 and accessed by the processor 11, and may include design data of a target circuit consisting of a plurality of different differential signal line pairs, ground protection lines, and signal output pads.

Please refer to FIG. 3 and FIG. 4 , FIG. 3 is a schematic diagram of the layout of the target circuit 3 according to an embodiment of the present invention, and FIG. 4 is an enlarged schematic diagram of part II of FIG. 3 . As shown in FIG. 3 , the target circuit 3 exemplarily includes a circuit board 30, 18 pairs of differential signal line pairs RX0 to RX8 and TX0 to TX8, and a grounding protection line GD disposed between two adjacent differential signal line pairs. For example, as shown in FIG. 4 , a grounding protection line GD is disposed between the differential signal line pairs RX3 and TX3, and a grounding protection line GD is also disposed between the differential signal line pairs RX3 and TX2. The circuit board 30 may, for example, include a plurality of wiring layers, and the differential signal line pairs RX0 to RX8, TX0 to TX8, and the grounding protection line GD may be disposed in the first wiring layer, but the present invention is not limited thereto.

As shown in FIG4 , each ground protection line GD may include an initial ground line GD0 and a plurality of ground vias GV, wherein the ground vias GV are arranged along the initial ground line GD0 with an initial spacing D0 (e.g., 1000 μm), and the initial ground line GD0 has an initial line width GW0 for accommodating the ground vias. It should be noted that the target circuit defined by the wiring data to be optimized must at least have a normal coupling state between the differential signal line pairs and no existing resonance of the ground protection. Taking half-wavelength resonance as an example, when the initial spacing D0 is 1000 μm, the resonance frequency can be calculated according to the following formula (1):

…Formula (1);

Where L is the length between the two ground points, ε _r is the dielectric constant, and C is the speed of light.

From the calculation of formula (1), we can know that the half-wavelength resonance frequency is about 80 GHz. The wiring data to be optimized must at least ensure that the differential signal line pair does not have excessive crosstalk interference near the frequency of 80 GHz.

In order to effectively shrink the area occupied by the differential signal line pairs RX0 to RX8 and TX0 to TX8 without affecting the impedance matching of each differential signal pair, taking the differential signal line pair RX3 as an example, the line width of the differential signal lines RX31 and RX32 in the differential signal line pair RX3 (for example, 20μm), the line spacing between the differential signal lines RX31 and RX32 (for example, 37μm), and the distance between the differential signal line RX31 and the ground guard line GD (40μm) need to remain unchanged. Therefore, the parameter that can be changed is the initial line width GW0 of the ground guard line GD (for example, 97μm). Since the diameter of the ground via GV (e.g., 95 μm) is usually larger than the actual required line width of the ground guard line GD, in order to effectively reduce the wiring area, the initial spacing D0 between the ground vias GV on the ground guard line GD must be conditionally corrected (e.g., extended) or even the ground vias GV must be removed.

Step S201: Find the differential signal line pairs and their corresponding ground protection lines that meet the strong coupling condition. Specifically, based on the thinnest line width that can be achieved under the packaging process stacking condition, the strong coupling condition can be, for example, that the signal line spacing in the differential signal line pair is less than five times the signal line width. In the embodiment of the present invention, the differential signal lines (such as differential signal lines RX31, RX32) are narrower designs under the packaging process conditions and belong to the strongly coupled differential signal line pairs. Under this premise, it can be seen from the electric field distribution that for a differential signal line pair that meets the strong coupling condition, the electromagnetic field will tightly surround the differential signal line, and it is not easy for the electromagnetic field to leak out and affect the adjacent differential signal line pair.

Step S202: For the found ground shield line, a portion of the corresponding ground through hole is removed, and the portion of the initial ground line with the ground through hole removed is replaced with a modified ground line segment to generate a plurality of modified ground shield lines.

Step S203: Adjust the differential signal line pair and correct the position of the ground shield line according to the corrected line width.

Please refer to FIG. 5 to FIG. 7 , FIG. 5 is a schematic diagram of a modified layout of the target circuit 3 according to an embodiment of the present invention, FIG. 6 is an enlarged schematic diagram of part III of FIG. 5 , and FIG. 7 is a detailed flow chart of step S203 .

As shown in FIG5 and FIG6, in the modified ground shield line GD', the portion of the initial ground line GD0 from which the ground via GV has been removed has been replaced by the modified ground line segment GD1, and the modified ground line segment GD1 has a modified line width GW1 that is smaller than the initial line width GW0. Moreover, after effectively reducing the number of ground vias GV on the ground shield line GD, the grounding point on the modified ground shield line GD' can have a modified spacing D1 that is larger than the initial spacing D0, for example, up to 10000 μm. According to formula (1), the second resonance frequency (half-wavelength resonance frequency) corresponding to the modified spacing may occur at 8 GHz. However, since the differential signal line pair meets the strong coupling condition, even if the second resonance frequency is within the operating frequency range of the differential signal line pair, the impact of the ground resonance can still be minimized.

As shown in FIG. 7 , step S203 further includes:

Step S2030: Adjust the positions of the differential signal line pairs and the corresponding corrected ground protection lines according to the predetermined spacing and the corrected line width. It should be noted that in the target circuit before correction, the distance between two adjacent differential signal line pairs and the ground protection line therebetween is a predetermined spacing. For example, there is a ground shield line GD between the differential signal line pair TX4 and RX4, and the differential signal line pair TX4 and RX4 are respectively spaced apart from the ground shield line GD by a predetermined distance D00. In this step, when modifying the layout, the original predetermined distance D00 can be maintained (that is, the predetermined distance D00 is used as the distance between the differential signal line pair and the nearest modified ground line segment GD1), and the original initial ground line segment GD0 is replaced by the modified ground line segment GD1 having a modified line width GW1, and then the overall arrangement of the differential signal line pair can be adjusted.

Step S2031: Reduce the dense wiring area in which the differential signal line pairs that meet the strong coupling condition are arranged in parallel in the parallel direction. As shown in FIG3 , the dense wiring area R1 is divided into three areas, and the differential signal line pairs RX0 to RX8 and TX0 to TX8 are arranged in parallel along the parallel directions Da1, Da2, and Da3, and the parallel directions Da1, Da2, and Da3 are respectively perpendicular to the wiring directions DL1, DL2, and DL3 shared by the differential signal line pairs RX0 to RX8 and TX0 to TX8.

Step S2032: After the dense wiring area is reduced, the signal output pads corresponding to the differential signal line pairs are adjusted to make them consistent in the direction of pad arrangement. As shown in FIG6 , since the modified ground line segment GD1 has a modified line width GW1 that is smaller than the initial line width GW0, the adjusted differential signal line pairs RX0' to RX8', TX0' to TX8' can be arranged in a more dense manner, and the dense wiring area R2 of FIG6 is obviously much smaller than the dense wiring area R1. Therefore, after the dense wiring area R1 of the signal output pad PD in FIG. 3 is reduced to R2, the arrangement of the signal output pad PD can be adjusted (in FIG. 3 , the arrangement direction of the signal output pad PD is not consistent) so that it has consistency in the pad arrangement direction, as shown in the signal output pad PD’ in FIG. 6 .

Please refer to FIG. 8 , which is a schematic cross-sectional view taken along the section line IV-IV of FIG. 6 .

First, as shown in FIG. 8 , the circuit board 30 includes a first wiring layer LL1, a plurality of second wiring layers LL2, and a third wiring layer LL3. Taking the package of an eight-layer board as an example, the differential signal line pair RX5' is mainly designed in the first wiring layer LL1, and the second wiring layers LL2 are arranged below the first wiring layer LL1, and the third wiring layer LL3 is arranged below the second wiring layers LL2. It should be noted that the first wiring layer LL1, the second wiring layer LL2, and the third wiring layer LL3 can all be made of conductive metal materials, and the wiring layers are electrically connected to each other through a plurality of signal vias SV arranged in the middle dielectric layer DR (e.g., glass fiber) or the core layer CR. Based on this architecture, if the original wiring design of Figure 3 is used, the differential signal line pair RX8 will need to have a wiring design other than signal vias SV or pads on other layers.

Please refer to Fig. 9, which is a cross-sectional schematic diagram of the output pad PD' of Fig. 5 according to an embodiment of the present invention. Referring to Fig. 9, since the adjusted signal output pad PD' has consistency in the pad arrangement direction, it is possible to directly electrically connect to the multiple bottom pads BPD' of the third wiring layer LL3 through the multiple signal vias SV corresponding to the second wiring layer LL2 without having a wiring design in the second wiring layer LL2.

Therefore, in the process of modifying the dense wiring area R1 to the dense wiring area R2, it can be seen that the overall length of the differential signal line pair routed along the wiring direction DL2 and arranged in parallel along the parallel direction Da2 changes from the length L1 to the length L2.

Please refer to Table 1 below, which provides an actual example to illustrate the change in overall length before and after optimization: Before optimization After optimization Differential signal line width 20μm 20μm Differential signal line spacing 37μm 37μm Width of grounding wire 97μm 30μm Distance between ground shield and differential signal line 40μm 40μm Number of differential signal line pairs 17 17 Number of grounding wires 16 16 Overall length 4221μm 3149μm

As shown in Table 1, the ground shield line can reduce the line width from 97μm to 30μm by reducing the number of ground vias, and the overall length of the 17 pairs of differential signal lines can be improved by 1072μm.

Please refer to FIG. 2 again, the optimization method enters step S204: generating optimized wiring data. This step is similar to step S200, and the optimized wiring data can be, for example, the integrated circuit design file 102 that defines the modified target circuit.

It should be noted that before generating the optimized wiring data, the optimization device 1 can first execute the simulation tool 104, such as electrical simulation software, to confirm the impact of adjusting the wiring method on the signal.

Please refer to FIG. 10A and FIG. 10B. FIG. 10A is the simulation result of the insertion loss of two pairs of differential signal lines before and after the correction, and FIG. 10B is the simulation result of the reflection loss of two pairs of differential signal lines before and after the correction. In this embodiment, two pairs of differential signal lines RX2, RX2', RX7, and RX7' are selected to compare the difference before and after the modification, and the solid line is the result after the correction, and the dotted line is the result before the correction. As can be seen from the figure, the results of the dotted line and the solid line are very similar, which means that adjusting the width of the ground shield line and the ground via spacing will not significantly affect the quality of the differential signal line itself.

Please refer to FIG. 11A and FIG. 11B , FIG. 11A is the simulated near-end crosstalk interference result of the near-end coupling of two pairs of differential signal lines to the chip end before and after the modification, and FIG. 11B is the simulated near-end crosstalk interference result of the near-end coupling of two pairs of differential signal lines to the ball grid array end before and after the modification. In this embodiment, two pairs of differential signal lines RX2, RX2', RX7, RX7' are also selected to compare the differences before and after the modification, and the solid line is the result after the modification, and the dotted line is the result before the modification. As can be seen from the figure, the coupling between the differential signal line pair TX2/RX2 and the coupling between the differential signal line pair TX7/RX7 are displayed. The width of the ground shield line does affect the coupling between different differential signal line pairs. Although the result of the dotted line is slightly better than that of the solid line, the near-end coupling of both within 10GHz can be controlled below -45dB. For competing for the wiring area of the package, maintaining the quality of the signal itself and properly controlling the crosstalk interference, the optimization method of the present invention can provide a more competitive integrated circuit design. In addition, the second resonance frequency (half-wavelength resonance frequency) corresponding to the modified spacing may occur at 8 GHz. However, since the differential signal line pair meets the strong coupling condition, the impact of ground resonance is minimized.

Please refer to FIG. 12A and FIG. 12B. FIG. 12A is the eye diagram of the differential signal line pair TX1/RX1 of the embodiment of the present invention before modification, and FIG. 12B is the eye diagram of the differential signal line pair TX1/RX1 of the embodiment of the present invention after modification. The quality of the eye diagram before and after modification is compared by using the channel simulation method. As can be seen from the figure, the eye diagram quality is basically completely unaffected by coupling. In other words, after modification through the optimization method provided by the present invention, the wiring area can be saved, and the degree of impact on the electrical quality is very limited.

[Beneficial Effects of Embodiments]

One of the beneficial effects of the present invention is that the optimization method and optimization device for integrated circuit layout provided by the present invention can remove part of the grounding vias of the grounding shield line that meets the strong coupling condition, reduce the required width of the grounding shield line, and effectively reduce the area occupied by multiple differential signal line pairs without affecting the signal transmission quality.

The contents disclosed above are only preferred feasible embodiments of the present invention and are not intended to limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the contents of the specification and drawings of the present invention are included in the scope of the patent application of the present invention.

Optimized device: 1 Memory: 10 Processor: 11 Network unit: 12 Storage unit: 13 Input/output interface: 14 Bus: 15 Computer-readable instructions: 100 Integrated circuit design file: 102 Simulation tool: 104 Circuit board: 30 Differential signal line pair: RX0 to RX8, TX0 to TX8, RX0’ to RX8’, TX0’ to TX8’ Ground shield: GD Ground via: GV Initial spacing: D0 Initial ground line: GD0 Differential signal line: RX31, RX32 Corrected ground line segment: GD1 Corrected line width: GW1 Corrected ground shield: GD’ Predetermined spacing: D00 Parallel direction: Da1, Da2, Da3 Wiring direction: DL1, DL2, DL3 Dense wiring area: R1, R2 First wiring layer: LL1 Second wiring layer: LL2 Third wiring layer: LL3 Dielectric layer: DR Core layer: CR Signal via: SV Output pad: PD, PD’ Bottom pad: BPD’ Length: L1, L2 Part: II, III Section line: IV-IV

FIG. 1 is a functional block diagram of an optimization device for integrated circuit layout according to an embodiment of the present invention.

FIG. 2 is a flow chart of an optimization method for integrated circuit layout according to an embodiment of the present invention.

FIG3 is a schematic diagram showing the layout of a target circuit 3 according to an embodiment of the present invention.

FIG. 4 is an enlarged schematic diagram of part II of FIG. 3 .

FIG5 is a schematic diagram of a modified layout of the target circuit 3 according to an embodiment of the present invention.

FIG. 6 is an enlarged schematic diagram of part III of FIG. 5 .

FIG. 7 is a detailed flow chart of step S203.

FIG. 8 is a schematic cross-sectional view taken along section line IV-IV of FIG. 6 .

FIG. 9 is a schematic cross-sectional view of the output pad of FIG. 5 according to an embodiment of the present invention.

FIG. 10A is a simulation result of insertion loss of two pairs of differential signal lines before and after correction, and FIG. 10B is a simulation result of reflection loss of two pairs of differential signal lines before and after correction.

FIG. 11A is a simulated near-end crosstalk interference result of the near-end coupling of two pairs of differential signal lines at the chip end before and after modification, and FIG. 11B is a simulated near-end crosstalk interference result of the near-end coupling of two pairs of differential signal lines at the ball grid array end before and after modification.

FIG. 12A is an eye diagram of the differential signal line pair TX1/RX1 before modification according to an embodiment of the present invention, and FIG. 12B is an eye diagram of the differential signal line pair TX1/RX1 after modification according to an embodiment of the present invention.

The representative diagram is a flow chart, so it is simply explained without symbols.

Claims (10)

An optimization method for integrated circuit layout, comprising: obtaining a wiring data to be optimized, which defines a target circuit, including: a circuit board; a plurality of differential signal line pairs, arranged in a first wiring layer of a circuit board; and a plurality of ground protection lines, arranged between the differential signal line pairs adjacent to each other, wherein the ground protection lines each include an initial ground line and a plurality of ground through holes arranged along the initial ground line with an initial spacing, the initial ground line having an initial line width for accommodating the ground through holes; finding a circuit that satisfies The differential signal line pairs and the corresponding ground protection lines under a strong coupling condition; for each of the found ground protection lines, a portion of the corresponding ground through holes is removed, and a modified ground line segment is used to replace the portion of the initial ground line from which the ground through holes have been removed, so as to generate a plurality of modified ground protection lines, wherein the modified ground line has a modified line width smaller than the initial line width; the positions of the differential signal line pairs and the modified ground protection lines are adjusted according to the modified line width; and optimized wiring data is generated. The optimization method as described in claim 1, wherein the strong coupling condition is that the distance between a signal line in each differential signal line pair is less than five times the width of a signal line. The optimization method as described in claim 1, wherein each of the modified ground protection lines has a modified spacing greater than the initial spacing, and the ground vias that are not removed in each of the modified ground protection lines are set at the modified spacing. The optimization method as described in claim 4, wherein the initial spacing corresponds to a first resonant frequency, the modified spacing corresponds to a second resonant frequency, and the second resonant frequency is within an operating frequency range of the differential signal line pairs. The optimization method as described in claim 1, wherein the step of adjusting the positions of the differential signal line pairs and the modified ground protection lines according to the modified line width further includes: reducing a dense wiring area in which the differential signal line pairs that meet the strong coupling condition are arranged in parallel in a parallel direction, wherein the parallel direction is perpendicular to a wiring direction shared by the differential signal line pairs. As described in claim 4, the step of adjusting the positions of the differential signal line pairs and the corrected ground protection lines according to the corrected line width further includes: after the dense wiring area is reduced, adjusting the plurality of signal output pads corresponding to the differential signal line pairs respectively so that they have consistency in a pad arrangement direction. The optimization method as described in claim 6, wherein the circuit board further includes a plurality of second wiring layers disposed below the first wiring layer, and a third wiring layer disposed below the second wiring layers, and the adjusted signal output pads do not have a wiring design in the second wiring layers, but are directly electrically connected to the plurality of bottom pads of the third wiring layer through the corresponding plurality of signal vias in the second wiring layers. As in the optimization method of claim 1, two adjacent pairs of differential signal lines are spaced a predetermined distance from the ground protection line therebetween, and the optimization method further includes adjusting the positions of the differential signal line pairs and the corresponding corrected ground protection lines according to the predetermined distance and the corrected line width. The optimization method as described in claim 8, wherein the step of adjusting the positions of the differential signal line pairs and the corresponding modified ground protection lines according to the predetermined spacing and the modified line width further includes: The predetermined spacing is used as the spacing between two adjacent differential signal line pairs and the modified ground line segment therebetween. An optimization device for integrated circuit layout includes: a memory configured to store a plurality of computer executable instructions; and a processor electrically coupled to the memory and configured to capture and execute the computer executable instructions to execute an optimization method, the optimization method including: obtaining a wiring data to be optimized, which defines a target circuit, including: a circuit board; a plurality of differential signal line pairs, arranged in a first wiring layer of a circuit board; and a plurality of ground protection lines, arranged between the differential signal line pairs adjacent to each other, wherein the ground protection lines each include an initial ground line and a plurality of ground protection lines arranged along the initial ground line at an initial spacing. A plurality of ground vias, the initial ground line having an initial line width for accommodating the ground vias; finding the differential signal line pairs that meet a strong coupling condition and the corresponding ground protection lines; for each of the found ground protection lines, removing a portion of the corresponding ground vias, and replacing the portion of the initial ground line from which the ground vias have been removed with a revised ground line segment to generate a plurality of revised ground protection lines, wherein the revised ground line has a revised line width less than the initial line width; adjusting the positions of the differential signal line pairs and the revised ground protection lines according to the revised line width; and generating optimized wiring data.