TWI868089B - High-aspect ratio electroplated structures and anisotropic electroplating processes - Google Patents

Abstract

A device includes a dielectric layer having a first surface and a second surface. The device also includes a first set of high-aspect ratio electroplated structures disposed on the first surface of the dielectric layer and a second set of high-aspect ratio electroplated structures disposed on the second surface of the dielectric layer opposite the first set of high-aspect ratio electroplated structures.

Description

High aspect ratio electroplating structure and anisotropic electroplating process

The present invention generally relates to electroplating structures and electroplating processes.

Electroplating processes for fabricating structures such as copper or copper alloy circuit structures such as leads, traces, and through-hole interconnects are generally known and disclosed, for example, in Castellani et al., U.S. Patent 4,315,985, entitled Fine-Line Circuit Fabrication and Photoresist Application Therefor. These types of processes are used, for example, in conjunction with the manufacture of disk head suspensions as disclosed in the following patents: Bennin et al., U.S. Patent 8,885,299, entitled Low Resistance Ground Joints for Dual Stage Actuation Disk Drive Suspensions; Rice et al., U.S. Patent 8,169,746, entitled Integrated Lead Suspension with Multiple Trace Configurations; Hentges et al., U.S. Patent 8,144,430, entitled Multi-Layer Ground Plane Structures for Integrated Lead Suspensions; Hentges et al., U.S. Patent 7,929,252, entitled Multi-Layer Ground Plane Structures for Integrated Lead Suspensions; Swanson et al., U.S. Patent 7,388,733, entitled Method for Making Noble Metal Conductive Leads for Suspension Assemblies; and Peltoma et al. U.S. Patent 7,384,531, entitled Plated Ground Features for Integrated Lead Suspensions. These types of processes are also used in conjunction with the manufacture of camera lens suspensions as disclosed below, for example in Miller U.S. Patent 9,366,879, entitled Camera Lens Suspension with Polymer Bearings.

Superfill and superconformal plating processes and compositions are also known and disclosed, for example, in the following articles: Vereecken et al., "The chemistry of additives in damascene copper plating", IBM J. of Res. & Dev., Vol. 49, No. 1, January 2005; Andricacos et al., "Damascene copper electroplating for chip interconnections", IBM J. of Res. & Dev., Vol. 42, No. 5, September 1998; and Moffat et al., "Curvature enhanced adsorbate coverage mechanism for bottom-up superfilling and bump control in damascene processing", Electrochimica Acta 53, pp. 145-154, 2007. With such processes, plating within trenches (e.g., photoresist mask trenches that define spaces for structures to be plated) occurs preferably in the bottom. This can avoid voids in the deposited structure. All of the patents and articles identified above are hereby incorporated by reference in their entirety for all purposes.

There continues to be a need for enhanced circuit structures. There also continues to be a need for efficient and effective processes, including electroplating processes, for manufacturing circuits and other structures.

Apparatus including high aspect ratio electroplated structures and methods of forming high aspect ratio electroplated structures are described. A method for fabricating a metal structure includes providing a substrate having a metal base characterized by a height to width aspect ratio and electroplating a metal top on the substrate to form a metal structure having a height to width aspect ratio greater than the aspect ratio of the substrate.

Other features and advantages of the embodiments of the present invention will be apparent from the accompanying drawings and the following embodiments.

Cross-reference to related applications

This application claims priority to U.S. Patent Application No. 16/693,169, filed on November 22, 2019, and further claims the benefit of U.S. Provisional Application No. 62/771,442, filed on November 26, 2018, each of which is incorporated herein by reference in its entirety.

A high aspect ratio electroplated structure and a method of manufacturing according to an embodiment of the present invention are described. The high aspect ratio electroplated structure provides a tighter conductor spacing than current technology. For example, the high aspect ratio electroplated structure according to various embodiments includes a conductor stack having a cross-sectional area of the conductor stack greater than 50%. In addition, according to an embodiment, the high aspect ratio electroplated structure realizes multiple layers of conductors. In addition, according to various embodiments, the high aspect ratio electroplated structure realizes precise alignment between layers. For example, the high aspect ratio electroplated structure has an alignment of less than 0.030 mm between layers. According to various embodiments, high aspect ratio electroplated structures achieve reduced overall stack height.

According to various embodiments, high aspect ratio electroplated structures enable thinner dielectric materials between coils and magnets formed using high aspect ratio electroplated structures. This enables the coils to generate stronger electromagnetic fields than current printed circuit coils such as those illustrated in FIG. 1 . As a result, high aspect ratio electroplated structures are more cost effective, produce higher performance devices, and reduce the footprint required for the device relative to current technology.

2 illustrates a high density precision coil including high aspect ratio plated structures according to an embodiment. The high aspect ratio plated structures 202 are formed in rows with a dielectric material between each row and each high aspect ratio plated structure 204. The high density precision coil can be formed as a spiral coil or other coil types.

FIG. 3 illustrates a diagram for representing the electromagnetic force generated by a high density precision coil including a high aspect ratio electroplated structure according to an embodiment. The diagram includes a coil cross section 302 close to a magnet 304. The highest electromagnetic force 306 is located in a coil layer 308 closer to the magnet 304. Other coil layers 310 from the magnet 304 exert smaller forces. The main factors affecting the force are from the Lorentz equation: .Because The magnitude of the magnitude decreases with the distance between the coil and the magnet, so is the current flowing through the copper. Any area of the cross-section 302 that is not a conductor does not cause stress ( ).

The main factors affecting the force capability of the coil include the number of turns within the magnetic field (the turns closest to the poles of the magnet provide the greatest force), the distance of the coil from the magnet (layers closer to the magnet will exert more force), and the total percentage of the copper cross-sectional area within the magnetic field. Using high aspect ratio electroplated structures according to various embodiments improves these aspects compared to coils using current coil technology.

For example, a coil with two layers using current technology has a total thickness of about 210 microns, a conductor pitch of 38 microns, a cross-sectional percentage of copper of about 20%, an estimated resistance of 3.1 ohms, an estimated force ratio of 1.0 (an estimated B ratio of 1.0 and an estimated J ratio of 1.0), and an estimated power ratio of 1.0. In contrast, according to various embodiments, a high-density precision coil including a high aspect ratio electroplating structure has a total thickness of about 116 microns, a conductor pitch of 40 microns, a cross-sectional percentage of copper of about 60%, an estimated resistance of 5.5 ohms, an estimated force ratio of 1.2 (an estimated B ratio of 1.5 and an estimated J ratio of 0.8), and an estimated power ratio of 0.71. Therefore, according to various embodiments, a high-density precision coil including a high aspect ratio electroplated structure is a higher performance device. Therefore, according to some embodiments, this high-density precision coil provides 20% more force and 30% less power with half the thickness of the coil using current state-of-the-art technology.

FIG. 4 illustrates a device including multiple layers of a high aspect ratio electroplated structure according to one embodiment configured for use in a linear motor type application. Due to size advantages over current technology, each layer 402a-d of the high aspect ratio electroplated structure is closer to the magnet 404 than is possible using current technology as illustrated in FIG. 1 . Additionally, each layer 402a-d is closer to the magnet 404 by utilizing volume Field (magnetic flux density) to improve the force-applying ability of linear motors. Therefore, multi-layer high aspect ratio electroplated structures for linear motors will require fewer layers than using current technology. In addition, this structure provides greater flexibility in obtaining electrical properties such as low resistance.

FIG. 5 illustrates a high aspect ratio electroplated structure at one stage during a fabrication process according to some embodiments. The layers of the high aspect ratio electroplated structure 602 at this stage during the fabrication process are formed using semi-additive techniques to produce fine pitch, resist defined conductors having an initial height to width aspect ratio (A/B) of approximately 1 to 1. For example, the high aspect ratio electroplated structure may have a height of 20 microns and a width of 20 microns. According to some embodiments, the plating process is stopped at this point in order to remove defined products, such as photoresist masks and seed layers, using techniques including those known in the art.

FIG. 6 illustrates a high aspect ratio electroplated structure at another stage during a manufacturing process according to some embodiments. The layers of the high aspect ratio electroplated structure 702 at this stage during the manufacturing process are formed using a top plating technique to convert a semi-additive conductor into a high aspect ratio, high percentage metal conductor circuit. For example, the high aspect ratio electroplated structure has a final height to width ratio (A/S) greater than 1 to 1. According to various embodiments, the final height to width ratio can be in a range including 1.2 to 3.0. Other embodiments include a final height to width ratio greater than 3.0. However, those skilled in the art will appreciate that any final height to width ratio may be achieved using the techniques described herein to meet design and performance criteria. In the formation stage as illustrated in FIG. 6 resulting from the previous stage as illustrated in FIG. 5 , there is no particular limitation on the final height of the high aspect ratio electroplated structure as disclosed in the various embodiments.

FIG. 7 illustrates a high aspect ratio plated structure at another stage during the fabrication process according to some embodiments. The layers of high aspect ratio plated structures 802a, 802b at this stage during the fabrication process are formed using a planarization transfer technique to allow stacking of multiple layers of high aspect ratio plated structures using a semi-additive technique to form subsequent layers. FIG. 8 illustrates a device having multiple layers of high aspect ratio plated structures having a high ratio of conductor cross-sectional area 901 according to some embodiments.

A method for forming high aspect ratio plated structures from structures such as those illustrated in FIG. 5 includes using a low current density plating technique. This plating technique plates the sidewalls until the desired spacing between the high aspect ratio plated structures is obtained. For various embodiments, if the spacing between the high aspect ratio plated structures is not narrow enough, undesirable pinching at the top can occur. Pinching occurs when the top edges of adjacent structures grow together and interrupt the gap, which creates a short circuit. For various embodiments, the low current density plating process is enhanced by sufficient fluid exchange so that fresh plating bath is continuously available to the surface where copper plating occurs. In addition, the method for forming a high aspect ratio electroplated structure includes using a high current density plating technique. This high current density plating technique is performed at a high percentage of mass transfer limit. This is mainly or only coated on the top of the conductive material forming the high aspect ratio electroplated structure. The high current density plating process is enhanced by precise current density control. 9 illustrates a graph having an upper line 1002 indicating high SPS coverage during a high current density plating technique according to one embodiment and a lower line 1004 indicating low, very uniform accelerator coverage during a low current density plating technique according to one embodiment.

Figures 10a-f illustrate a process for forming a high aspect ratio electroplated structure according to one embodiment. Figure 10a illustrates a trace 1102 formed at the thickness limit of the etchant capability at time T1 of the process. For some embodiments, a pre-plated conventional trace is formed from copper using a process such as metal inlay, or using etching and deposition techniques including those known in the art. Figure 10b illustrates the formation of a high aspect ratio electroplated structure at time T2 during a low current density or conformal plating process. According to one embodiment, the conformal plating process grows all surfaces of the trace at approximately the same rate. In addition, the conformal plating process suppresses plating dynamics (low accelerator coverage). The conformal plating process also provides a fairly uniform metal concentration, which has a high uniform inhibitor coverage to offset. This suppressed plating kinetic effect can be enhanced by including a leveler in the plating bath. A lower current density is required to obtain a uniform metal concentration and obtain a high uniform inhibitor coverage. According to some embodiments, a conformal plating process using 2 amps per square meter is used for plating, such as copper, brightener additives, platen temperature, and fluid mechanisms. Examples of this conformal plating process include, but are not limited to, a low current density plating process. At low current density, the plating bath maintains a uniformly suppressed state, providing conformal coating. For another embodiment, a leveler can be added to the plating bath to provide higher current density and faster plating. For yet another embodiment, increasing the copper content to near the solubility limit of copper sulfate in the plating bath can be used to further increase the current density. This provides the ability to double the current density or even greater to achieve the same conformal plating quality. For example, the copper content can be as high as 40 grams per liter with reduced acid content to prevent co-ion effects.

For some embodiments, a low current density plating process deposits a conductive material such as copper onto the top and side walls of the trace 1102, for example, T2 is approximately five minutes into the process (T1+5 minutes) during the low current density plating process. FIG. 10c illustrates the formation of a high aspect ratio electroplated structure at time T3 into the process during the low current density plating process. For one embodiment, a low current density plating process deposits a conductive material such as copper onto the top and side walls of the trace 1102, for example, T3 is approximately five minutes into the process (T1+15 minutes) during the low current density plating process.

FIG. 10d illustrates the formation of a high aspect ratio electroplated structure at time T4 into the process during a top plating process (e.g., a high current anisotropic super plating process). For example, T4 is approximately 15 minutes and 10 seconds into the process (T1+15 minutes 10 seconds). For some embodiments, the high current anisotropic super plating process is top plating. Top plating is based on balancing the interaction between the following factors: metal concentration in the solution, brightener additives, inhibitor additives, mass transfer to the surface-fluid exchange rate, leveling agents, and current density at the substrate. The metal concentration in the solution may include, but is not limited to, copper. Brightener additives may include but are not limited to SPS (bis(3-sulfopropyl)-disulfide), DPS (3-N,N-dimethylaminodithiocarbamoyl-1-propanesulfonic acid) and MPS (methylpropylsulfonic acid). Suppressor additives may include but are not limited to linear PEGs of various molecular weights known to those skilled in the art; poloxamines; co-block polymers of polyethylene glycol and polypropylene glycol, such as water-soluble poloxamers known by various trade names, such as BASF pluronic f127; and random copolymers of various monomer ratios and various molecular weights, such as the DOW® UCON series of high performance fluids; polyvinylpyrrolidone of various molecular weights.

According to some embodiments, a high current anisotropic superplating process includes a suppressed exchange current of 1% of the accelerating current. In addition, the sidewalls of the formed high aspect ratio electroplated structure have nearly zero accelerator coverage. Nearly zero accelerator coverage is achieved by shifting the Nernst Potential of copper deposition to promote suppressor coverage. In addition, high overpotential and copper availability (transport phenomenon) produce higher accelerator coverage at the top of the formed structure. The overall copper concentration can also be adjusted to support near-zero accelerator coverage during the process. For example, the bulk concentration of copper used in the high current anisotropic superplating process is 14 grams per liter or less. For some embodiments, the bulk concentration of copper depends on a particular fluid mechanism. Because various embodiments of the process operate at a relatively high percentage of mass transfer limits, small differences in fluid velocity on the article to be plated will affect the mass transfer limits, making it difficult to achieve adequate control of the gap between plated lines without a high degree of control of the fluid velocity in all areas of the article to be plated. According to some embodiments, the high current anisotropic superplating process includes a leveling agent additive that is used to prevent accelerator coating to minimize or eliminate coating on the side walls of the formed structure. For other embodiments, a plating bath without a leveler additive is used.

According to some embodiments, at high current densities, such as those used during high current anisotropic superplating processes, a triple feedback mechanism operates. The mass transfer effect depletes copper in the spaces between traces. In addition, high current densities support accelerator (e.g., SPS)-dominated surfaces. To maintain containment sidewalls, mass transfer is tuned to reduce the Nernst potential via the copper mass transfer effect. For example, the fluid boundary layer thickness and the spacing between traces are designed to reduce the Nernst potential.

In addition, according to some embodiments, the high current anisotropic superplating process includes operating at copper concentrations where such differences can produce concentration differences greater than four times. During such conditions, the lower copper concentration and Nernst potential cause the plating rate to decrease. For example, when the Nernst potential is changed within a range of approximately 50 millivolts ("mV") to 60 mV, this can cause the plating rate to decrease by a factor of twenty. Such conditions induce Tafel kinetics, which for copper plating is a tenfold change in current for every 120 mV change in applied voltage (non-rectified voltage). The lower sidewall current feeds back to the top surface of the formed structure where the diffusion length is shorter which promotes faster delivery of metal from the plating bath (solution) to the surface and higher accelerator coverage rather than suppression, and higher Nernst potential. For some embodiments, a two-additive system (e.g., brightener and suppressor) is used. Levelers mitigate the feedback mechanism by blocking the SPS action on the top side of the plated feature.

As the spacing between metal conductors or traces continues to shrink, the aspect ratio of the height to width of the spacing between metal conductors is substantially increased. According to some embodiments, the method of electroplating process provided herein achieves plating with an aspect ratio of 7:1 and greater in the spacing between metal conductors.

According to some embodiments, a method of forming a high aspect ratio electroplated structure selectively forms a metal top coating at a selective location or region. In an exemplary embodiment, the metal top is selectively formed by performing an electroplating process according to the following relationship: where C is the concentration of the metal (in this case copper) where the plating occurs, and C∞ is the overall concentration in the plating bath. This relationship can also be expressed for the electroplating process, where is equal to or greater than 67% (%) of the mass transfer limit. According to other embodiments, the metal top is selectively formed by performing an electroplating process according to the following relationship: or among them is equal to or greater than 80% of the mass transfer limit. In another aspect, the selective formation of the metal top is achieved by performing the electroplating process according to the following relationship: Here i is the current density, and i _limit is the current density limit.

Figure 10e illustrates the formation of a high aspect ratio plating structure at time T5 during a high current anisotropic super plating process. For example, T5 is about 15 minutes and 30 seconds into the process (T1+15 minutes 30 seconds). For another embodiment, a high aspect ratio plating structure as illustrated in Figure 10e is formed at time T5=T1+5 minutes. Figure 10f illustrates the formation of a high aspect ratio plating structure at time T6 during a high current anisotropic super plating process. This illustrates the end of the top plating process, which ends according to the formation of a high aspect ratio plating structure in some embodiments. For example, T6 is approximately 20 minutes into the process (T1+20 minutes). For another embodiment, a high aspect ratio electroplating structure as shown in FIG. 10f is formed at time T6=T1+10 minutes.

For some embodiments, a method for forming a high aspect ratio electroplated structure uses a process including conformal plating and anisotropic plating as described herein. According to some embodiments, the conformal plating process uses 2/3 of the total plating time. For other embodiments, the conformal plating process uses 1/3 of the total plating time. In addition, the conformal plating process starts with a 2 ampere per square inch ("ASD") low metal plating bath or a 4 ASD high metal plating bath. For example, the plating bath includes 12 grams per liter of copper and 1.85 molar concentration (mol/liter) of sulfuric acid. Alternatively, the conformal plating process is a process that is plated at a rate of 0.4 to 1.2 microns per minute. According to one embodiment, the conformal plating process continues until the spacing between traces is within a range of 6 to 8 microns, inclusive. The current density will slowly decrease as the surface area of the structure being formed increases. However, the process will achieve uniform current density and growth rate for all surfaces being formed. For some embodiments, as the surface area of the high aspect ratio structure being formed increases, the current can be increased to maintain the current density.

According to some embodiments, an anisotropic plating process uses 1/3 of the total plating time to form a high aspect ratio plated structure. The anisotropic plating process increases the ASD to 7 ASD (3.5 times the current of the conformal plating process), but on average, doubles the ASD at the top of the formed metal structure. The same fluid flow as used in the conformal plating process can be maintained. For example, at a plating rate of 3 microns/minute, the top of the structure is formed on the side walls of the structure with almost zero plating rate. As the structure grows, the average current is halved, but the peak current density is maintained at approximately 14 ASD at the structured top according to the embodiments. For example, the peak current density exceeds the mass transfer limit at the top surface by only 50%, and even though the sidewalls are exposed to 3 g/L of copper, the sidewalls are still coated at less than 10% of the mass transfer limit, or a coating rate of 5:1. At higher ratios of the mass transfer limit, we can get higher coating rate ratios.

Embodiments of methods for forming high aspect ratio plated structures include variations of those described above to form high aspect ratio plated structures including different features. For example, the copper content in a plating bath configured as an anisotropic bath can vary by 13.5 grams per liter as described above. Varying the copper content in a flat trace bath but using the same current density can be used to control the spacing between high aspect ratio plated structures. Another embodiment of the method described herein includes using a flat trace bath having a flat trace bath with a copper content of 12 grams per liter to form high aspect ratio plated structures that are 8 microns apart. Yet another embodiment of the method described herein includes using a flat trace bath having a flat trace bath with a copper content of 15 g/L to form high aspect ratio electroplated structures 4 microns apart. Thus, one skilled in the art will appreciate that adjusting other parameters of the method described herein can be used to alter the characteristics of the high aspect ratio electroplated structures. Some embodiments of the method described herein include adjusting the current density to match the current plating conditions, such as mass transfer rate, metal contained in the plating bath, fluid velocity, copper concentration, additives used, and temperature.

The method of forming high aspect ratio electroplated structures also includes using a thinner dielectric process. According to some embodiments, photosensitive polyimide is used as a dielectric between each high aspect ratio electroplated structure. Liquid photosensitive polyimide enables smaller via capability, good coverage between high aspect ratio conductors, good alignment/tolerance capability, is a high reliability material and has a coefficient of thermal expansion ("CTE") that is closely matched to copper. Liquid photosensitive polyimide can easily fill gaps between high aspect ratio electroplated structures. According to some embodiments, the use of liquid photosensitive polyimide produces via entrances down to 0.030 mm. Other dielectrics that may be used include but are not limited to KMPR and SU-8.

FIG. 11 illustrates a high aspect ratio plated structure formed using the methods described herein according to some embodiments. Each high aspect ratio plated structure 1202 includes a plurality of texture lines 1204 showing how the plating process progresses to form the structure. A thinner dielectric 1206 is formed between and disposed on the high aspect ratio plated structures 1202. FIG. 12 illustrates a perspective view of a high aspect ratio plated structure 1302 formed using the methods described herein according to some embodiments.

The methods described herein can be used to form high aspect ratio plating structures that form high density precision coils. Figure 13a illustrates a high density precision coil formed using a high aspect ratio plating structure according to an embodiment. Coil 1402 is formed from a high aspect ratio plating structure such as those structures described herein. The high density precision coil also includes a center coil through hole 1404. The center coil through hole 1404 reduces the voltage drop across the coil during the manufacturing steps described herein. In addition, the center coil through hole 1404 enables better control of the variation in the spacing within the coil through better control of the voltage drop and current during the anisotropic plating process described herein. The center coil through hole 1404 also enables better control of the voltage drop of the formed high density precision coil. Figure 13b illustrates a cross section of the center coil through hole 1404 as part of a high density precision coil as described herein.

FIG. 14 illustrates a high aspect ratio plated structure including high resolution stacked conductor layers according to one embodiment. A first conductor layer 1502a includes a high aspect ratio plated structure 1504 formed using techniques including those described herein. A first dielectric layer 1508 is formed using a thin dielectric process (using techniques including those described herein). The first dielectric layer 1508 fills all spaces between the high aspect ratio plated structures of the first conductor layer 1502a and forms a coating over the high aspect ratio plated structures 1504. The first dielectric layer 1508 is planarized using techniques known in the art. The second conductive layer 1502b includes a high aspect ratio plated structure 1506 formed over the planarized surface of the first dielectric layer 1508. A second dielectric layer 1510 is formed using a thin dielectric process (using techniques including those described herein) to fill all spaces between the high aspect ratio plated structures 1506 of the second conductive layer 1502b and to form a coating layer over the high aspect ratio plated structures 1506. The second dielectric layer 1510 may also be planarized. Additional layers including high aspect ratio plated structures may be formed using techniques described herein.

FIG. 15 illustrates a high density precision coil including high aspect ratio plated structures including high resolution stacked conductor layers according to one embodiment. A first conductor layer 1602a includes a high aspect ratio plated structure formed using techniques including those described herein. A first dielectric layer 1608 is formed using a thin dielectric process (using techniques including those described herein). The first dielectric layer 1608 fills all spaces between the high aspect ratio plated structures of the first conductor layer 1602a and forms a coating over the high aspect ratio plated structures. The first dielectric layer 1608 is planarized using techniques known in the art. The second conductive layer 1602b includes high aspect ratio plated structures formed over the planarized surface of the first dielectric layer 1608. A second dielectric layer 1610 is formed using a thin dielectric process (using techniques including those described herein) to fill all spaces between the high aspect ratio plated structures of the second conductive layer 1602b and to form a coating layer over the high aspect ratio plated structures. The second dielectric layer 1610 may also be planarized. Additional layers including high aspect ratio plated structures may be formed using techniques described herein.

The high density precision coil is formed to have a first distance 1614 between the high aspect ratio electroplated structure of the first conductive layer 1602a and the high aspect ratio electroplated structure of the second conductive layer 1602b. For various embodiments, the first distance 1614 is less than 0.020 mm. For another embodiment, the first distance 1614 is 0.010 mm. The high density precision coil is formed to have a second distance 1616 between the surface 1618 of the second dielectric layer 1610 and the high aspect ratio electroplated structure of the first conductive layer 1602a. For various embodiments, the second distance 1616 is less than 0.010 mm. For some embodiments, the second distance 1616 is 0.005 mm. For some embodiments, the second distance 1616 can be the starting gap minus the final desired gap divided by 2. The high density precision coil is formed to have a third distance 1620 between the high aspect ratio electroplated structure of the first conductor layer 1602a and the surface of the first dielectric layer 1622. For various embodiments, the third distance 1620 is less than 0.020 mm. For some embodiments, the third distance 1620 is less than 0.015 mm. For another embodiment, the third distance 1620 is 0.010 mm. For various embodiments, the first dielectric layer is formed on a substrate 1624 using techniques including those described herein. For some embodiments, the substrate 1624 is a stainless steel layer. Those skilled in the art will appreciate that the substrate 1624 may be formed of other materials, including but not limited to steel alloys, copper alloys (such as bronze, pure copper, nickel alloys, palladium copper alloys), and other metals including those known in the art.

Other advantages of forming devices using high aspect ratio electroplated structures as described herein include devices having high structural strength, high reliability, and high heat dissipation. High structural strength is provided by the ability to form extremely dense concentrations of metal high aspect ratio electroplated structures on all layers of the device. In addition, the process used to form the metal high aspect ratio electroplated structures described herein provides lateral alignment of the structure between layers, thereby increasing the high structural strength. The high structural strength of the device formed using the process used to form the metal high aspect ratio electroplated structures described herein is also a result of the good adhesion of the dielectric layer material (such as a photosensitive polyimide layer) to the structure. For some embodiments, a high aspect ratio electroplated structure formed using the techniques described herein is coated with a non-magnetic nickel layer to improve the adhesion of the dielectric layer. This will further increase the high structural strength of the final device formed using the high aspect ratio electroplated structure described herein.

The reliability of devices formed using the high aspect ratio electroplating structures described herein is also higher due to the use of high reliability materials that provide robust electrical performance, such as photosensitive polyimide for the dielectric layer. Using the techniques described herein provides the ability to form devices with less dielectric material and reduce the overall thickness of the formed device. Thus, heat dissipation is increased by increasing the thermal conductivity above the device using current process technology.

Figures 16a-c illustrate a process for forming a high aspect ratio electroplated structure according to another embodiment. Figure 16a illustrates a trace 1802 formed on a substrate 1804 using subtractive etching. According to some embodiments, a metal layer is formed above the substrate 1804. A photoresist layer is formed above the metal layer using techniques including those known in the art. For some embodiments, the photoresist layer is a photosensitive polyimide deposited in liquid form above the metal layer. The photoresist is patterned and developed using techniques including those known in the art. The metal layer is then etched using techniques including those known in the art. After the etching process, trace 1802 is formed.

FIG. 16b illustrates forming a high aspect ratio electroplated structure using a conformal plating process such as those described herein. FIG. 16c illustrates forming a high aspect ratio electroplated structure using a top plating process such as those described herein. For various embodiments, the high aspect ratio electroplated structure is formed without using a conformal plating process such as those described with reference to FIG. 16b. Instead, a top plating process such as that described with reference to FIG. 16c is used after forming traces 1802 such as those illustrated in FIG. 16a.

FIG. 17 illustrates the selective formation of a high aspect ratio electroplated structure according to one embodiment. Once traces 1902 are formed using techniques including those described herein, a photoresist layer 1904 is formed over segments of one or more of the formed traces 1902. The photoresist layer 1904 may be a photosensitive polyimide and is deposited and formed using techniques including those described herein. A metal top 1906 is formed over the traces 1902 using one or both of a conformal plating process and a top plating process as described herein. FIG. 18 illustrates a perspective view of a high aspect ratio electroplated structure formed with a metal top portion selectively formed over the traces according to one embodiment. According to some embodiments, selectively forming a metal top portion on a trace is used to improve structural properties of a high aspect ratio plated structure, improve electrical performance of a high aspect ratio plated structure, improve heat transfer properties, and meet custom size requirements of a device formed using the high aspect ratio plated structure. Examples of electrical performance improvements include, but are not limited to, capacitance, inductance, and resistance properties of the high aspect ratio plated structure. Additionally, selectively forming a metal top portion on a trace can be used to tune mechanical or electrical properties of a circuit formed using the high aspect ratio plated structure.

FIG. 19 illustrates a hard disk drive suspension flexure 2102 including a high aspect ratio plated structure formed using selective formation as described herein according to one embodiment. FIG. 20 illustrates a cross-sectional view of the hard disk drive suspension flexure illustrated in FIG. 19 taken along line A-A. The cross-section of the flexure 2102 includes a high aspect ratio plated structure 2104 and a trace 2106. The high aspect ratio plated structure 2104 is formed using selective formation techniques as described herein. Forming the high aspect ratio plated structure 2104 to function as a conductor in a predetermined area of the flexure can achieve a reduction in DC resistance. This allows for the fine lines and spaces required on the flexure while meeting the design requirements for DC resistance and improving the electrical performance of the flexure.

Figures 21a, 21b illustrate a process for forming a high aspect ratio electroplated structure according to one embodiment using photoresist during a conformal coating process. Figure 21a illustrates a trace 2302 formed on a substrate 2304 using techniques including those described herein. Figure 21b illustrates the formation of a high aspect ratio electroplated structure using a coating process as described herein. A photoresist portion 2306 is formed over the substrate 2304 using deposition and patterning techniques including those described herein. Once the photoresist portion 2306 is formed in one or both of the conformal coating processes, a top coating process is performed to form a metal portion 2308 over the trace 2302. Photoresist portions 2306 may be used to better define the spacing between high aspect ratio plated structures.

22 illustrates exemplary chemistries for forming an initial metal layer process, a standard/conformal plating process, and a top plating process according to various embodiments.

FIG. 23 illustrates a perspective view of a top surface 2501 of an inductively coupled coil 2502 formed from a high aspect ratio plating structure 2504 having an integrated tuning capacitor according to one embodiment. Forming the inductively coupled coil using the high aspect ratio plating structure reduces the footprint of the inductively coupled coil as compared to an inductively coupled coil formed using a galvanic technique. This enables the inductively coupled coil 2502 to be used in applications where space is limited. Additionally, the use of a capacitor integrated into the inductively coupled coil further reduces the footprint of the inductively coupled coil because no additional space requirements are required to accommodate discrete capacitors such as surface mount technology (“SMT”) capacitors.

Figure 24 illustrates a perspective view of the back side 2604 of the embodiment of the inductively coupled coil 2502 illustrated in Figure 23. Figure 25 illustrates a perspective view of the top side of the inductively coupled coil 2502 coupled to a radio frequency identification ("RFID") chip 2704 according to one embodiment.

Figures 26a-j illustrate a method of forming an inductively coupled coil 2502 formed from a high aspect ratio electroplated structure 2504 according to one embodiment. According to various embodiments, the inductively coupled coil comprises an integrated tuning capacitor. Figure 26a illustrates a substrate 2802 formed using techniques including those known in the art. For some embodiments, the substrate 2802 is formed of stainless steel. Other materials that may be used for the substrate include, but are not limited to, steel alloys, copper, copper alloys, aluminum, non-conductive materials that may be metallized using techniques including plasma vapor deposition, chemical vapor deposition, and electrodeless chemical deposition. A shield 2804 is formed over the substrate 2802. According to some embodiments, the shield 2804 is a high-K dielectric. Examples of high-K dielectrics that may be used include, but are not limited to, titanium dioxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (TaO), aluminum oxide (Al2O3), silicon dioxide (SiO2), polyimide, SU-8, KMPR, and other high-capacitance dielectric materials. According to some embodiments, the shield 2804 is formed using a sputtering process using techniques including those known in the art. For some embodiments, the shield 2804 is formed to have a thickness in a range of 500 to 1000 angstroms. For other embodiments, the shield 2804 is formed using screen printing of a high-capacitance ink. Examples of high dielectric constant inks include inks including epoxy loaded with particles made of one or more of titanium dioxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (TaO), aluminum oxide (Al2O3), silicon dioxide (SiO2), polyimide, and other high dielectric constant materials. For other embodiments, a slot mold application using a photoimageable dielectric doped with a high-K filler is used to form the mask 2804. An example of a high-K filler includes zirconium dioxide (ZrO2).

FIG. 26b illustrates a metal capacitor plate 2806 formed above the shield 2804. The metal capacitor plate 2806 and substrate 2802 form two capacitor plates of an integrated capacitor. The thickness of the shield 2804 can be used to set the effective capacitance of the integrated capacitor. In addition, the purity of the high-K dielectric used to form the shield 2804 can be used to set the effective capacitance of the integrated capacitor. The surface area of the metal capacitor plate 2806 can also be used to set the effective capacitance of the integrated capacitor.

FIG. 26 c illustrates a base dielectric layer 2808 formed over the shield 2804, the metal capacitor plate 2806, and at least a portion of the substrate 2802. According to some embodiments, the base dielectric layer 2808 is formed by depositing a dielectric material, patterning the dielectric material, and curing the dielectric material using techniques including techniques known in the art. Examples of dielectric materials that may be used include, but are not limited to, polyimide, SU-8, KMPR, and hard-baked photoresists, such as those sold by IBM®. The base dielectric layer 2808 may also be patterned or etched to form vias. For example, a jumper via 2812 and a shunt capacitor via 2810 are formed in the base dielectric layer 2808. Shunt capacitor vias 2810 are formed to interconnect the integrated capacitor to the remaining portion of the circuit to be formed. Similarly, jumper vias 2812 are used to interconnect the circuit elements to be formed to the substrate 2802.

FIG. 26d illustrates a coil 2814 formed over a base dielectric layer 2808 using a high aspect ratio plating structure to form a coil using techniques including those described herein. For some embodiments, coil 2814 is a single layer coil. Coil 2814 includes a center connection portion 2816 connected to one of the shunt capacitor vias 2810 and one of the crossover vias 2812 that is in electrical contact with the metal capacitor plate 2806 of the integrated capacitor. Coil 2814 also includes a capacitor connection portion 2818 to connect coil 2814 to another of the shunt capacitor vias 2810 that is in electrical contact with the substrate 2802 configured as the lower plate of the integrated capacitor. According to various embodiments, the terminal pad 2820 is formed from a high aspect ratio electroplated structure using techniques including those described herein. The terminal pad 2820 can be formed during the same process used to form the coil 2814.

FIG. 26e illustrates a top layer 2822 formed over the coil 2814, the terminal pad 2820, and the base dielectric layer 2808 to cover the coil side of the inductive coupling coil. The top layer 2822 is formed using deposition, etching, and patterning steps, including those steps known in the art. For example, the top layer 2822 can be formed of polyimide solder resist, SU-8, KMPR, or epoxy.

FIG. 26f illustrates the back side of an inductively coupled coil formed according to one embodiment. At least a first bonding pad 2824 and a second bonding pad 2826 are formed on the side of substrate 2802 opposite coil 2814. According to some embodiments, first bonding pad 2824 and second bonding pad 2826 are formed from gold using deposition and patterning techniques including those known in the art. First bonding pad 2824 and second bonding pad 2826 are formed to provide electrical contacts for attaching an integrated circuit chip, such as an RFID chip, to substrate 2802.

FIG. 26g illustrates a back dielectric layer 2828 formed on the back side of an inductively coupled coil formed according to one embodiment. The method of forming the inductively coupled coil may optionally include forming a back dielectric layer 2828 on a substrate 2802. The back dielectric layer 2828 is formed using techniques similar to those used to form the base dielectric layer 2808. According to some embodiments, the back dielectric layer 2828 is patterned to prevent short circuits between the substrate 2802 and the attached integrated circuit chip. According to various embodiments, the back dielectric layer 2828 is patterned to provide a jumper pattern 2830 to be etched to the substrate 2802 to form a jumper path in a subsequent step. Other patterns in the back dielectric may be formed to also etch other portions of the substrate 2802.

FIG. 26h illustrates an inductively coupled coil 2834 formed into its final shape according to one embodiment. The portion of the substrate 2802 not covered by the back dielectric layer 2828 is etched. This etched portion includes a jumper pattern 2830 to form a jumper path 2832. The etching is performed using techniques including techniques known in the art. Those skilled in the art will understand that other portions of the substrate 2802 can be etched to form other conductive paths similar to the jumper path 2832. FIG. 26i illustrates the coil side of the inductively coupled coil 2834 including the jumper path 2832 according to one embodiment.

FIG. 26j illustrates the coil side of an inductively coupled coil 2834 according to one embodiment, which includes an integrated chip 2836 attached to the back side of the inductive coil. The method for forming the inductively coupled coil 2834 may optionally include the step of attaching an integrated chip 2836 (such as an RFID chip) to the inductively coupled coil 2834 using techniques including those known in the art. The integrated chip 2836 is attached using adhesives including, but not limited to, conductive epoxy, solder, and other materials for connecting electrical connectors.

Integration of capacitors into devices including high aspect ratio plated structures can take advantage of the smaller footprint requirements achieved by using high aspect ratio plated structures. Other embodiments of the inductively coupled coil include an inductively coupled coil having a plurality of integrated capacitors. As is known in the art, the integrated capacitors may be connected in parallel or in series. Other devices including high aspect ratio plated structures (which may also include integrated capacitors) include, but are not limited to, buck transformers, signal conditioning devices, tuning devices, and other devices that would include one or more inductors and one or more capacitors.

High aspect ratio electroplated structures according to embodiments described herein may be used to form devices or portions of devices to optimize performance and achieve a small footprint. Such devices include, but are not limited to, power converters (e.g., step-down transformers, voltage dividers, AC transformers), actuators (e.g., linear, VCM), antennas (e.g., RFID, wireless power transfer and security chips for battery charging), wireless passive coils, cellular phones and rechargeable medical device batteries, proximity sensors, pressure sensors, contactless connectors, micromotors, microfluidic components, on-package cooling/heat sinks, long and narrow flexible circuits with air core capacitors and inductors (e.g., for catheters), interdigitated acoustic wave transducers, tactile vibrators, implantable devices (e.g., pacemakers, stimulators, bone growth devices), magnetic resonance imaging ("MRI") devices for procedures (e.g., esophagoscopy, colonoscopy), Ultratactile (e.g., clothing, gloves), coated surfaces for detection/filter release, security systems, high energy density batteries, inductive heating devices (for small local areas), magnetic fields for fluid/drug dispersion and dose delivery via channel pulses, tracking and information devices (e.g., agriculture, food, valuables), credit card security, acoustic wave systems (e.g., speaker coils, recharging mechanisms in headphones, earplugs), heat transfer, mechanical thermally conductive seals, energy harvesters, and interlocking formations (similar to hook and loop fasteners). In addition, high aspect ratio electroplated structures as described herein can be used to form high bandwidth, low impedance interconnects. The use of high aspect ratio plated structures in interconnects can be used to improve electrical characteristics (e.g., resistance, inductance, capacitance), improve heat transfer characteristics, and tailor dimensional requirements (thickness control). Interconnects including high aspect ratio plated structures as described herein can be used to tune the bandwidth of one or more circuits for a given frequency range. Other interconnect applications including high aspect ratio plated structures can integrate one or more circuits of different currents (e.g., signal and power). The use of high aspect ratio plated structures allows circuits with different cross-sections, allowing some with more current carrying capacity, to be manufactured together in close proximity to maintain a concentrated overall package size. High aspect ratio plated structures can also be used in interconnects for mechanical purposes. For example, it may be desirable to raise some areas of a circuit above other areas to act as mechanical stops, bearings, electrical contact areas, or for additional rigidity.

27 illustrates a plan view of a flexure of a suspension for a hard disk drive including a high aspect ratio electroplated structure according to one embodiment. Flexure 2900 includes a distal portion 2901, a ring portion 2902, a middle portion 2904, a gap portion 2906, and a proximal portion 2908. Proximal portion 2908 is configured to attach to a base plate such that distal portion 2901 extends above a rotating disk media. According to some embodiments, the ring frame portion 2902 is configured to include one or more motors, such as piezoelectric motors, and one or more electrical components, such as a head float for reading or writing to disk media, and components for heat-assisted magnetic recording ("HAMR")/thermal-assisted magnetic recording ("TAMR") or microwave-assisted magnetic recording ("MAMR"). The one or more motors and the one or more electrical components are electrically connected to other circuits via one or more traces formed on a conductive layer of the flexure, which extends from the distal portion 2901 of the flexure 2900 through the middle portion 2904 and beyond the proximal portion 2908 on the gap portion 2906. The gap portion 2906 is a portion of the flexure where a substrate layer, such as a stainless steel layer, is partially and completely removed. Thus, one or more of the traces in the conductor layer of the flexure extend over the gap portion 2906 without any support. Those skilled in the art will appreciate that the flexure may have one or more gap portions 2906 at any location along the flexure.

FIG. 28 illustrates a cross-section of the interstitial portion of the flexure at the interstitial portion, taken along line A as illustrated in FIG. The interstitial portion 2906 includes a trace 3002 disposed over a dielectric layer 3004. A dielectric layer, such as a polyimide layer, is disposed over a substrate 3006, such as a stainless steel layer. The substrate 3006 and the dielectric layer 3004 define a void 3008 such that the trace 3002 extends over the void 3008. The trace 3002 includes a metal top portion to form a high aspect ratio structure. The metal top portion is selectively formed over the trace 3002 using the techniques described herein. A metal top portion is formed on trace 3002 to provide additional strength across gap 3008 and to electrically couple with an interconnect at the area of gap 3008 when used.

FIG. 29 illustrates a frame portion 2902 having a mass structure 3102 according to one embodiment. The mass structure 3102 is formed using a high aspect ratio electroplated structure using the techniques described herein. For some embodiments, the mass structure 3102 is used as a counterweight to tune the resonance of the frame portion 2902. Thus, the shape, size, and location of the mass structure 3102 may be determined to tune the resonance of the frame portion 2902 to enhance the performance of the hard drive suspension. The processes described herein for forming the high aspect ratio structure may be used to maintain the size of the high aspect ratio structure so that the resonance may be finely tuned. Additionally, the process is able to form high aspect ratio structures at dimensions beyond the capabilities of current lithography processes, thereby enabling more control over the final structure formed.

The mass structure 3102 may also be configured to act as a mechanical stop. For example, one or more mechanical stops may be formed in any shape to act as a reverse stop and/or to align the mounting of components on the ring frame portion 2902 or other portions of the flexure.

FIG30 illustrates a cross-section of a proximal portion of a flexure including a high aspect ratio electroplated structure according to one embodiment, taken along line B as illustrated in FIG27. The proximal portion 2904 includes a conductive layer including traces 3002a, 3002b, 3002c, 3002d disposed over a dielectric layer 3004. The dielectric layer 3004 is disposed over a substrate 3006. A capping layer 3001 is disposed over the conductive layer and the dielectric layer. The conductive layer includes known traces 3002a, 3002b and traces 3002c, 300d formed with at least a portion of the trace including a metal top portion 3202a, 3202b to form a high aspect ratio electroplated structure using the techniques described herein. One or more portions of the traces 3002a, 3002b, 3002c, 3002d may be formed to include a metal top portion 3202a, 3202b to tune the impedance of each trace. For example, the resistance of the trace may be tuned as needed to meet desired performance characteristics. Another example includes using a metal top portion to tune impedance by closing the distance between adjacent traces 3002a, 3002b, 3002c, 3002d.

FIG31 illustrates a cross-section of a proximal portion of a flexure including a high aspect ratio structure according to one embodiment, taken along line C as illustrated in FIG27. The proximal portion of the flexure includes a conductive layer including at least one trace 3002 disposed over a dielectric layer 3004. The dielectric layer 3004 is disposed on a substrate 3006. In addition, a cover layer 3001 is disposed over the dielectric layer 3004 formed to include a metal top portion to form a high aspect ratio electroplated structure using the techniques described herein. The trace 3002 is configured as a high aspect ratio structure to match the impedance of the trace to a terminal connector and provide strength to a joint that electrically couples the trace 3002 to the connector. 32 illustrates a plan view of a proximal portion 2908 of a flexure including a high aspect ratio structure according to one embodiment. The use of high aspect ratio structures as described with reference to use with flexures is also applicable to other circuit board technologies, for example, in microcircuits and radio frequency ("RF") circuits.

FIG. 33 illustrates a process for forming a high aspect ratio electroplated structure according to one embodiment. As illustrated, a copper layer 3318 is used as a substrate. However, other conductive materials may be used as a substrate. At 3301, a dielectric layer 3320 is disposed on the copper layer 3318, such as those described herein, marked and stamped. The dielectric layer 3320 may be formed using materials including but not limited to photoimageable or non-photoimageable materials, polymers, ceramics, and other insulating materials. For some embodiments, the copper layer 3318 is a copper alloy layer such as the copper alloy layer described herein. For some embodiments, one or more perforations or through holes 3322 are marked and stamped in the dielectric layer to expose the copper layer 3318. According to some embodiments, dielectric layer 3320 is a photoimageable dielectric material and one or more perforations or vias 3322 are produced using patterning and development techniques including those described herein. Other embodiments include using a laser, drilling, or etching dielectric layer 3320 to produce one or more perforations or vias 3322. For some embodiments, the copper alloy layer has a thickness ranging from 15 microns to 40 microns, inclusive. At 3302, traces 3324 or other conductive features are disposed on the dielectric layer 3320 on the side opposite the copper layer 3318. For some embodiments, a seed layer is sputter-plated using techniques including those described herein to form a pattern on dielectric layer 3320. Other embodiments include using electrodeless plating to form the seed layer. Plating processes such as those described herein are used to form one or more traces 3324 and conductive features to a desired thickness using techniques including those described herein.

At 3304, a conformal plating process such as those described herein is used to build up one or more traces and conductive features to increase the thickness or further enhance the shape of one or more traces and conductive features on the side of the dielectric layer 3320 that opposes the copper layer 3318, using techniques including those described herein. For some embodiments, at 3304, a top plating process such as those described herein is used in addition to the conformal plating process on the side of the dielectric layer 3320 that opposes the copper layer 3318. For some embodiments, a top plating process is used in place of a conformal plating process.

At 3306, a dielectric layer 3326 (e.g., a land layer) is disposed over the one or more traces 3324 and conductive features on the side of the dielectric layer opposite the copper layer 3318 using techniques including those described herein. For some embodiments, a land layer is not included. For example, the one or more traces 3324 and conductive features formed may be coated with a gold layer. At 3308, the copper layer 3318 is etched using techniques including those described herein to form a pattern. For some embodiments, the copper layer 3318 is etched to form the one or more traces 3328 and/or the one or more conductive features.

At 3310, a conformal plating process, such as those described herein, is used to build up one or more traces 3328 and conductive features to increase the thickness or further enhance the shape of the one or more traces 3328 and conductive features formed in the copper layer 3318 using techniques including those described herein. For some embodiments, at 3310, a top plating process, such as those described herein, is used in addition to the conformal plating process on the copper layer 3318. For some embodiments, a top plating process is used instead of a conformal plating process.

At 3312, a dielectric layer 3330 (e.g., a surface layer) is disposed on one or more traces 3328 and conductive features formed from a copper layer 3318 using techniques including those described herein. For some embodiments, a surface layer is not included. For example, one or more traces 3328 and conductive features formed may be coated with a gold layer. For some embodiments, a process is used to fabricate multiple circuits or devices on a single substrate. At 3316, for such embodiments, the circuits or devices are singulated and optionally packaged using techniques including those known in the art. For some embodiments, the circuits and/or devices are singulated using techniques including, but not limited to, laser ablation, fracture, cutting, etching, and the like. For some embodiments, the top layer described herein can be patterned using the patterning techniques described herein. For example, the top layer is applied in a blanket coating. According to some embodiments, the top layer is applied using slot die coating to apply the photoimageable dielectric material. Other techniques may be used, such as rolling, spraying, dry film lamination, or other known methods for applying photoimageable or non-photoimageable materials. If the material is not photoimageable, it can then be patterned using other methods (e.g., laser or etching). For some embodiments, one or both dielectric layers/top layers can be formed with a surface modification, such as to assist in attachment to other structures or substrates. For some embodiments, the surface modification is formed on the dielectric layer/surface layer by texturing or patterning the dielectric layer/surface layer.

At 3314, in some embodiments, terminal pads 3332 such as nickel terminals coated with a gold layer may be formed on substrate 3318 using electrodeless plating and may be provided with solder. According to some embodiments, the surface modification formed on the exposed copper layer (which is disposed on the top and/or bottom surface) is plated using electroless plating or electrolytic plating of nickel, gold or other industry standard surface modification. Additionally, solder may be applied to these areas.

FIG. 34 illustrates a more detailed process similar to that described with reference to FIG. 33 for forming a high aspect ratio electroplated structure according to some embodiments.

FIG. 35 illustrates a coil made using the process described herein. Coil 3501 includes multiple coil segments, for example, three or more coil segments, electrically coupled to form coil 3501. For some embodiments, such as the embodiment illustrated in FIG. 35, the number of turns in the outer coil segment 3504 is the same as the inner coil segment 3502 between the two outer coil segments 3504. For some embodiments, the inner coil segment 3402 includes more turns than the outer coil segment 3504. Other embodiments include multiple coil segments having a subset of the multiple coil segments electrically coupled, for example, with reference to FIG. 35, two of the multiple coil segments are electrically coupled, and the remaining coil segments are not electrically coupled to the other two coil segments. Thus, any combination of any number of coil segments electrically coupled to any of the other coil segments may be included.

Multiple layers including one or more of any of the traces and conductive features fabricated using the techniques described herein may be formed by stacking each layer, and connections between each layer may be made by vias passing through the layers, the vias being filled with a conductive material such as a conductive adhesive.

According to some embodiments, the processes described herein are used to form coils that incorporate other circuit components such as resistance temperature detectors (RTDs), strain gauges, and other sensors.

According to some embodiments, the processes described herein are used to form one or more of any of mechanical structures and electromechanical structures.

Although described with reference to these embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.

202: High aspect ratio electroplating structure 204: High aspect ratio electroplating structure 302: Cross section 304: Magnet 306: Maximum electromagnetic force 308: Coil layer 310: Coil layer 402a: Layer 402b: Layer 402c: Layer 402d: Layer 404: Magnet 602: High aspect ratio electroplating structure 702: High aspect ratio electroplating structure 802a: High aspect ratio electroplating structure 80 2b: High aspect ratio electroplating structure 901: Conductor cross-sectional area 1002: Upper line 1004: Lower line 1102: Trace 1202: High aspect ratio electroplating structure 1204: Texture line 1206: Dielectric 1302: High aspect ratio electroplating structure 1402: Coil 1404: Center coil through hole 1502a: First conductor layer 1502b: Second conductor layer 1504: High aspect ratio Aspect ratio plating structure 1506: High aspect ratio plating structure 1508: First dielectric layer 1510: Second dielectric layer 1602a: First conductor layer 1602b: Second conductor layer 1608: First dielectric layer 1610: Second dielectric layer 1614: First distance 1616: Second distance 1618: Surface 1620: Third distance 1622: First dielectric layer 1624: Base board 1802: trace 1804: substrate 1902: trace 1904: photoresist layer 1906: metal top 2102: deflection piece 2104: high aspect ratio electroplating structure 2106: trace 2302: trace 2304: substrate 2306: photoresist part 2308: metal part 2501: top 2502: inductively coupled coil 2504: high aspect ratio electroplating structure 2604: Back side 2704: Chip 2802: Substrate 2804: Shielding cover 2806: Metal capacitor plate 2808: Base dielectric layer 2810: Shunt capacitor via 2812: Jumper via 2814: Coil 2816: Center connection part 2818: Capacitor connection part 2820: Terminal pad 2822: Surface layer 2824: First welding pad 282 6: Second solder pad 2828: Back dielectric layer 2830: Jumper pattern 2832: Jumper path 2834: Inductive coupling coil 2836: Integrated chip 2900: flexure 2901: Distal part 2902: Ring frame part 2904: Middle part 2906: Gap part 2908: Proximal part 3001: Cover layer 3002: Trace 3002a: Trace 3002b: trace 3002c: trace 3002d: trace 3004: dielectric layer 3006: substrate 3008: gap 3102: mass structure 3202a: metal top portion 3202b: metal top portion 3301: step 3302: step 3304: step 3306: step 3308: step 3310: step 3312: step 3314: Step 3316: Step 3318: Copper layer 3320: Dielectric layer 3322: Perforation or through hole 3324: Trace 3326: Dielectric layer 3328: Trace 3330: Dielectric layer 3332: Terminal pad 3501: Coil 3502: Inner coil segment 3504a: Outer coil segment 3504b: Outer coil segment A: Wire B: Wire C: Wire

Embodiments of the invention are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like reference characters indicate similar elements and in which:

Figure 1 illustrates a coil manufactured using current printed circuit technology;

FIG. 2 illustrates a high-density precision coil including a high aspect ratio electroplated structure according to one embodiment;

FIG. 3 illustrates a graph showing the electromagnetic force generated by a high-density precision coil including a high aspect ratio electroplated structure according to one embodiment;

FIG. 4 illustrates a device including multiple layers of high aspect ratio electroplated structures according to one embodiment configured for use in linear motor type applications;

FIG. 5 illustrates a high aspect ratio electroplated structure according to some embodiments;

FIG. 6 illustrates a high aspect ratio electroplated structure according to some embodiments;

FIG. 7 illustrates a high aspect ratio electroplated structure according to some embodiments;

FIG. 8 illustrates a device having multiple layers of high aspect ratio electroplated structures having a high density cross-sectional area according to some embodiments;

FIG. 9 illustrates a graph indicating SPS coverage during a high current density plating technique and during a low current density plating technique according to one embodiment;

10a - f illustrate a process for forming a high aspect ratio electroplated structure according to one embodiment;

FIG. 11 illustrates a high aspect ratio electroplated structure according to some embodiments;

FIG. 12 illustrates a perspective view of a high aspect ratio electroplated structure according to some embodiments;

FIG. 13a and FIG. 13b illustrate a high-density precision coil formed using a high aspect ratio electroplating structure according to an embodiment;

FIG. 14 illustrates a high aspect ratio electroplated structure including high resolution stacked conductive layers according to one embodiment;

FIG. 15 illustrates a high-density precision coil including a high aspect ratio electroplated structure according to one embodiment;

16a - c illustrate a process for forming a high aspect ratio electroplated structure according to another embodiment;

FIG. 17 illustrates the selective formation of a high aspect ratio electroplated structure according to one embodiment;

FIG. 18 illustrates a perspective view of a high aspect ratio electroplated structure having metal top portions selectively formed on traces according to one embodiment;

FIG. 19 illustrates a hard disk drive suspension flexure including a high aspect ratio electroplated structure according to one embodiment;

FIG. 20 illustrates a cross-sectional view of the hard disk drive suspension bending member illustrated in FIG. 19 ;

21a and 21b illustrate a process for forming a high aspect ratio electroplated structure according to one embodiment using a photoresist during a conformal plating process;

FIG. 22 illustrates exemplary chemistries for forming an initial metal layer process, a standard/conformal plating process, and a top plating process according to various embodiments;

FIG. 23 illustrates a perspective view of the top surface of an inductively coupled coil formed from a high aspect ratio electroplated structure according to one embodiment;

FIG. 24 illustrates a perspective view of the back side of the embodiment of the inductively coupled coil illustrated in FIG. 21 ;

FIG. 25 is a perspective view illustrating a top surface of an inductively coupled coil 2502 coupled to an RF identification chip according to an embodiment;

26a - j illustrate a method of forming an inductively coupled coil formed from a high aspect ratio electroplated structure according to one embodiment;

FIG. 27 illustrates a plan view of a flexure of a suspension of a hard disk drive including a high aspect ratio electroplated structure according to one embodiment;

FIG. 28 illustrates a cross-section of the gap portion of the flexure member at the gap portion, taken along line A as illustrated in FIG. 27 ;

FIG. 29 illustrates a ring frame portion having a mass structure according to one embodiment;

FIG30 illustrates a cross-section of a proximal portion of a flexure including a high aspect ratio electroplated structure according to one embodiment , taken along line B as illustrated in FIG27;

FIG31 illustrates a cross-section of a proximal portion of a flexure including a high aspect ratio structure according to an embodiment, taken along line C as illustrated in FIG27 ;

FIG32 illustrates a plan view of a proximal portion of a flexure including a high aspect ratio structure according to one embodiment ;

FIG. 33 illustrates a process for forming a high aspect ratio electroplated structure according to one embodiment;

FIG. 34 illustrates a more detailed process of the type described with reference to FIG. 33 ; and

FIG. 35 illustrates a coil according to an embodiment manufactured using the process described herein.

3301: Steps

3302: Steps

3304: Steps

3306: Steps

3308: Steps

3310: Steps

3312: Steps

3314: Steps

3316: Steps

3318: Copper layer

3320: Dielectric layer

3322: Perforation or through hole

3324:Traces

3326: Dielectric layer

3328:Traces

3330: Dielectric layer

3332:Terminal pad

Claims (20)

A device including a high aspect ratio electroplated structure, comprising: a conductive substrate etched or electroplated to include at least a first set of traces, wherein the conductive substrate is configured to be disposed in a gap portion of the device; a dielectric layer disposed on the conductive substrate; at least a second set of traces disposed on the dielectric layer; a first metal top portion formed on at least a portion of each trace of the second set of traces to form a first set of high aspect ratio electroplated structures; and a second metal top portion formed on at least a portion of each of the first set of traces to form a second set of high aspect ratio electroplated structures disposed relative to the first set of high aspect ratio electroplated structures, wherein the conductive substrate and the dielectric layer define a gap such that the first metal top portion or the second metal top portion extends over the gap. A device as claimed in claim 1, comprising a second dielectric layer disposed on the first set of high aspect ratio electroplated structures. A device as claimed in claim 1, comprising a third dielectric layer disposed on the second set of high aspect ratio electroplated structures. The device of claim 1, wherein the dielectric layer includes a through hole to electrically couple at least one high aspect ratio plated structure of the first set of high aspect ratio plated structures with at least one high aspect ratio plated structure of the second set of high aspect ratio plated structures. The device of claim 1, wherein the first set of high aspect ratio electroplated structures and the second set of high aspect ratio electroplated structures are configured to form an inductively coupled coil. A device as claimed in claim 1, configured to form a coil having two outer coil segments and an inner coil segment between the two outer coils. A device as claimed in claim 1, comprising a first terminal pad coupled to at least one high aspect ratio electroplated structure of the first set of high aspect ratio electroplated structures. A device as claimed in claim 7, wherein the first terminal pad is a nickel terminal coated with a gold layer. A device as claimed in claim 1, wherein at least a portion of the first set of high aspect ratio electroplated structures is formed using a top plating process. A device as claimed in claim 1, wherein the second set of high aspect ratio electroplated structures is formed by etching the conductive substrate. A device as claimed in claim 1, wherein the first metal top portion is formed using a top plating process. A coil includes: a conductive substrate etched or plated to include a first plurality of traces, wherein the conductive substrate is configured to be disposed in a gap portion; a dielectric layer disposed on the conductive substrate; a second plurality of traces disposed on the dielectric layer; a first metal top portion formed on at least a portion of each of the second plurality of traces to form a first set of high aspect ratio plated structures; and a second metal top portion formed on at least a portion of each of the first plurality of traces to form a second set of high aspect ratio plated structures disposed relative to the first set of high aspect ratio plated structures, wherein the conductive substrate and the dielectric layer define a gap such that the first metal top portion or the second metal top portion extends over the gap. A coil as claimed in claim 12, wherein the dielectric layer includes a through hole to electrically couple at least one high aspect ratio plated structure of the first set of high aspect ratio plated structures with at least one high aspect ratio plated structure of the second set of high aspect ratio plated structures. A coil as claimed in claim 12, wherein the first set of high aspect ratio electroplating structures and the second set of high aspect ratio electroplating structures are used in the first coil section of the coil. The coil of claim 14 includes a third set of high aspect ratio electroplating structures and a fourth set of high aspect ratio electroplating structures for the second coil section of the coil. The coil of claim 15 includes a fifth set of high aspect ratio electroplating structures and a sixth set of high aspect ratio electroplating structures for the third coil section of the coil. A coil as claimed in claim 16, wherein the first coil section is electrically coupled to the second coil section and the third coil section. A coil as claimed in claim 16, wherein the second coil section is electrically coupled to the third coil section. A coil as claimed in claim 12, wherein the second set of high aspect ratio electroplated structures is formed by etching the conductive substrate. A coil as claimed in claim 19, wherein at least a portion of the second set of high aspect ratio electroplated structures is formed using a top plating process.