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TWI866619B - Power distribution board - Google Patents

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TWI866619B
TWI866619B TW112144410A TW112144410A TWI866619B TW I866619 B TWI866619 B TW I866619B TW 112144410 A TW112144410 A TW 112144410A TW 112144410 A TW112144410 A TW 112144410A TW I866619 B TWI866619 B TW I866619B
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chip
voltage
distribution board
power
power distribution
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TW112144410A
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TW202522156A (en
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宋文文
林宏州
陳俞帆
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英業達股份有限公司
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Abstract

A power distribution board includes: a complex programmable logic device (CPLD), a first buck chip and a second buck chip. The first buck chip is connected to the CPLD. The first buck chip is configured to receive a first direct-current (DC) voltage, lower the first DC voltage to a first voltage, and supply the first voltage to the CPLD. The second buck chip is configured to receive a second DC voltage, lower the second DC voltage to a second voltage, and supply the second voltage to a power module. The first DC voltage and the second DC voltage has a same voltage value.

Description

電源分配板Power distribution board

本發明係關於一種電源分配板。 The present invention relates to a power distribution board.

在目前的沉浸式伺服器多是以220伏特的交流電經電力供應單元(power supply unit,PSU)提供電力給伺服器。然而,此供電方式會造成很高的電力損耗。 Most current immersive servers use 220 volt AC power through a power supply unit (PSU) to provide power to the server. However, this power supply method will cause high power loss.

鑒於上述,本發明提供一種解決上述問題的電源分配板。 In view of the above, the present invention provides a power distribution board that solves the above problems.

依據本發明一實施例的電源分配板,包含:複雜可程式邏輯裝置、第一降壓晶片以及第二降壓晶片。第一降壓晶片連接於複雜可程式邏輯裝置,第一降壓晶片用於接收第一直流電壓,將第一直流電壓降低至第一電壓,及供應第一電壓至複雜可程式邏輯裝置。第二降壓晶片用於接收第二直流電壓,將第二直流電壓降低至第二電壓,及供應第二電壓至功率模組。第一直流電壓及第二直流電壓的電壓值相同。 According to an embodiment of the present invention, a power distribution board includes: a complex programmable logic device, a first buck chip and a second buck chip. The first buck chip is connected to the complex programmable logic device, and the first buck chip is used to receive a first DC voltage, reduce the first DC voltage to a first voltage, and supply the first voltage to the complex programmable logic device. The second buck chip is used to receive a second DC voltage, reduce the second DC voltage to a second voltage, and supply the second voltage to the power module. The voltage values of the first DC voltage and the second DC voltage are the same.

綜上所述,相較於以220伏特的交流電經電力供應單元提供電力給伺服器,依據本發明一或多個實施例的電源分配板可有效降低電力傳輸及轉換的過程中產生的功耗。 In summary, compared to using 220 volt AC power to provide power to the server via a power supply unit, the power distribution board according to one or more embodiments of the present invention can effectively reduce the power consumption generated during the power transmission and conversion process.

以上之關於本揭露內容之說明及以下之實施方式之說明係用以示範與解釋本發明之精神與原理,並且提供本發明之專利申請範圍更進一步之解釋。 The above description of the disclosed content and the following description of the implementation method are used to demonstrate and explain the spirit and principle of the present invention, and provide a further explanation of the scope of the patent application of the present invention.

以下在實施方式中詳細敘述本發明之詳細特徵以及優點,其內容足以使任何熟習相關技藝者了解本發明之技術內容並據以實施,且根據本說明書所揭露之內容、申請專利範圍及圖式,任何熟習相關技藝者可輕易地理解本發明相關之目的及優點。以下之實施例係進一步詳細說明本發明之觀點,但非以任何觀點限制本發明之範疇。 The detailed features and advantages of the present invention are described in detail in the following implementation method. The content is sufficient for anyone familiar with the relevant technology to understand the technical content of the present invention and implement it accordingly. According to the content disclosed in this specification, the scope of the patent application and the drawings, anyone familiar with the relevant technology can easily understand the relevant purposes and advantages of the present invention. The following embodiments are to further illustrate the viewpoints of the present invention, but do not limit the scope of the present invention by any viewpoint.

請參考圖1,其中圖1係依據本發明第一實施例所繪示的電源分配板的方塊圖。如圖1所示,電源分配板1包括第一降壓晶片11、第二降壓晶片12以及複雜可程式邏輯裝置13。第一降壓晶片11連 接於複雜可程式邏輯裝置13及直流電源A1。第二降壓晶片12連接於直流電源A1及功率模組A2。 Please refer to FIG. 1, which is a block diagram of a power distribution board according to the first embodiment of the present invention. As shown in FIG. 1, the power distribution board 1 includes a first buck chip 11, a second buck chip 12 and a complex programmable logic device 13. The first buck chip 11 is connected to the complex programmable logic device 13 and the DC power supply A1. The second buck chip 12 is connected to the DC power supply A1 and the power module A2.

第一降壓晶片11可為降壓轉換器(buck converter)。第二降壓晶片12的輸入電壓可為40伏特到60伏特,輸出電壓可為12伏特,輸出功率可為1600瓦。舉例而言,第二降壓晶片12可為電源模組(power module),其型號可為Q50SN120A4RKDS。第一降壓晶片11用於從直流電源A1接收第一直流電壓,將第一直流電壓降低至第一電壓,及供應第一電壓至複雜可程式邏輯裝置13。第二降壓晶片12用於從直流電源A1接收第二直流電壓,將第二直流電壓降低至第二電壓,及供應第二電壓至功率模組A2。功率模組A2可為用於提供電力給伺服器的電力連接器。第一直流電壓及第二直流電壓的電壓值相同。舉例而言,第一直流電壓及第二直流電壓的電壓值可為48伏特到54伏特。進一步而言,第一直流電壓及第二直流電壓的電壓值可為48伏特。第一電壓可為待機電壓,例如3.3伏特。第二電壓可為12伏特。並且,第二降壓晶片12可包括多個子晶片,各子晶片連接於各自的功率模組及輸出第二電壓給各自的功率模組,且子晶片可提供總共3200瓦的功率。 The first buck chip 11 may be a buck converter. The input voltage of the second buck chip 12 may be 40 volts to 60 volts, the output voltage may be 12 volts, and the output power may be 1600 watts. For example, the second buck chip 12 may be a power module, and its model may be Q50SN120A4RKDS. The first buck chip 11 is used to receive a first DC voltage from a DC power source A1, reduce the first DC voltage to a first voltage, and supply the first voltage to a complex programmable logic device 13. The second buck chip 12 is used to receive a second DC voltage from a DC power source A1, reduce the second DC voltage to a second voltage, and supply the second voltage to a power module A2. The power module A2 may be a power connector for providing power to the server. The voltage values of the first DC voltage and the second DC voltage are the same. For example, the voltage values of the first DC voltage and the second DC voltage may be 48 volts to 54 volts. Further, the voltage values of the first DC voltage and the second DC voltage may be 48 volts. The first voltage may be a standby voltage, such as 3.3 volts. The second voltage may be 12 volts. Furthermore, the second step-down chip 12 may include a plurality of sub-chips, each of which is connected to its own power module and outputs a second voltage to its own power module, and the sub-chips may provide a total of 3200 watts of power.

相較於以220伏特的交流電經電力供應單元(power supply unit,PSU)提供電力給伺服器,透過以上架構,可有效降低電力傳輸及轉換的過程中產生的功耗。 Compared to using 220 volt AC to provide power to the server through a power supply unit (PSU), the above architecture can effectively reduce the power consumption generated during power transmission and conversion.

請參考圖2,其中圖2係依據本發明第二實施例所繪示的電源分配板的方塊圖。如圖2所示,電源分配板2包括保險絲控制晶片20、第一降壓晶片21、第二降壓晶片22以及複雜可程式邏輯裝置23。 保險絲控制晶片20連接於直流電源A1、第一降壓晶片21及第二降壓晶片22。第一降壓晶片21連接於複雜可程式邏輯裝置23。第二降壓晶片22連接於功率模組A2。電源分配板2的第一降壓晶片21、第二降壓晶片22以及複雜可程式邏輯裝置23的實現方式可與圖1的第一降壓晶片11、第二降壓晶片12以及複雜可程式邏輯裝置13相同,故不於此贅述。 Please refer to FIG. 2, which is a block diagram of a power distribution board according to the second embodiment of the present invention. As shown in FIG. 2, the power distribution board 2 includes a fuse control chip 20, a first buck chip 21, a second buck chip 22, and a complex programmable logic device 23. The fuse control chip 20 is connected to the DC power supply A1, the first buck chip 21, and the second buck chip 22. The first buck chip 21 is connected to the complex programmable logic device 23. The second buck chip 22 is connected to the power module A2. The implementation of the first buck chip 21, the second buck chip 22 and the complex programmable logic device 23 of the power distribution board 2 can be the same as the first buck chip 11, the second buck chip 12 and the complex programmable logic device 13 in Figure 1, so they will not be described here in detail.

保險絲控制晶片20用於從直流電源A1接收電力,及基於接收的電力分別提供第一直流電壓及第二直流電壓至第一降壓晶片21及第二降壓晶片22。保險絲控制晶片20例如為熱插拔電壓控制器。此外,保險絲控制晶片20與直流電源A1之間可更設置卡扣螺釘固定器(clip screw hold)。 The fuse control chip 20 is used to receive power from the DC power source A1, and provide a first DC voltage and a second DC voltage to the first step-down chip 21 and the second step-down chip 22 respectively based on the received power. The fuse control chip 20 is, for example, a hot-swap voltage controller. In addition, a clip screw hold can be further provided between the fuse control chip 20 and the DC power source A1.

舉例而言,保險絲控制晶片20從直流電源A1接收電力後,將大部分的電力作為第二直流電壓輸出至第二降壓晶片22,以對主板供電,及將剩餘的電力作為第一直流電壓輸出給第一降壓晶片21。舉例而言,第一電壓可為待機電壓,例如3.3伏特。 For example, after receiving power from the DC power source A1, the fuse control chip 20 outputs most of the power as the second DC voltage to the second buck chip 22 to power the mainboard, and outputs the remaining power as the first DC voltage to the first buck chip 21. For example, the first voltage can be a standby voltage, such as 3.3 volts.

請參考圖3,其中圖3係依據本發明第三實施例所繪示的電源分配板的方塊圖。如圖3所示,電源分配板3包括保險絲控制晶片30、第一降壓晶片31、第二降壓晶片32、複雜可程式邏輯裝置33以及旁帶連接器(sideband connector)34。保險絲控制晶片30連接於直流電源A1、第一降壓晶片31、第二降壓晶片32以及旁帶連接器34。第一降壓晶片31連接於複雜可程式邏輯裝置33。第二降壓晶片32連接於功率模組A2。電源分配板3的保險絲控制晶片30、第一降壓晶片31、 第二降壓晶片32以及複雜可程式邏輯裝置33的實現方式可與圖2的保險絲控制晶片20、第一降壓晶片21、第二降壓晶片22以及複雜可程式邏輯裝置23相同,故不於此贅述。 Please refer to FIG. 3, which is a block diagram of a power distribution board according to the third embodiment of the present invention. As shown in FIG. 3, the power distribution board 3 includes a fuse control chip 30, a first buck chip 31, a second buck chip 32, a complex programmable logic device 33 and a sideband connector 34. The fuse control chip 30 is connected to the DC power supply A1, the first buck chip 31, the second buck chip 32 and the sideband connector 34. The first buck chip 31 is connected to the complex programmable logic device 33. The second buck chip 32 is connected to the power module A2. The fuse control chip 30, the first step-down chip 31, the second step-down chip 32 and the complex programmable logic device 33 of the power distribution board 3 can be implemented in the same way as the fuse control chip 20, the first step-down chip 21, the second step-down chip 22 and the complex programmable logic device 23 in FIG. 2, so they are not described here in detail.

旁帶連接器34連接於複雜可程式邏輯裝置33,及用於連接主板端的基板管理控制器A3至保險絲控制晶片30、第一降壓晶片31、第二降壓晶片32及複雜可程式邏輯裝置33。旁帶連接器34可以透過積體電路之間介面連接於複雜可程式邏輯裝置33,及透過積體電路之間介面將基板管理控制器A3連接至保險絲控制晶片30、第一降壓晶片31及第二降壓晶片32。據此,電源分配板3的運作狀態可經由旁帶連接器34輸出至主板端的基板管理控制器A3。所述運作狀態可包括保險絲控制晶片30、第一降壓晶片31、第二降壓晶片32及複雜可程式邏輯裝置33的功耗、電壓及電流資料等。透過旁帶連接器34連接於複雜可程式邏輯裝置33,複雜可程式邏輯裝置33的暫存器(register)可被基板管理控制器A3更新。 The sideband connector 34 is connected to the complex programmable logic device 33, and is used to connect the baseboard management controller A3 on the main board to the fuse control chip 30, the first step-down chip 31, the second step-down chip 32 and the complex programmable logic device 33. The sideband connector 34 can be connected to the complex programmable logic device 33 through the interface between the integrated circuits, and connect the baseboard management controller A3 to the fuse control chip 30, the first step-down chip 31 and the second step-down chip 32 through the interface between the integrated circuits. Accordingly, the operating status of the power distribution board 3 can be output to the baseboard management controller A3 on the main board through the sideband connector 34. The operating status may include power consumption, voltage and current data of the fuse control chip 30, the first buck chip 31, the second buck chip 32 and the complex programmable logic device 33. The register of the complex programmable logic device 33 can be updated by the baseboard management controller A3 by connecting to the complex programmable logic device 33 through the sideband connector 34.

另外,第一降壓晶片31及第二降壓晶片32更可用於透過旁帶連接器34輸出電源良好(power good)訊號、警告(alert)訊號、直流電源良好(DCOK)訊號、交流電源良好訊號(ACOK)中的至少一者至複雜可程式邏輯裝置33,以供複雜可程式邏輯裝置33進行監控。 In addition, the first buck chip 31 and the second buck chip 32 can be used to output at least one of a power good signal, an alert signal, a DC power good (DCOK) signal, and an AC power good (ACOK) signal to the complex programmable logic device 33 through the sideband connector 34 for monitoring by the complex programmable logic device 33.

請參考圖4,其中圖4係依據本發明第四實施例所繪示的電源分配板的方塊圖。如圖4所示,電源分配板4包括保險絲控制晶片40、第一降壓晶片41、第二降壓晶片42、複雜可程式邏輯裝置43、旁 帶連接器44、溫度感測器45、現場可更換單元(field replaceable unit,FRU)46以及通用平行輸入/輸出擴展(general purpose parallel input/output expansion)晶片47。保險絲控制晶片40連接於直流電源A1、第一降壓晶片41、第二降壓晶片42以及旁帶連接器44。第一降壓晶片41連接於複雜可程式邏輯裝置43。第二降壓晶片42連接於功率模組A2。電源分配板4的保險絲控制晶片40、第一降壓晶片41、第二降壓晶片42以及複雜可程式邏輯裝置43的實現方式可與圖3的保險絲控制晶片30、第一降壓晶片31、第二降壓晶片32以及複雜可程式邏輯裝置33相同,故不於此贅述。 Please refer to FIG. 4, which is a block diagram of a power distribution board according to the fourth embodiment of the present invention. As shown in FIG. 4, the power distribution board 4 includes a fuse control chip 40, a first buck chip 41, a second buck chip 42, a complex programmable logic device 43, a sideband connector 44, a temperature sensor 45, a field replaceable unit (FRU) 46, and a general purpose parallel input/output expansion chip 47. The fuse control chip 40 is connected to the DC power supply A1, the first buck chip 41, the second buck chip 42, and the sideband connector 44. The first buck chip 41 is connected to the complex programmable logic device 43. The second buck chip 42 is connected to the power module A2. The implementation of the fuse control chip 40, the first buck chip 41, the second buck chip 42 and the complex programmable logic device 43 of the power distribution board 4 can be the same as the fuse control chip 30, the first buck chip 31, the second buck chip 32 and the complex programmable logic device 33 in Figure 3, so it is not described here in detail.

旁帶連接器44更透過積體電路之間介面連接基板管理控制器A3至溫度感測器45、現場可更換單元46及通用平行輸入/輸出擴展晶片47。溫度感測器45、現場可更換單元46及通用平行輸入/輸出擴展晶片47皆為選擇性設置的元件。旁帶連接器44可以是連接基板管理控制器A3至溫度感測器45、現場可更換單元46及通用平行輸入/輸出擴展晶片47中的至少一者。 The sideband connector 44 further connects the baseboard management controller A3 to the temperature sensor 45, the field replaceable unit 46 and the universal parallel input/output expansion chip 47 through the interface between the integrated circuits. The temperature sensor 45, the field replaceable unit 46 and the universal parallel input/output expansion chip 47 are all selectively arranged components. The sideband connector 44 can be connected to at least one of the baseboard management controller A3 to the temperature sensor 45, the field replaceable unit 46 and the universal parallel input/output expansion chip 47.

溫度感測器45可用於感測電源分配板4上的一或多個元件的溫度。通用平行輸入/輸出擴展晶片47可經由旁帶連接器44將資料寫入現場可更換單元46或從現場可更換單元46讀取資料。 The temperature sensor 45 can be used to sense the temperature of one or more components on the power distribution board 4. The universal parallel input/output expansion chip 47 can write data to the field replaceable unit 46 or read data from the field replaceable unit 46 via the sideband connector 44.

第一降壓晶片41可更另外直接連接於溫度感測器45、現場可更換單元46及通用平行輸入/輸出擴展晶片47,以提供第一電壓予溫度感測器45、現場可更換單元46及通用平行輸入/輸出擴展晶片47。 The first step-down chip 41 can be directly connected to the temperature sensor 45, the field replaceable unit 46 and the universal parallel input/output expansion chip 47 to provide a first voltage to the temperature sensor 45, the field replaceable unit 46 and the universal parallel input/output expansion chip 47.

此外,通用平行輸入/輸出擴展晶片47可以是經由旁帶連接器44連接複雜可程式邏輯裝置43執行不中斷(hitless)的引腳。因此,當基板管理控制器A3例如透過區域網路(local area network,LAN)更新複雜可程式邏輯裝置43的韌體時,可使複雜可程式邏輯裝置43不會斷電。 In addition, the universal parallel input/output expansion chip 47 can be connected to the hitless pins of the complex programmable logic device 43 via the sideband connector 44. Therefore, when the baseboard management controller A3 updates the firmware of the complex programmable logic device 43 through the local area network (LAN), the complex programmable logic device 43 will not be powered off.

請接著參考圖5,其中圖5係依據本發明第五實施例所繪示的電源分配板的方塊圖。如圖5所示,電源分配板5包括第一降壓晶片51、第二降壓晶片52、複雜可程式邏輯裝置53、溫度感測器54、現場可更換單元55以及通用平行輸入/輸出擴展晶片56。第一降壓晶片51連接於直流電源A1、複雜可程式邏輯裝置53、溫度感測器54、現場可更換單元55以及通用平行輸入/輸出擴展晶片56。第二降壓晶片52連接於直流電源A1及功率模組A2。電源分配板5的第一降壓晶片51、第二降壓晶片52以及複雜可程式邏輯裝置53的實現方式可與圖1的第一降壓晶片11、第二降壓晶片12以及複雜可程式邏輯裝置13相同,故不於此贅述。 Please refer to FIG. 5, which is a block diagram of a power distribution board according to the fifth embodiment of the present invention. As shown in FIG. 5, the power distribution board 5 includes a first buck chip 51, a second buck chip 52, a complex programmable logic device 53, a temperature sensor 54, a field replaceable unit 55, and a universal parallel input/output expansion chip 56. The first buck chip 51 is connected to the DC power supply A1, the complex programmable logic device 53, the temperature sensor 54, the field replaceable unit 55, and the universal parallel input/output expansion chip 56. The second buck chip 52 is connected to the DC power supply A1 and the power module A2. The implementation of the first buck chip 51, the second buck chip 52 and the complex programmable logic device 53 of the power distribution board 5 can be the same as the first buck chip 11, the second buck chip 12 and the complex programmable logic device 13 in Figure 1, so they will not be described here in detail.

溫度感測器54、現場可更換單元55以及通用平行輸入/輸出擴展晶片56可分別與圖4的溫度感測器45、現場可更換單元46及通用平行輸入/輸出擴展晶片47相同。 The temperature sensor 54, the field replaceable unit 55, and the universal parallel input/output expansion chip 56 may be respectively the same as the temperature sensor 45, the field replaceable unit 46, and the universal parallel input/output expansion chip 47 of FIG. 4.

溫度感測器54、現場可更換單元55以及通用平行輸入/輸出擴展晶片56皆為選擇性設置的元件。第一降壓晶片51可以是連接於溫度感測器54、現場可更換單元55以及通用平行輸入/輸出擴展晶片56中的至少一者。第一降壓晶片51在將第一直流電壓降低至第一電壓 後,可更將第一電壓供應至溫度感測器54、現場可更換單元55以及通用平行輸入/輸出擴展晶片56中的一或多者。舉例而言,溫度感測器54、現場可更換單元55以及通用平行輸入/輸出擴展晶片56的每一者接收的第一電壓可為待機電壓,例如3.3伏特。 The temperature sensor 54, the field replaceable unit 55, and the universal parallel input/output expansion chip 56 are all selectively arranged components. The first buck chip 51 can be connected to at least one of the temperature sensor 54, the field replaceable unit 55, and the universal parallel input/output expansion chip 56. After reducing the first DC voltage to the first voltage, the first buck chip 51 can further supply the first voltage to one or more of the temperature sensor 54, the field replaceable unit 55, and the universal parallel input/output expansion chip 56. For example, the first voltage received by each of the temperature sensor 54, the field replaceable unit 55, and the universal parallel input/output expansion chip 56 can be a standby voltage, such as 3.3 volts.

請接著參考圖6,其中圖6係依據本發明第六實施例所繪示的電源分配板的方塊圖。如圖6所示,電源分配板6包括第一降壓晶片61、第二降壓晶片62、複雜可程式邏輯裝置63、電子式可清除程式化唯讀記憶體(electrically erasable programmable read-only memory,EEPROM)64以及發光元件65。第一降壓晶片61連接於直流電源A1、複雜可程式邏輯裝置63及電子式可清除程式化唯讀記憶體64。第二降壓晶片62連接於直流電源A1及功率模組A2。複雜可程式邏輯裝置63連接於電子式可清除程式化唯讀記憶體64及發光元件65。發光元件65為可用於發出不同顏色的光的元件,例如發光二極體。電源分配板6的第一降壓晶片61、第二降壓晶片62以及複雜可程式邏輯裝置63的實現方式可與圖1的第一降壓晶片11、第二降壓晶片12以及複雜可程式邏輯裝置13相同,故不於此贅述。 Please refer to FIG. 6, which is a block diagram of a power distribution board according to the sixth embodiment of the present invention. As shown in FIG. 6, the power distribution board 6 includes a first buck chip 61, a second buck chip 62, a complex programmable logic device 63, an electrically erasable programmable read-only memory (EEPROM) 64, and a light-emitting element 65. The first buck chip 61 is connected to the DC power supply A1, the complex programmable logic device 63, and the EEPROM 64. The second buck chip 62 is connected to the DC power supply A1 and the power module A2. The complex programmable logic device 63 is connected to the electronic erasable programmable read-only memory 64 and the light-emitting element 65. The light-emitting element 65 is an element that can be used to emit light of different colors, such as a light-emitting diode. The first buck chip 61, the second buck chip 62 and the complex programmable logic device 63 of the power distribution board 6 can be implemented in the same way as the first buck chip 11, the second buck chip 12 and the complex programmable logic device 13 in Figure 1, so they are not described here in detail.

具體而言,第一降壓晶片61可提供第一電壓給電子式可清除程式化唯讀記憶體64,其中第一電壓可為待機電壓,例如3.3伏特。電子式可清除程式化唯讀記憶體64可以是透過積體電路之間介面連接複雜可程式邏輯裝置63。電子式可清除程式化唯讀記憶體64可用於儲存複雜可程式邏輯裝置63的韌體備份。因此,當複雜可程式邏輯裝置63被更新(例如,被前述的基板管理控制器更新)時,若更新過程 突然出現異常而導致更新暫停或失敗,可藉由讀取複雜可程式邏輯裝置63的韌體備份,以確保複雜可程式邏輯裝置63正常運作。並且,複雜可程式邏輯裝置63可控制發光元件65發出對應複雜可程式邏輯裝置63的狀態的光線。例如,正常運作狀態對應綠色光。因此,當複雜可程式邏輯裝置63基於前述韌體備份而正常運作時,複雜可程式邏輯裝置63可控制發光元件65發出綠色光。 Specifically, the first step-down chip 61 can provide a first voltage to the EEPROM 64, wherein the first voltage can be a standby voltage, such as 3.3 volts. The EEPROM 64 can be connected to the CPLD 63 through an interface between integrated circuits. The EEPROM 64 can be used to store a firmware backup of the CPLD 63. Therefore, when the CPLD 63 is updated (for example, by the aforementioned BMC), if an abnormality suddenly occurs during the update process, resulting in the update being suspended or failing, the CPLD 63 can be ensured to operate normally by reading the firmware backup of the CPLD 63. Furthermore, the CPLD 63 can control the light emitting element 65 to emit light corresponding to the state of the CPLD 63. For example, the normal operation state corresponds to green light. Therefore, when the complex programmable logic device 63 operates normally based on the aforementioned firmware backup, the complex programmable logic device 63 can control the light-emitting element 65 to emit green light.

請接著參考圖7,其中圖7係依據本發明第七實施例所繪示的電源分配板的方塊圖。如圖7所示,電源分配板7包括第一降壓晶片71、第二降壓晶片72以及複雜可程式邏輯裝置73。第一降壓晶片71連接於直流電源A1及複雜可程式邏輯裝置73。第二降壓晶片72連接於直流電源A1及功率模組A2。 Please refer to FIG. 7, which is a block diagram of a power distribution board according to the seventh embodiment of the present invention. As shown in FIG. 7, the power distribution board 7 includes a first buck chip 71, a second buck chip 72, and a complex programmable logic device 73. The first buck chip 71 is connected to the DC power supply A1 and the complex programmable logic device 73. The second buck chip 72 is connected to the DC power supply A1 and the power module A2.

電源分配板7的第一降壓晶片71以及複雜可程式邏輯裝置73的實現方式可與圖1的第一降壓晶片11以及複雜可程式邏輯裝置13相同,故不於此贅述。 The implementation of the first buck chip 71 and the complex programmable logic device 73 of the power distribution board 7 can be the same as the first buck chip 11 and the complex programmable logic device 13 in Figure 1, so they will not be described here in detail.

第二降壓晶片72可包括連接器721。連接器721用於接收關聯於第二降壓晶片72的韌體更新指令及韌體除錯(debug)指令的至少一者。韌體更新指令及韌體除錯指令可以是使用者給的指令。韌體更新指令可以用於更新第二降壓晶片72的韌體,韌體除錯指令可以用於除錯第二降壓晶片72的韌體。 The second step-down chip 72 may include a connector 721. The connector 721 is used to receive at least one of a firmware update instruction and a firmware debug instruction associated with the second step-down chip 72. The firmware update instruction and the firmware debug instruction may be instructions given by a user. The firmware update instruction may be used to update the firmware of the second step-down chip 72, and the firmware debug instruction may be used to debug the firmware of the second step-down chip 72.

需特別說明的是,本發明的電源分配板除了透過以上的多個實施例實現之外,更可透過以上的部分實施例的組合或所有實施例的組合實現。並且,本發明的電源分配板可應用於沉浸式伺服器。 It should be noted that the power distribution board of the present invention can be implemented through the above multiple embodiments, as well as a combination of some or all of the above embodiments. Furthermore, the power distribution board of the present invention can be applied to immersive servers.

綜上所述,相較於以220伏特的交流電經電力供應單元提供電力給伺服器,依據本發明一或多個實施例的電源分配板可有效降低電力傳輸及轉換的過程中產生的功耗。此外,透過積體電路之間介面將基板管理控制器連接至保險絲控制晶片,電源分配板的運作狀態可被輸出至主板端的基板管理控制器,以供基板管理控制器監控電源分配板的運作狀態。透過使通用平行輸入/輸出擴展晶片連接複雜可程式邏輯裝置執行不中斷的引腳,可避免複雜可程式邏輯裝置在被更新時不斷電。透過電子式可清除程式化唯讀記憶體儲存複雜可程式邏輯裝置的韌體備份,即使更新過程發生異常,仍可確保複雜可程式邏輯裝置正常運作。 In summary, compared with using 220 volts of alternating current to provide power to the server through a power supply unit, the power distribution board according to one or more embodiments of the present invention can effectively reduce the power consumption generated in the process of power transmission and conversion. In addition, by connecting the baseboard management controller to the fuse control chip through the interface between the integrated circuits, the operating status of the power distribution board can be output to the baseboard management controller on the main board side, so that the baseboard management controller can monitor the operating status of the power distribution board. By connecting the universal parallel input/output expansion chip to the pins of the complex programmable logic device without interruption, the complex programmable logic device can be prevented from being powered off when being updated. By storing the firmware backup of the CPLD in electronically erasable read-only memory, the CPLD can still operate normally even if an error occurs during the update process.

雖然本發明以前述之實施例揭露如上,然其並非用以限定本發明。在不脫離本發明之精神和範圍內,所為之更動與潤飾,均屬本發明之專利保護範圍。關於本發明所界定之保護範圍請參考所附之申請專利範圍。 Although the present invention is disclosed as above by the aforementioned embodiments, it is not intended to limit the present invention. Any changes and modifications made within the spirit and scope of the present invention are within the scope of patent protection of the present invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

1,2,3,4,5,6,7:電源分配板 1,2,3,4,5,6,7: Power distribution board

11,21,31,41,51,61,71:第一降壓晶片 11,21,31,41,51,61,71: The first step-down chip

12,22,32,42,52,62,72:第二降壓晶片 12,22,32,42,52,62,72: Second step-down chip

13,23,33,43,53,63,73:複雜可程式邏輯裝置 13,23,33,43,53,63,73: Complex programmable logic devices

20,30,40:保險絲控制晶片 20,30,40: Fuse control chip

34,44:旁帶連接器 34,44: Sideband connector

45,54:溫度感測器 45,54: Temperature sensor

46,55:現場可更換單元 46,55: Field replaceable unit

47,56:通用平行輸入/輸出擴展晶片 47,56: Universal parallel input/output expansion chip

64:電子式可清除程式化唯讀記憶體 64: Electronically erasable programmable read-only memory

65:發光元件 65: Light-emitting element

721:連接器 721: Connector

A1:直流電源 A1: DC power supply

A2:功率模組 A2: Power module

A3:基板管理控制器 A3: Baseboard management controller

圖1係依據本發明第一實施例所繪示的電源分配板的方塊圖。 FIG1 is a block diagram of a power distribution board according to the first embodiment of the present invention.

圖2係依據本發明第二實施例所繪示的電源分配板的方塊圖。 Figure 2 is a block diagram of a power distribution board according to the second embodiment of the present invention.

圖3係依據本發明第三實施例所繪示的電源分配板的方塊圖。 FIG3 is a block diagram of a power distribution board according to the third embodiment of the present invention.

圖4係依據本發明第四實施例所繪示的電源分配板的方塊圖。 FIG4 is a block diagram of a power distribution board according to the fourth embodiment of the present invention.

圖5係依據本發明第五實施例所繪示的電源分配板的方塊圖。 FIG5 is a block diagram of a power distribution board according to the fifth embodiment of the present invention.

圖6係依據本發明第六實施例所繪示的電源分配板的方塊圖。 FIG6 is a block diagram of a power distribution board according to the sixth embodiment of the present invention.

圖7係依據本發明第七實施例所繪示的電源分配板的方塊圖。 FIG. 7 is a block diagram of a power distribution board according to the seventh embodiment of the present invention.

1:電源分配板 1: Power distribution board

11:第一降壓晶片 11: The first step-down chip

12:第二降壓晶片 12: Second step-down chip

13:複雜可程式邏輯裝置 13: Complex programmable logic device

A1:直流電源 A1: DC power supply

A2:功率模組 A2: Power module

Claims (8)

一種電源分配板,包含:一複雜可程式邏輯裝置;一第一降壓晶片,連接於該複雜可程式邏輯裝置,該第一降壓晶片用於接收一第一直流電壓,將該第一直流電壓降低至一第一電壓,及供應該第一電壓至該複雜可程式邏輯裝置;以及一第二降壓晶片,用於接收一第二直流電壓,將該第二直流電壓降低至一第二電壓,及供應該第二電壓至一功率模組,其中該第一直流電壓及該第二直流電壓的電壓值相同,其中該電源分配板更包含:一保險絲控制晶片,連接於一直流電源、該第一降壓晶片及該第二降壓晶片,該保險絲控制晶片用於從該直流電源接收電力,及基於該電力分別提供該第一直流電壓及該第二直流電壓至該第一降壓晶片及該第二降壓晶片;以及一旁帶連接器,用於連接一基板管理控制器至該保險絲控制晶片、該第一降壓晶片及該第二降壓晶片。 A power distribution board includes: a complex programmable logic device; a first buck chip connected to the complex programmable logic device, the first buck chip is used to receive a first DC voltage, reduce the first DC voltage to a first voltage, and supply the first voltage to the complex programmable logic device; and a second buck chip is used to receive a second DC voltage, reduce the second DC voltage to a second voltage, and supply the second voltage to a power module, wherein the first DC voltage and the second DC voltage are The voltage value of the DC voltage is the same, wherein the power distribution board further includes: a fuse control chip connected to a DC power source, the first step-down chip and the second step-down chip, the fuse control chip is used to receive power from the DC power source, and provide the first DC voltage and the second DC voltage to the first step-down chip and the second step-down chip respectively based on the power; and a sideband connector, used to connect a baseboard management controller to the fuse control chip, the first step-down chip and the second step-down chip. 如請求項1所述的電源分配板,其中該旁帶連接器係透過積體電路之間介面連接該基板管理控制器至該保險絲控制晶片、該第一降壓晶片及該第二降壓晶片。 The power distribution board as described in claim 1, wherein the sideband connector connects the baseboard management controller to the fuse control chip, the first buck chip and the second buck chip through an interface between integrated circuits. 如請求項1所述的電源分配板,其中該旁帶連接器係透過積體電路之間介面連接該基板管理控制器至一溫度感測器、一現場可更換單元及一通用平行輸入/輸出擴展晶片的至少一者。 A power distribution board as claimed in claim 1, wherein the sideband connector connects the baseboard management controller to at least one of a temperature sensor, a field replaceable unit and a universal parallel input/output expansion chip through an interface between integrated circuits. 如請求項1所述的電源分配板,更包含:一電子式可清除程式化唯讀記憶體,透過積體電路之間介面連接該複雜可程式邏輯裝置,該電子式可清除程式化唯讀記憶體用於儲存該複雜可程式邏輯裝置的韌體備份。 The power distribution board as described in claim 1 further comprises: an electronic erasable programmable read-only memory connected to the complex programmable logic device through an interface between integrated circuits, and the electronic erasable programmable read-only memory is used to store the firmware backup of the complex programmable logic device. 如請求項1所述的電源分配板,其中該第一降壓晶片更用於供應該第一電壓至一溫度感測器、一現場可更換單元及一通用平行輸入/輸出擴展晶片的至少一者,其中該第一電壓是待機電壓。 A power distribution board as described in claim 1, wherein the first step-down chip is further used to supply the first voltage to at least one of a temperature sensor, a field replaceable unit, and a universal parallel input/output expansion chip, wherein the first voltage is a standby voltage. 如請求項1所述的電源分配板,其中該第二降壓晶片更連接於該複雜可程式邏輯裝置,該第一降壓晶片及該第二降壓晶片更分別用於輸出一電源良好訊號、一警告訊號、一直流電源良好訊號、一交流電源良好訊號中的至少一者至該複雜可程式邏輯裝置。 The power distribution board as described in claim 1, wherein the second buck chip is further connected to the complex programmable logic device, and the first buck chip and the second buck chip are respectively used to output at least one of a power good signal, a warning signal, a DC power good signal, and an AC power good signal to the complex programmable logic device. 如請求項1所述的電源分配板,其中該第二降壓晶片包含一連接器,用於接收關聯於該第二降壓晶片的一韌體更新指令及一韌體除錯指令的至少一者。 A power distribution board as described in claim 1, wherein the second buck chip includes a connector for receiving at least one of a firmware update command and a firmware debug command associated with the second buck chip. 如請求項1所述的電源分配板,其中該複雜可程式邏輯裝置更連接於一發光元件,用於發出對應該複雜可程式邏輯裝置的狀態的光線。 A power distribution board as described in claim 1, wherein the CPLD is further connected to a light-emitting element for emitting light corresponding to the state of the CPLD.
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US20180314308A1 (en) * 2017-05-01 2018-11-01 Drexel University Work Load Scheduling For Multi Core Systems With Under-Provisioned Power Delivery
TW202227932A (en) * 2021-01-12 2022-07-16 康舒科技股份有限公司 Multi-output power supply and power distribution control method thereof with which two power output terminals of a power conversion module are optimally designed for different rated powers

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