TWI866391B - Test circuit system - Google Patents

Abstract

A testing circuit system is capable of programming and debugging the power supply chip, and the testing circuit system operates in both normal mode and debugging mode. The testing circuit system includes a resistor-capacitor delay circuit module, a debugging selection module, and an awakening delay circuit module. The resistor-capacitor delay circuit module, when receiving a 12-volt input power supply in debugging mode, generates a debugging signal and then delays the output of the awakening signal. When the debugging signal starts, the awakening pin is in a low-level state. The debugging selection module can choose either an 8-volt first high level or a 5-volt second high level to output the power supply chip, where the second high level is used for debugging and the first high level is used for programming. And the second high level will lower to a low-level state after at least seven seconds.

Description

Test circuit system

The present invention relates to the field of circuit technology for testing circuit systems, and in particular to a circuit system that can reduce costs and test circuits in an external manner.

In a test system, PMIC IC FS84 and PMIC IC FS84 series chips are used. The chip has two modes: normal mode and debug mode. When testing the chip for the first time, it is necessary to enter the debug mode first to prevent the watchdog timer in the integrated circuit from failing to clear the internal timing value of the watchdog timer in a timely manner, causing the watchdog timer to send a reset, restart or shutdown signal to the system, thereby affecting the abnormal power supply of the system.

The chip will later need to burn configuration data, serial numbers, and other important data such as security verification or product identification into the OTP (One-Time Programmable) memory, and when burning for the first time, an extra high level is required to enable normal burning.

There is a delay signal in both normal mode and debug mode. Testing can only be started through this delay signal. According to application number CN200810110168.2, a delay signal can be input into a delay module with a certain delay amount to determine whether it is wrong and whether it is necessary to proceed to the next delay level test.

However, the chip requires a more complex test method. For example, in addition to clearing the internal timing value of the watchdog timer in the debug mode, the chip also needs to provide an additional high level for burning during the burning process. The previous case did not provide such a test method. In addition, if the substrate with this test method is to be used, the circuit design is complex, resulting in a more complicated space design and higher manufacturing cost.

In order to solve the problem of increased manufacturing cost of substrates due to complex circuit design, the main purpose of this invention is to provide a test circuit system that can not only meet the test circuit system of this chip, but also reduce the basic manufacturing cost. Therefore, it is necessary to develop an ideal technical method to solve the above problems.

In view of the fact that the prior art does not provide the high voltage level required for burning and cannot reduce the manufacturing cost; therefore, the main purpose of the present invention is to provide a test circuit system.

In order to solve the problems of the previous technology, the necessary technical means adopted by the present invention is to provide a test circuit system. By making an external small card and testing on the small card, this can not only meet the test methods of normal mode and debugging mode, but also simplify the complex circuit structure designed for the test of the original motherboard, and at the same time reduce the production cost of the motherboard, so as to achieve the advantages of saving space and reducing costs.

The present invention provides a test circuit system that can burn and debug a chip with a power supply. The test circuit system has two operating modes, one is a normal mode (Normal Mode) and the other is a debug mode (Debug Mode). The test circuit system includes a resistor and capacitor delay circuit module, a debug selection module, and a wake-up delay circuit module.

When the RC delay circuit module receives input power in the debug mode, it will generate a debug signal at the same time. Then the RC delay circuit module will delay the output of the wake-up signal. The wake-up signal is used to make the wake-up pin of the chip supply power to output at a high level. When the debug signal starts, the wake-up pin is in a low level state.

The debug selection module is electrically coupled to the resistor and capacitor delay circuit module. The debug selection module can control the output power supply to the chip at one of the first high level and the second high level, that is, the debug selection module can choose to output power supply to the chip at the first high level or the second high level, wherein the second high level is used for debugging, the first high level is used for burning, and the second high level will be reduced to a low level after a predetermined period of time.

Continuation, wherein the predetermined time in the test circuit system is at least 7 seconds, and the second high level will drop to a low level after at least 7 seconds.

The wake-up delay circuit module is coupled to the input power in normal mode. The wake-up delay circuit module will delay the output of the wake-up signal, wherein the wake-up pin is in a low level state when receiving the input power.

The test circuit system also includes a main substrate, on which the resistor and capacitor delay circuit module, the debug selection module, and the wake-up delay circuit module are installed, namely the aforementioned external card.

The resistor-capacitor delay circuit module in the test circuit system further includes a voltage regulator to provide a stable output voltage and protect the circuit from voltage fluctuations and overloads, wherein the voltage regulator is used to generate the first high level and the second high level.

The wake-up delay circuit module in the test circuit system will delay the output of the wake-up signal, so that when entering the debugging mode, the wake-up pin is in a low level state when receiving input power.

The debug selection module in the test circuit system also includes a unidirectional diode, which is used to prevent the first high level and the second high level from interfering with each other, so that the current only flows in the forward direction. When the reverse direction occurs, the current will be blocked. At the same time, because of the fast switching characteristics, it can satisfy the debug selection module to choose whether to output with the first high level or the second high level.

The debug selection module in the test circuit system also has an automatic second high level, which is combined with the resistor and capacitor delay circuit module to switch the output level between low level and high level.

The chip in the test circuit system can be either PMIC IC FS84 or PMIC IC FS84 series chip.

The input power level in the test circuit system is 12 volts, the first high level is 8 volts, and the second high level is 5 volts. Therefore, it can be seen that the RC delay circuit module receives a 12 volt input power in the debug mode, and the debug selection module can choose to output power to the chip with the first high level of 8 volts or the second high level of 5 volts.

Therefore, the present invention provides a test circuit system that can test the circuit through three modules, namely, the resistor capacitor delay circuit module, the error detection selection module, and the wake-up delay circuit module. The three modules will be set on an external small card to simplify the circuit design and manufacturing cost of the motherboard. As long as it is a compatible chip such as PMIC IC FS84 and PMIC IC FS84 series chips, this external small card can be used. In this way, it can be tested in a variety of motherboards, which is easier and more convenient.

The specific embodiments adopted by the present invention will be further described through the following embodiments and drawings.

1: Test circuit system

3: Normal mode

5: Debug mode

10: Substrate

12: Input power

14: Convert input signal source

20: Resistor and capacitor delay circuit module

22: Detection signal

24: Wake-up signal

26: Voltage regulator

30: Debug selection module

32: The first high level

34: Second highest level

36: Automatic second highest level

38: Diode

40: Wake-up delay circuit module

50: Chip

The first figure is a schematic diagram showing the test circuit system of the present invention; the second figure is a schematic diagram showing the normal mode of the test circuit system of the present invention; the third figure is a schematic diagram showing the debugging mode of the test circuit system of the present invention; the fourth figure is a schematic diagram showing the resistor and capacitor delay circuit module of the present invention; the fifth figure is a schematic diagram showing the debugging selection module of the present invention; and the sixth figure is a schematic diagram showing the wake-up delay circuit module of the present invention.

The purpose of the present invention is to provide a test circuit system. By making an external small card and testing on the small card, the normal mode and debug mode test methods in the test circuit system can be satisfied. In addition, the complex circuit structure designed for the test on the original motherboard can be simplified. At the same time, the production cost of the motherboard can be reduced, so as to achieve the advantages of saving space and reducing costs.

Please refer to the first figure and the second and third figures, which are schematic diagrams showing the test circuit system of the present invention. The present invention provides a test circuit system 1, which has a normal mode 3 and a debug mode 5, and can burn and debug a chip 50 supplied by a power supply. The test circuit system 1 includes a resistor and capacitor delay circuit module 20, a debug selection module 30, and a wake-up delay circuit module 40. The debug selection module 30 and the wake-up delay circuit module 40 are electrically coupled to the resistor and capacitor delay circuit module 20 respectively.

The test circuit system 1 is set on a main substrate 10, so that the resistor and capacitor delay circuit module 20, the error detection selection module 30, and the wake-up delay circuit module 40 can be tested on the main substrate 10, that is, the three modules can be tested on the aforementioned external small card.

Through these three modules, the requirements for burning the chip 50 and the requirement for manually entering the debug mode 5 in the early stage and automatically entering the debug mode 5 in the later stage can be met. In addition, any chip using the PMIC IC FS84 or the PMIC IC FS84 series can be tested using the three modules of the main substrate 10.

The resistor capacitor delay circuit module 20 receives a 12 volt input power source 12 and cooperates with a conversion input signal source 14 to control the output of the input power source 12. The debug selection module 30 receives three high levels, namely, a first high level 32 of 8 volts, a second high level 34 of 5 volts, and an automatic second high level 36 of 5 volts, to meet the requirements of manually entering the debug mode 5 in the early stage and automatically entering the debug mode 5 in the later stage. The wake-up delay circuit module 40 receives the input The power source 12 is used for the control of the input power source 14, and the output of the wake-up signal 24 is delayed. That is, the resistor-capacitor delay circuit module 20 receives the input power source 12 of 12 volts in the debug mode 5, and the debug selection module 30 can respectively select the first high level 32 of 8 volts or the second high level 34 of 5 volts, and the automatic second high level 36 to output the debug signal 22 to the chip 50, and the wake-up delay circuit module 40 will delay the output of the wake-up signal 24.

The operating mode of the test circuit system 1 has two modes, one is the normal mode 3 and the other is the debugging mode 5. Please refer to the second and third figures. The second figure is a schematic diagram showing the normal mode of the test circuit system 1 of the present invention, and the third figure is a schematic diagram showing the debugging mode of the test circuit system 1 of the present invention.

In normal mode 3, the input power 12 will reach a high level first, and then the wake-up signal 24 will reach a high level. At this time, the wake-up signal 24 will be delayed.

In debug mode 5, the debug signal 22 and the input power 12 will reach a high level first, and then the wake-up signal 24 will reach a high level. At this time, the wake-up signal 24 will be delayed, and when the debug signal 22 and the input power 12 reach a high level, the wake-up signal 24 is still at a low level.

And in debugging mode 5, the debugging signal 22 needs to experience a predetermined time T of at least 7 seconds. After the second high level 34 has experienced at least 7 seconds, it will drop to a low level, that is, the debugging signal 22 will first rise from a low level to a high level and then drop to a low level.

Please refer to the fourth figure in conjunction with the first figure, which is a schematic diagram showing the resistor-capacitor delay circuit module 20 of the present invention. The resistor-capacitor delay circuit module 20 has an input power source 12 and is matched with a conversion input signal source 14 to control the input power output. When the resistor-capacitor delay circuit module 20 is in the debug mode 5, a delay circuit is formed through the resistor R and the capacitor C, so that when the resistor-capacitor delay circuit module 20 receives the input power source 12, a debug signal 22 is generated, and then the output of the wake-up signal 24 is delayed. The wake-up signal 24 is used to make the wake-up pin of the chip 50 output at a high level, and when the debug signal 22 starts, the wake-up pin is in a low level state.

The RC delay circuit module 20 further includes two voltage regulators 26 to provide a stable output voltage and protect the circuit from voltage fluctuations and overloads. The voltage regulators 26 are used to generate a first high level 32 of 8 volts and a second high level 34 of 5 volts. The first high level 32 can be used for burning.

Please refer to the fifth figure in conjunction with the first figure, which is a schematic diagram showing the debug selection module 30 in the present invention. The debug selection module 30 can control the output of power to the chip 50 with one of the first high level 32 and the second high level 34, that is, the debug selection module 30 can choose to output power to the chip 50 with the first high level 32 of 8 volts or the second high level 34 of 5 volts, wherein the second high level 34 is used for debugging, the first high level 32 is used for burning, and the second high level 34 needs to be reduced to a low level after a predetermined time of at least 7 seconds.

In order to automatically debug in the later stage, the debug selection module 30 also has a 5V automatic second high level 36, which is composed of the resistor capacitor delay circuit module 20 to switch the output level between low level and high level. After the initial debug mode 5 test is completed, the automatic second high level 36 can be used to automatically debug, that is, after the manual test can be performed in the debug selection module 30 by switching or inserting pins, the test can be performed in an automated manner after the initial test is completed.

Furthermore, the debug selection module 30 further includes a unidirectional conducting diode 38, which is used to prevent the first high level 32 and the second high level 34 provided by the resistor and capacitor delay circuit module 20 from interfering with each other, so that the current flows only in the forward direction, and when the reverse direction occurs, the current will be prevented from flowing. At the same time, because of the fast switching characteristics, the debug selection module 30 can choose to output power to the chip 50 with the first high level 32 or the second high level 34.

Please refer to the sixth figure in conjunction with the first, second and third figures, which are schematic diagrams showing the wake-up delay circuit module 40 of the present invention. The wake-up delay circuit module 40 is coupled to the input power 12 in normal mode 3, and the wake-up delay circuit module 40 will delay the output of the wake-up signal 24, wherein the wake-up pin is in a low level state when receiving the input power 12, that is, the wake-up signal 24 will be raised to a high level only after the input power 12 is raised to a high level, and the wake-up pin is in a low level state when the input power 12 is raised to a high level.

In the debugging mode 5, the wake-up delay circuit module 40 delays the output of the wake-up signal 24 and then enters the debugging mode 5. In order to make the wake-up pin at the time of receiving the input power 12 be in a low level state, the wake-up delay circuit module 40 has another diode 38 to ensure that the wake-up pin can switch between high and low levels.

Therefore, the present invention provides a test circuit system 1, which can test the circuit through three modules, namely, the resistor-capacitor delay circuit module 20, the debug selection module 30, and the wake-up delay circuit module 40. The three modules will be set on an external small card to simplify the circuit design and manufacturing cost of the motherboard. As long as it is a compatible chip such as PMIC IC FS84 and PMIC IC FS84 series chips, this external small card can be used. In this way, it can be tested in a variety of motherboards, which is easier and more convenient.

The above detailed description of the preferred specific embodiments is intended to more clearly describe the features and spirit of the present invention, but is not intended to limit the scope of the present invention by the preferred specific embodiments disclosed above. On the contrary, the purpose is to cover various changes and arrangements with equivalents within the scope of the patent that the present invention intends to apply for.

1: Test circuit system

10: Substrate

12: Input power

14: Convert input signal source

20: Resistor and capacitor delay circuit module

22: Detection signal

24: Wake-up signal

30: Debug selection module

32: The first high level

34: Second highest level

36: Automatic second highest level

40: Wake-up delay circuit module

50: Chip

Claims (9)

A test circuit system can burn and debug a chip with a power supply. The operation mode of the test circuit system has a normal mode and a debug mode. The test circuit system comprises: a resistor and capacitor delay circuit module, which receives an input power supply and generates a debug signal at the same time in the debug mode. The resistor and capacitor delay circuit module delays the output of a wake-up signal, and the wake-up signal is used to make the power supply supply the wake-up pin of the chip to output at a high level, wherein when the debug signal starts, the wake-up pin is in a low level state; a debug selection module, which is electrically coupled to the resistor and capacitor delay circuit module, and the debug selection module can The control outputs one of a first high level and a second high level to the power supply chip, wherein the second high level is used for debugging, and the first high level is used for burning, wherein the second high level is reduced to a low level after a predetermined period of time; and a wake-up delay circuit module is coupled to the input power supply in the normal mode, and the wake-up delay circuit module delays the output of the wake-up signal, wherein the wake-up pin is in a low level state when receiving the input power supply. The test circuit system as described in claim 1 further comprises a substrate, and the resistor and capacitor delay circuit module, the debug selection module, and the wake-up delay circuit module are arranged on the substrate. The test circuit system as described in claim 1, wherein the resistor-capacitor delay circuit module further includes a voltage regulator, and the voltage regulator is used to generate the first high level and the second high level. The test circuit system as described in claim 1, wherein the wake-up delay circuit module delays the output of the wake-up signal so that when entering the debugging mode, the wake-up pin is in a low level state when receiving the input power. The test circuit system as described in claim 1, wherein the debug selection module further includes a diode, and the diode is used to prevent the first high level and the second high level from interfering with each other. A test circuit system as described in claim 1, wherein the predetermined time period is at least 7 seconds. The test circuit system as described in claim 1, wherein the debug selection module further has an automatic second high level, which is formed with the resistor-capacitor delay circuit module to switch the output level between a low level and a high level. The test circuit system as described in claim 1, wherein the chip is one of PMIC IC FS84 and PMIC IC FS84 series chips. A test circuit system as described in claim 1, wherein the input power level is 12 volts, the first high level is 8 volts, and the second high level is 5 volts.