TWI858958B - Semiconductor device and method of forming the same - Google Patents

Abstract

The present disclosure provides a semiconductor device and a method of forming the same. The method includes following steps. An epitaxial layer is formed on a substrate, wherein the epitaxial layer includes a first well adjacent to the substrate, a second well on the first well, and a first trench extending into the first well. An implantation region is formed in the first well adjacent to a bottom portion of the first trench. A portion of the implantation region is removed through the first trench to form a second trench and a first doped region surrounding the second trench. A second doped region is formed in the first well adjacent to a bottom portion of the second trench, and a third doped region is formed under the second doped region. The second and third doped regions in the device region form a source region, and the second and third doped regions in the pick-up region form a connection region. The source region is electrically connected to the connection region through the second and the third doped regions.

Description

Semiconductor device and method of forming the same

The present invention relates to a semiconductor device and a method for forming the same.

A power metal oxide semiconductor field effect transistor (MOSFET) is a power device commonly used in analog and/or digital circuits. It can be divided into planar power MOSFET and vertical power MOSFET according to the direction of current flow. Vertical power MOSFET can be used as a power MOSFET operating at low voltage, which may include trench gate power MOSFET or split gate power MOSFET.

As device sizes continue to shrink and users' requirements for electronic device performance continue to increase, existing power MOSFETs may not be able to meet current or future requirements in terms of certain performance (such as breakdown voltage or gate-source charge (Qgs)), and the manufacturing cost is becoming increasingly expensive, making it difficult to commercialize.

The present invention provides a semiconductor device and a method for forming the same, wherein a second doped region and a third doped region are formed as a source region in a device region of a substrate, and the second doped region and the third doped region are formed as a connection region in a pickup region of the substrate, and the source region is connected to the connection region through the second doped region and the third doped region, thereby saving the area occupied by the component (for example, compared with a laterally diffused metal oxide semiconductor (LDMOS)), and the substrate does not need to use an expensive substrate with a high doping concentration in terms of material selection, and does not need to use a wafer back grinding and wafer back metallization process (BGBM) to connect the source in the device region to the pickup region.

An embodiment of the present invention provides a method for forming a semiconductor device, which includes: forming an epitaxial layer on a substrate, wherein the epitaxial layer includes a first well region adjacent to the substrate and a second well region on the first well region, and the epitaxial layer includes a first trench extending into the first well region; forming a implantation region adjacent to the bottom of the first trench in the first well region; removing a portion of the implantation region through the first trench to form a second trench and a first doped region surrounding the second trench; and forming a second doped region adjacent to the bottom of the second trench and a third doped region below the second doped region in the first well region. The second doped region and the third doped region are formed as a source region in the device region of the substrate, the second doped region and the third doped region are formed as a connection region in the pickup region of the substrate, and the source region is electrically connected to the connection region through the second doped region and the third doped region.

In one embodiment of the present invention, the second well region, the first doped region and the second doped region have a first conductivity type, and the first well region, the third doped region and the substrate have a second conductivity type different from the first conductivity type.

In one embodiment of the present invention, the method for forming a semiconductor device further includes: forming a bottom oxide layer in the bottom of the second trench in the device region; forming a gate dielectric material layer on the bottom oxide layer and on the sidewalls of the second trench; forming a gate material layer on the gate dielectric material layer; removing a portion of the gate dielectric material layer to form a gate dielectric layer, exposing the gate dielectric layer; The side walls of the gate material layer and the side walls of the second well region adjacent to the second trench are formed; and the gate material layer and the second well region are subjected to an oxidation process to form a gate layer, a first field oxide layer on the top surface and the side walls of the gate layer, and a second field oxide layer on the side walls of the second trench adjacent to the second well region, wherein the second field oxide layer extends from the second trench to the top surface of the epitaxial layer.

In one embodiment of the present invention, the method for forming a semiconductor device further includes: forming a dielectric layer on a gate layer, a first field oxide layer and a second field oxide layer; forming a plurality of drain contact openings in the dielectric layer at opposite sides of the gate layer, the drain contact openings passing through the second field oxide layer to expose a portion of the top surface of the epitaxial layer; and forming a drain in a second well region of the epitaxial layer through a portion of the top surface of the epitaxial layer.

In one embodiment of the present invention, the top surface of the bottom oxide layer is lower than the interface where the first well region and the second well region contact each other.

In one embodiment of the present invention, the gate material layer includes polysilicon.

In one embodiment of the present invention, in a direction perpendicular to the substrate, the distance between the gate layer and the source region is greater than the thickness of the gate dielectric layer.

In one embodiment of the present invention, the method for forming a semiconductor device further includes: forming a first insulating layer in a second trench in a pickup region; forming a second insulating layer covering the first insulating layer on the epitaxial layer in the pickup region; forming a third insulating layer on the second insulating layer; forming a dielectric layer on the third insulating layer; and forming a source contact passing through the dielectric layer, the third insulating layer, the second insulating layer, the first insulating layer and a portion of the connection region, wherein the source contact is electrically connected to the source region through the connection region.

The present invention provides a semiconductor device, which includes a substrate, an epitaxial layer, a source region and a connection region. The substrate includes a device region and a pickup region. The epitaxial layer is arranged on the substrate and includes a first well region adjacent to the substrate and a second well region on the first well region. The epitaxial layer includes a first trench and a second trench extending into the first well region and respectively arranged in the device region and the pickup region. The epitaxial layer includes a first doped region surrounding the first trench and the second trench. The source region is arranged in the first well region adjacent to the bottom of the first trench. The connection region is arranged in the first well region adjacent to the bottom of the second trench. The connection region and the source region are connected to each other.

In one embodiment of the present invention, the source region and the connection region include a second doped region and a third doped region, the second well region, the first doped region and the second doped region have a first conductivity type, and the first well region, the third doped region and the substrate have a second conductivity type different from the first conductivity type.

In one embodiment of the present invention, the semiconductor device further includes a bottom oxide layer, a gate dielectric layer, a gate layer, a first field oxide layer and a second field oxide layer. The bottom oxide layer is disposed in the bottom of the first trench. The gate dielectric layer is disposed on the bottom oxide layer and on the sidewalls of the first trench adjacent to the first well region. The gate layer is disposed on the gate dielectric layer. The first field oxide layer is disposed on the top surface and the sidewalls of the gate layer. The second field oxide layer is disposed on the sidewalls of the first trench adjacent to the second well region and extends to the top surface of the epitaxial layer.

In one embodiment of the present invention, in a direction perpendicular to the substrate, a distance between the gate layer and the source region is greater than a thickness of the gate dielectric layer.

In one embodiment of the present invention, the semiconductor device further includes a first insulating layer, a second insulating layer, a third insulating layer, a dielectric layer, and a source contact. The first insulating layer is disposed in the second trench. The second insulating layer is disposed on the epitaxial layer in the pickup region and covers the first insulating layer. The third insulating layer is disposed on the second insulating layer. The dielectric layer is disposed on the third insulating layer. The source contact passes through the dielectric layer, the third insulating layer, the second insulating layer, the first insulating layer, and a portion of the connection region. The source contact is electrically connected to the source region through the connection region.

Based on the above, in the semiconductor device and the method for forming the same of the above embodiment, the second doped region and the third doped region are formed as a source region in the device region of the substrate, and the second doped region and the third doped region are formed as a connection region in the pickup region of the substrate, and the source region is electrically connected to the connection region through the second doped region and the third doped region. In this way, it is not necessary to use wafer back grinding and wafer back metallization process (BGBM) to connect the source in the device region to the pickup region, and the substrate does not need to use an expensive high-doping concentration substrate in material selection, and the area occupied by the component can be saved (for example, compared with LDMOS).

The present invention is more fully described with reference to the drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings are exaggerated for clarity. The same or similar reference numbers represent the same or similar elements, and the following paragraphs will not be repeated one by one.

It should be understood that when an element is referred to as being "on" or "connected to" another element, it may be directly on or connected to another element, or there may be an intermediate element. If an element is referred to as being "directly on" or "directly connected to" another element, there are no intermediate elements. As used herein, "connection" may refer to physical and/or electrical connection, and "electrical connection" or "coupling" may be the presence of other elements between two elements. As used herein, "electrical connection" may include physical connection (e.g., wired connection) and physical disconnection (e.g., wireless connection).

As used herein, "about", "approximately" or "substantially" includes the referenced value and the average value within an acceptable deviation range of a specific value that can be determined by a person of ordinary skill in the art, taking into account the measurement in question and the specific amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about", "approximately" or "substantially" can select a more acceptable deviation range or standard deviation depending on the optical properties, etching properties or other properties, and can apply to all properties without a single standard deviation.

The terms used herein are used to describe exemplary embodiments only, rather than to limit the present disclosure. In this case, unless otherwise explained in the context, the singular form includes the plural form.

1 to 13 are cross-sectional schematic views of a method for forming a semiconductor device according to an embodiment of the present invention.

First, referring to FIG. 1 , an epitaxial layer 110 is formed on a substrate 100. The substrate 100 may include a device region R1 and a pickup region R2. The device region R1 is a region where active components such as MOS are formed. The pickup region R2 is used to pick up signals (e.g., signals connected to the source, drain, and/or gate) of active components such as MOS in the device region R1 and connect them to a region formed by a wiring pattern of a corresponding structure/pattern. In some embodiments, the pickup region R2 may be adjacent to the device region R1. The epitaxial layer 110 includes a first well region PW adjacent to the substrate 100 and a second well region ND on the first well region PW. In some embodiments, the epitaxial layer 110 may be formed by an epitaxial growth process. The substrate 100 may be doped with a first conductivity type dopant to have a first conductivity type or may be doped with a second conductivity type dopant complementary to the first conductivity type to have a second conductivity type. In some embodiments, the first conductivity type may be a P type and the second conductivity type may be an N type, but is not limited thereto. The substrate 100 may have a first conductivity type. The first well region PW of the epitaxial layer 110 may have a first conductivity type, and the second well region ND of the epitaxial layer 110 may have a second conductivity type different from the first conductivity type.

The substrate 100 may include a semiconductor substrate. The semiconductor material in the semiconductor substrate may include an elemental semiconductor, an alloy semiconductor, or a compound semiconductor. For example, the elemental semiconductor may include Si or Ge. The alloy semiconductor may include SiGe, SiGeC, etc. The compound semiconductor may include SiC, a III-V semiconductor material, or a II-VI semiconductor material. The III-V semiconductor material may include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNP, GaNAs, GaPAs, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, GaAlNP, GaAlNAs, GaAlPAs, GaInNP, GaInNAs, GaInPAs, InAlNP, InAlNAs, or InAlPAs. Group II-VI semiconductor materials may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdH gTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe or HgZnSTe. The semiconductor material may be doped with a first conductivity type dopant or a second conductivity type dopant that is complementary to the first conductivity type.

Next, a protection layer PL is formed on the epitaxial layer 110. The protection layer PL may include a dielectric material such as tetraethyl orthosilicate (TEOS).

Then, a first trench T1 extending into the first well region PW is formed in the epitaxial layer 110. The first trench T1 is formed in the device region R1 and the pickup region R2. In some embodiments, the protective layer PL and a portion of the epitaxial layer 110 may be removed by a patterning process to form the first trench T1 extending into the first well region PW in the epitaxial layer 110.

Then, referring to FIG. 1 and FIG. 2 , a implantation region 112 is formed in the first well region PW adjacent to the bottom of the first trench T1. The implantation region 112 may have the same conductivity type as the second well region ND, for example, the second conductivity type. In some embodiments, the implantation region 112 may be formed by an ion implantation process. In some embodiments, the protection layer PL may prevent dopants from being implanted from the top surface of the epitaxial layer 110 into the first well region PW when the ion implantation process is performed.

Then, referring to FIG. 2 and FIG. 3 , a portion of the implantation region 112 is removed through the first trench T1 (eg, a portion of the implantation region 112 is vertically removed) to form a second trench T2 and a first doped region 113 surrounding the second trench T2 .

Thereafter, referring to FIGS. 3 and 4 , a second doped region 114 adjacent to the bottom of the second trench T2 and a third doped region 116 below the second doped region 114 are formed in the first well region PW. The second doped region 114 may have the same conductivity type as the first doped region 113 and the second well region ND, for example, the second conductivity type. The third doped region 116 may have the same conductivity type as the substrate 100 and the first well region PW, for example, the first conductivity type. In some embodiments, the second doped region 114 may be formed by an ion implantation process. In some embodiments, the third doped region 116 may be formed below the second doped region 114 by an ion implantation process. The second doped region 114 and the third doped region 116 are formed as a source region in the device region R1 of the substrate 100. The second doped region 114 and the third doped region 116 are formed as a connection region in the pickup region R2 of the substrate 100. The source region in the device region R1 is electrically connected to the connection region in the pickup region R2 through the second doped region 114 and the third doped region 116, so that it is not necessary to use a wafer back grinding and wafer back metallization process (BGBM) to connect the source in the device region R1 to the pickup region R2, and the substrate 100 does not need to use an expensive high-doping concentration substrate in terms of material selection, and the area occupied by the component can be saved (for example, compared with LDMOS).

The second well region ND, the first doped region 113, and the second doped region 114 may have a first conductivity type, and the first well region PW, the third doped region 116, and the substrate 100 may have a second conductivity type different from the first conductivity type.

Next, referring to FIG. 4 and FIG. 5 , after forming the second doping region 114 and the third doping region 116, the protective layer PL is removed and a first insulating layer 120 is formed in the second trench T2. The first insulating layer 120 is formed in the device region R1 and the pickup region R2. In some embodiments, the first insulating layer 120 can be formed, for example, by the following steps. First, after removing the protective layer PL, an insulating material (e.g., oxide) is filled in the second trench T2. In this step, the insulating material is also formed on the top surface of the epitaxial layer 110. Next, the insulating material formed on the top surface of the epitaxial layer 110 is removed by an etch-back process to form a first insulating layer 120 in the second trench T2.

Thereafter, referring to FIGS. 5 and 6 , a second insulating layer 130 covering the first insulating layer 120 is formed on the top surface of the epitaxial layer 110. The second insulating layer 130 is formed in the device region R1 and the pickup region R2. The second insulating layer 130 may include an insulating material such as oxide. In some embodiments, the first insulating layer 120 and the second insulating layer 130 may include the same insulating material.

Next, a third insulating layer 140 is formed on the second insulating layer 130 of the pickup region R2. The third insulating layer 140 is not formed on the second insulating layer 130 of the device region R1. The third insulating layer 140 may include a nitride such as silicon nitride. The material of the third insulating layer 140 is different from that of the second insulating layer 130 (for example, the second insulating layer 130 may include an oxide, and the third insulating layer 140 may include a nitride). In this way, the third insulating layer 140 can be used as a mask layer, so that when other processes are subsequently performed on the device region R1 (such as a process for forming a MOS), the structure/film layer located below the third insulating layer 140 in the pickup region R2 will not be affected.

Then, referring to FIG. 6 and FIG. 7 , the second insulating layer 130 and a portion of the first insulating layer 120 in the device region R1 are removed to form a bottom oxide layer 122 in the bottom of the second trench T2 in the device region R1. In some embodiments, the second insulating layer 130 and a portion of the first insulating layer 120 can be removed by an etch-back process. The material of the third insulating layer 140 is different from that of the second insulating layer 130 and the first insulating layer 120, so the above process performed in the device region R1 will not affect the film layer/structure of the pickup region R2. In some embodiments, the top surface of the bottom oxide layer 122 is lower than the interface where the first well region PW and the second well region ND contact each other.

7 and 8, a gate dielectric material layer 150 is formed on the bottom oxide layer 122 and the sidewalls of the second trench T2. In some embodiments, the gate dielectric material layer 150 may be formed on the top surface of the epitaxial layer 110 and extend into the second trench T2 to form the gate dielectric material layer 150 on the sidewalls of the second trench T2 and the bottom oxide layer 122. The gate dielectric material layer 150 may include any material suitable for a gate dielectric layer, such as silicon oxide.

Then, a gate material layer 160 is formed on the gate dielectric material layer 150. The gate material layer 160 includes polysilicon. In some embodiments, the gate material layer 160 can be formed in the second trench T2 by the following steps. First, a gate material is formed on the gate dielectric material layer 150. Then, the gate material above the top surface of the epitaxial layer 110 is removed to form the gate material layer 160 in the second trench T2. In some embodiments, the gate material above the top surface of the epitaxial layer 110 can be removed by etching back to form the gate material layer 160 in the second trench T2. In some embodiments, a top surface of the gate material layer 160 may be lower than a top surface of the epitaxial layer 110 .

Then, referring to FIG8 and FIG9, a portion of the gate dielectric material layer 150 is removed to form a gate dielectric layer 152, wherein the gate dielectric layer 152 exposes the sidewalls of the gate material layer 160 and the sidewalls of the second trench T2 adjacent to the second well region ND. In some embodiments, a portion of the gate dielectric material layer 150 may be removed by a wet etching process. Since the material of the third insulating layer 140 is different from that of the gate dielectric material layer 150, the above-mentioned process performed in the device region R1 will not affect the film layer/structure of the pickup region R2.

Thereafter, referring to FIGS. 9 and 10 , an oxidation process is performed on the gate material layer 160 and the second well region ND of the epitaxial layer 110 to form a gate layer 162, a first field oxide layer 170a on the top surface and side walls of the gate layer 162, and a second field oxide layer 170b on the side walls of the second well region ND adjacent to the second trench T2, wherein the second field oxide layer 170b extends from the second trench T2 to the top surface of the epitaxial layer 110. In some embodiments, a thermal oxidation process may be performed on the gate material layer 160 and the second well region ND of the epitaxial layer 110. When the gate material layer 160 includes polysilicon and the epitaxial layer 110 formed by the epitaxial growth process includes silicon, the gate material layer 160 and the second well region ND of the epitaxial layer 110 may undergo an oxidation reaction at the surface exposed to the process to form a first field oxide layer 170a and a second field oxide layer 170b whose material is silicon oxide. In other words, the portion of the gate material layer 160 adjacent to the exposed surfaces may be oxidized, so the shape or outline of the gate layer 162 may be different from the shape or outline of the gate material layer 160 (as shown in FIG. 10 ). Similarly, the second well region ND of the epitaxial layer 110 is oxidized near the exposed surfaces, which is different from the epitaxial layer 110 before the second field oxide layer 170b is formed. In some embodiments, the interface where the first field oxide layer 170a and the second field oxide layer 170b contact each other is in the second trench T2.

As shown in FIG. 10 , in a direction perpendicular to the substrate 100 , since there is a bottom oxide layer 122 between the gate layer 162 and the second doped region 114 and the third doped region 116 serving as the source region in the device region R1 in addition to the gate dielectric layer 152 (i.e., the distance between the gate layer 162 and the source region is greater than the thickness of the gate dielectric layer 152 ), the gate-source charge (Qgs) can be reduced without increasing the size of the device, thereby improving the performance of the semiconductor device.

10 and 11, a dielectric layer 180 is formed on the gate layer 162, the first field oxide layer 170a, and the second field oxide layer 170b. The dielectric layer 180 is also formed on the third insulating layer 140 of the pickup region R2.

Then, a plurality of drain contact openings DCH are formed in the dielectric layer 180 at opposite sides of the gate layer 162. The drain contact openings DCH penetrate the second field oxide layer 170b to expose a portion of the top surface of the epitaxial layer 110. Then, a drain 118 is formed in the second well region ND of the epitaxial layer 110 through the portion of the top surface of the epitaxial layer 110. The drain 118 may have the same conductivity type as the second well region ND, for example, the second conductivity type. There is a first field oxide layer 170a grown from the gate material layer 160 and a second field oxide layer 170b grown from the second well region ND of the epitaxial layer 110 between the drain 118 and the gate 162. Therefore, the formed field oxide layer includes the first field oxide layer 170a and the second field oxide layer 170b, so that the breakdown voltage of the semiconductor device can be increased without increasing the size of the component.

11 and 12, a source contact opening SCH is formed in the pickup region R2 through the dielectric layer 180, the third insulating layer 140, the second insulating layer 130, the first insulating layer 120, and a portion of the second doped region 114 and the third doped region 116 as a connection region.

Then, referring to FIG. 12 and FIG. 13 , a silicide 190 is formed on the drain 118 of the device region R1 through the drain contact opening DCH, and a silicide 190 is formed on the connection region of the pickup region R2 through the source contact opening SCH (e.g., on the second doped region 114 and the third doped region 116 exposed by the source contact opening SCH). The silicide 190 may include tungsten silicide, titanium silicide, cobalt silicide, zirconium silicide, platinum silicide, molybdenum silicide, copper silicide, nickel silicide, or a combination thereof.

Thereafter, referring to FIGS. 13 and 14 , conductive materials are filled into the drain contact opening DCH and the source contact opening SCH to form drain contacts DC and source contacts SC in the device region R1 and the pickup region R2, respectively. The conductive materials may include metals, metal alloys, metal nitrides, or combinations thereof. In some embodiments, the metals and metal alloys may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof. The metal nitride may be, for example, titanium nitride, tungsten nitride, tantalum nitride, tantalum silicon nitride, titanium silicon nitride, tungsten silicon nitride, or combinations thereof.

The source contact SC passes through the dielectric layer 180, the third insulating layer 140, the second insulating layer 130, the first insulating layer 120, and a portion of the second doped region 114 and the third doped region 116 as the connection region. The source contact SC is electrically connected to the source region in the device region R1 (the second doped region 114 and the third doped region 116 in the device region R1 are formed as the source region) through the connection region (the second doped region 114 and the third doped region 116 in the pickup region R2 are formed as the connection region). As a result, there is no need to use wafer back grinding and wafer back metallization (BGBM) to connect the source in the device region R1 to the pickup region R2, and the substrate 100 does not need to use an expensive high-doping concentration substrate in material selection, and the area occupied by the component can be saved (for example, compared with LDMOS).

Hereinafter, a semiconductor device according to an embodiment of the present invention will be described by way of example with reference to FIG13. In addition, although the method for forming a semiconductor device according to an embodiment of the present invention is described using the above method as an example, the method for forming a semiconductor device according to the present invention is not limited thereto.

Referring to FIG. 13 , the semiconductor device includes a substrate 100, an epitaxial layer 110, a source region (the second doping region 114 and the third doping region 116 in the device region R1 are formed as the source region), and a connection region (the second doping region 114 and the third doping region 116 in the pickup region R2 are formed as the connection region). The substrate 100 includes the device region R1 and the pickup region R2. The epitaxial layer 110 is disposed on the substrate 100 and includes a first well region PW adjacent to the substrate 100 and a second well region ND on the first well region PW. The epitaxial layer 110 includes a first trench and a second trench (e.g., trench T2 shown in FIG. 4 ) extending into the first well region PW and respectively disposed in the device region R1 and the pickup region R2. The epitaxial layer 110 includes a first doped region 113 surrounding the first trench and the second trench. The source region is disposed in a first well region PW adjacent to the bottom of the first trench. The connection region is disposed in the first well region PW adjacent to the bottom of the second trench. The connection region and the source region are connected to each other.

In some embodiments, the source region and the connection region include a second doped region 114 and a third doped region 116, the second well region ND, the first doped region 113, and the second doped region 114 have a first conductivity type, and the first well region PW, the third doped region 116, and the substrate 100 have a second conductivity type different from the first conductivity type.

In some embodiments, the semiconductor device further includes a bottom oxide layer 122, a gate dielectric layer 152, a gate layer 162, a first field oxide layer 170a, and a second field oxide layer 170b. The bottom oxide layer 122 is disposed in the bottom of the first trench. The gate dielectric layer 152 is disposed on the bottom oxide layer 122 and on the sidewalls of the first trench adjacent to the first well region PW. The gate layer 162 is disposed on the gate dielectric layer 152. The first field oxide layer 170a is disposed on the top surface and the sidewalls of the gate layer 162. The second field oxide layer 170b is disposed on the sidewall of the first trench adjacent to the second well region ND and extends to the top surface of the epitaxial layer 110.

In one embodiment of the present invention, in a direction perpendicular to the substrate 100 , a distance between the gate layer 162 and the source region (the second doped region 114 and the third doped region 116 in the device region R1 are formed as the source region) is greater than a thickness of the gate dielectric layer 152 .

In one embodiment of the present invention, the semiconductor device further includes a first insulating layer 120, a second insulating layer 130, a third insulating layer 140, a dielectric layer 180, and a source contact SC. The first insulating layer 120 is disposed in the second trench. The second insulating layer 130 is disposed on the epitaxial layer 110 in the pickup region R2 and covers the first insulating layer 120. The third insulating layer 140 is disposed on the second insulating layer 130. The dielectric layer 180 is disposed on the third insulating layer 140. The source contact SC passes through the dielectric layer 180, the third insulating layer 140, the second insulating layer 130, the first insulating layer 120, and a portion of the connection region (the second doped region 114 and the third doped region 116 in the pickup region R2 form the connection region). The source contact SC is electrically connected to the source region through the connection region.

In summary, in the semiconductor device and the method for forming the same according to the above-mentioned embodiment, the second doped region and the third doped region are formed as a source region in the device region of the substrate, and the second doped region and the third doped region are formed as a connection region in the pickup region of the substrate, and the source region is electrically connected to the connection region through the second doped region and the third doped region. In this way, it is not necessary to use wafer back grinding and wafer back metallization (BGBM) to connect the source in the device region to the pickup region, and the substrate does not need to use an expensive substrate with a high doping concentration in terms of material selection, and the area occupied by the component can be saved (for example, compared with LDMOS).

100: Base

110: Epitaxial layer

112: Planting area

113: First mixed area

114: Second mixed area

116: The third mixed area

118: Drain

120: First insulation layer

122: Bottom oxide layer

130: Second insulation layer

140: The third insulating layer

150: Gate dielectric material layer

152: Gate dielectric layer

160: Gate material layer

162: Gate layer

170a: First field oxide layer

170b: Second field oxide layer

180: Dielectric layer

190:Silicide

DC: Drain contact

DCH: Drain Contact Hole

ND: Second Well Area

PW: First Well Area

PL: Protective layer

R1: Equipment area

R2: Pickup Area

SC: Source Contact

SCH: Source contact opening

T1: First channel

T2: Second channel/channel

1 to 13 are cross-sectional schematic views of a method for forming a semiconductor device according to an embodiment of the present invention.

100: Base

110: Epitaxial layer

113: First mixed area

114: Second mixed area

116: The third mixed area

118: Drain

120: First insulation layer

122: Bottom oxide layer

130: Second insulation layer

140: The third insulating layer

152: Gate dielectric layer

162: Gate layer

170a: First oxide layer

170b: Second field oxide layer

180: Dielectric layer

190: Silicide

DC: Drain contact

ND: Second well area

PW: First Well Area

R1: Equipment area

R2: Pickup Area

SC: Source contact

Claims (12)

A method for forming a semiconductor device, comprising: forming an epitaxial layer on a substrate, wherein the epitaxial layer comprises a first well region adjacent to the substrate and a second well region on the first well region, and the epitaxial layer comprises a first trench extending into the first well region; forming a implantation region adjacent to a bottom of the first trench in the first well region; removing a portion of the implantation region through the first trench to form a second trench and a first trench surrounding the second trench; doped region; and forming a second doped region adjacent to the bottom of the second trench in the first well region and a third doped region below the second doped region, wherein the second doped region and the third doped region are formed as a source region in the device region of the substrate, the second doped region and the third doped region are formed as a connection region in the pickup region of the substrate, and the source region is electrically connected to the connection region through the second doped region and the third doped region. The method of claim 1, wherein the second well region, the first doped region and the second doped region have a first conductivity type, and the first well region, the third doped region and the substrate have a second conductivity type different from the first conductivity type. The method of claim 1 further comprises: forming a bottom oxide layer in the bottom of the second trench in the device region; forming a gate dielectric material layer on the bottom oxide layer and on the sidewalls of the second trench; forming a gate material layer on the gate dielectric material layer; removing a portion of the gate dielectric material layer to form a gate dielectric layer, wherein the gate dielectric layer exposes the gate material layer. The sidewall of the second trench and the sidewall of the second well region adjacent to the second trench; and the gate material layer and the second well region are subjected to an oxidation process to form a gate layer, a first field oxide layer on the top surface and sidewall of the gate layer, and a second field oxide layer on the sidewall of the second trench adjacent to the second well region, wherein the second field oxide layer extends from the second trench to the top surface of the epitaxial layer. The method of claim 3 further includes: forming a dielectric layer on the gate layer, the first field oxide layer and the second field oxide layer; forming a plurality of drain contact openings in the dielectric layer at opposite sides of the gate layer, the drain contact openings passing through the second field oxide layer to expose a portion of the top surface of the epitaxial layer; and forming a drain in the second well region of the epitaxial layer through the portion of the top surface of the epitaxial layer. As described in claim 3, the top surface of the bottom oxide layer is lower than the interface where the first well region and the second well region contact each other. A method as described in claim 3, wherein the gate material layer includes polysilicon. A method as described in claim 3, wherein the distance between the gate layer and the source region in a direction perpendicular to the substrate is greater than the thickness of the gate dielectric layer. The method of claim 1 further includes: forming a first insulating layer in the second trench in the pickup region; forming a second insulating layer covering the first insulating layer on the epitaxial layer in the pickup region; forming a third insulating layer on the second insulating layer; forming a dielectric layer on the third insulating layer; and forming a source contact passing through the dielectric layer, the third insulating layer, the second insulating layer, the first insulating layer and a portion of the connection region, wherein the source contact is electrically connected to the source region through the connection region. A semiconductor device comprises: a substrate, comprising a device region and a pickup region; an epitaxial layer, disposed on the substrate and comprising a first well region adjacent to the substrate and a second well region on the first well region, the epitaxial layer comprising a first trench and a second trench extending into the first well region and respectively disposed in the device region and the pickup region, and comprising a first doped region surrounding the first trench and the second trench; a source region, disposed at the bottom of the first trench adjacent to the first trench and a connecting region disposed in the first well region adjacent to the bottom of the second trench, wherein the connecting region and the source region are connected to each other, wherein the source region and the connecting region include a second doped region and a third doped region, the second well region, the first doped region and the second doped region have a first conductivity type, and the first well region, the third doped region and the substrate have a second conductivity type different from the first conductivity type. The semiconductor device as described in claim 9 further includes: a bottom oxide layer disposed in the bottom of the first trench; a gate dielectric layer disposed on the bottom oxide layer and on the sidewalls of the first trench adjacent to the first well region; a gate layer disposed on the gate dielectric layer; a first field oxide layer disposed on the top surface and sidewalls of the gate layer; and a second field oxide layer disposed on the sidewalls of the first trench adjacent to the second well region and extending to the top surface of the epitaxial layer. A semiconductor device as described in claim 10, wherein the distance between the gate layer and the source region in a direction perpendicular to the substrate is greater than the thickness of the gate dielectric layer. The semiconductor device as described in claim 9 further includes: a first insulating layer disposed in the second trench; a second insulating layer disposed on the epitaxial layer in the pickup region and covering the first insulating layer; a third insulating layer disposed on the second insulating layer; a dielectric layer disposed on the third insulating layer; and a source contact passing through the dielectric layer, the third insulating layer, the second insulating layer, the first insulating layer and a portion of the connection region, wherein the source contact is electrically connected to the source region through the connection region.

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