TWI856816B - A semiconductor device - Google Patents

Abstract

A semiconductor device includes a drift layer, a plurality of first doped regions, a plurality of second doped regions, a plurality of third doped regions, a doped channel layer, a gate insulating layer, a gate contact and a source contact. The drift layer is disposed on a substrate and has an upper surface. A junction field effect transistor region is defined between adjacent first doped regions. The second doped regions and the first doped regions define a plurality of channel regions along the upper surface. The doped channel layer is disposed adjacent to the upper surface and extends across the drift layer between the second doped regions. The gate insulating layer is disposed on the upper surface, the gate contact contacts the gate insulating layer, and the source contact contacts the second doped regions and the third doped regions.

Description

A semiconductor device

The present invention relates to a semiconductor device, and more particularly to a constant current diode circuit.

A constant current diode (CRD) is a semiconductor constant current element that can maintain a certain current value within a certain operating voltage range. Its output current is between a few milliamperes (mA) and tens of milliamperes. The output current can drive the load and has the advantages of simple circuit structure, good reliability, and small size. In addition, the constant current diode has a large operating range of constant current and high dynamic resistance, which can make the circuit structure obtain the circuit characteristics of constant current, and obtain low power supply variation, low load variation, and low ripple voltage through a single diode. The knee voltage of a constant current diode refers to the voltage value at which the current begins to increase rapidly when the diode is under forward bias.

However, current constant current diode circuits still have problems such as high breaking point voltage, unstable current characteristics at high temperatures, small operating current value range, and difficulty in adjusting the positive and negative trends of the temperature coefficient. How to improve the above-mentioned shortcomings of constant current diode circuits is a problem that technicians in this field want to solve.

The main purpose of the present invention is to solve the problems of high flexure voltage of constant current diode, unstable current characteristics at high temperature, small operating current value range and difficulty in adjusting the positive and negative trends of temperature coefficient.

The invention discloses a semiconductor device, comprising a drift layer, a plurality of first doped regions, a plurality of second doped regions, a plurality of third doped regions, a doped channel layer, a gate insulating layer, a gate contact and a source contact. The drift layer is disposed on a substrate and has a first conductivity type and an upper surface. The first doped regions are arranged in the drift layer adjacent to the upper surface and are separated from each other. The first doped regions have a second conductivity type opposite to the first conductivity type. The first doped regions and the drift layer form a plurality of first pn junctions. A junction field effect transistor region is defined between adjacent first doped regions. The first doped regions have a depth ranging from 3 μm to 5 μm and a doping concentration ranging from 8e16 cm ^-3 to 2e15 cm ^-3 . The second doped region is disposed in the first doped region, the second doped region has the first conductivity type, the second doped region and the first doped region form a plurality of second pn junctions, and a plurality of channel regions are defined between the first pn junction and the second pn junction along the upper surface, the second doped region has a depth ranging from 0.4 μm to 1 μm, and a doping concentration ranging from 2e19 cm ^-3 to 2e17 cm ^-3 . The third doped region is disposed in the second doped region, and the third doped regions have the second conductivity type. The doped channel layer is disposed adjacent to the upper surface and extends across the drift layer between the second doped regions, the doped channel layer having a thickness ranging between 75 Å and 90 Å, a doping concentration ranging between 1e17 cm ^-3 and 1e16 cm ^-3 , and a width ranging between 1 μm and 6 μm. The gate insulating layer is disposed on the upper surface, the gate insulating layer extending over the junction field effect transistor region, the channel regions, and a portion of the second doped regions. The gate contact contacts the gate insulating layer. The source contact contacts the second doped regions and the third doped regions.

The present invention also discloses a constant current diode circuit, comprising the semiconductor device as described above.

It should be understood that the thickness of each layer and each region is exaggerated for clarity. It should also be understood that when an element such as a layer, portion, region, or substrate is referred to as being "on," "overlying," or "over" another element, it can be directly on, directly overlying, or directly over that element; or there may be other elements in between. Conversely, when an element is referred to as being "directly on," "directly overlying," or "directly over" another element, there are no intervening elements. Similarly, when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements between them.

Relative terms such as "higher than", "lower than", "above", "below", "horizontal", "lateral" or "vertical" may be used herein to describe the relationship of one element, layer, portion or region in the drawings to another element, layer, portion or region. It should be understood that these terms and those described above are intended to cover different orientations of the elements in addition to the direction depicted in the figure. A number of embodiments will be described below, in which the same structural features are identified by the same or similar figure labels. As used herein, "lateral" or "lateral direction" should be understood to mean a direction or range extending generally parallel to the lateral extent of a semiconductor element, which therefore extends generally parallel to its surface or side. In contrast, the term "thickness direction" is understood to mean a direction extending generally perpendicular to its surface or side and therefore perpendicular to the lateral direction.

In this article, the terms used in the description of various embodiments are only for the purpose of describing specific examples and are not intended to be limiting. Unless the context clearly indicates otherwise, or the number of elements is deliberately limited, the singular forms "a", "the" used herein may also include plural forms. Further, the terms "include" and/or "comprise" when used in this article indicate the presence of the described features, elements and/or components, but do not exclude the addition or presence of one or more other features, elements, components and/or their groups. Indefinite and definite articles should include the plural and singular, unless the contrary is clearly seen from the context.

The terms "first conductivity type" and "second conductivity type" refer to opposite conductivity types, such as n-type or p-type. However, the description and drawings of each embodiment herein also include its complementary embodiments, and the same numbers represent the same elements.

Referring to FIG. 1 , the present invention discloses a semiconductor device 100 , which includes a substrate 110 , a drift layer 120 , a plurality of first doped regions 130 , a plurality of second doped regions 140 , a plurality of third doped regions 150 , a doped channel layer 160 , a gate insulating layer 170 , a gate contact 181 , a source contact 182 , and a drain contact 183 . In one example, the material of the substrate 110 is silicon (Si), and the first doped region 130 can be formed by epitaxial process, diffusion, ion implantation or chemical vapor deposition (CVD) and other techniques, such as directly growing a p-type layer on an n-type drift layer in a MOCVD reactor, or implanting aluminum ions as dopants into the n-type drift layer by ion implantation technology to form a reverse doped p-type region adjacent to a main surface of the drift layer 120. Similarly, the second doped region 140 and the third doped region 150 can be formed by epitaxial process, diffusion method, ion implantation or vapor phase doping.

The substrate 110 has a top surface 111 and a bottom surface 112 . The drift layer 120 is disposed on the top surface 111 of the substrate 110 and has a first conductivity type (eg, n-type). The drift layer 120 includes an upper surface 121 .

The first doped regions 130 are disposed in the drift layer 120 adjacent to the upper surface 121 and are spaced apart from each other. Specifically, the first doped regions 130 are doped downward from the upper surface 121 into the drift layer 120. The first doped regions 130 have a second conductivity type (e.g., p-type), and the first doped regions 130 and the drift layer 120 form a plurality of first pn junctions PN1, and a junction field effect transistor region J is defined between adjacent first doped regions 130. In this embodiment, the first doped region 130 has a depth D1 ranging between 3 μm and 5 μm, and a doping concentration ranging between 8e16 cm ⁻³ and 2e15 cm ⁻³ .

The second doped region 140 is disposed in the first doped region 130, the second doped region has the first conductivity type, the second doped region 140 and the first doped region 130 form a plurality of second pn junctions PN2, and the second doped region 140 and the first doped region 130 define a plurality of channel regions CH between the first pn junction PN1 and the second pn junction PN2 along the upper surface 121. In the present embodiment, the second doped region 140 has a depth D2 ranging from 0.4 μm to 1 μm, and a doping concentration ranging from 2e19 cm ^-3 to 2e17 cm ^-3 .

The third doped region 150 is disposed in the second doped region 140 and contacts the first doped region 130 and the second doped region 140. The third doped regions 150 have the second conductivity type.

The doped channel layer 160 is disposed adjacent to the upper surface 121 and extends across the drift layer 120 between the second doped regions 140, and the doped channel layer 160 is doped downward from the upper surface 121 of the drift layer 120 to be formed between the second doped regions 140 and across the drift layer 120. In the present embodiment, the doped channel layer 160 has a thickness T ranging between 75 Å and 90 Å, a doping concentration ranging between 1e17 cm ^-3 and 1e16 cm ^-3 , and a width W ranging between 1 μm and 6 μm.

The gate insulating layer 170 is disposed on the upper surface 121 of the drift layer 120 , and the gate insulating layer 170 extends on and contacts a portion of the junction field effect transistor region J, the channel regions CH, and the second doped regions 140 .

In one example, the depth D1 of the first doped region 130 and the depth D2 of the second doped region 140 are vertical distances from the upper surface 121 to the bottom of the first doped region 130 and the second doped region 140, the thickness T of the doped channel layer 160 is also the vertical distance from the upper surface 121 to the bottom of the doped channel layer 160, and the width W of the doped channel layer 160 is the horizontal distance between adjacent second doped regions 140.

The gate contact 181 contacts the gate insulating layer 170 and is a contact structure for connecting the gate (Gate) and an external circuit. The source contact 182 contacts the second doped regions 140 and the third doped regions 150 and is a contact structure for connecting the source (Source) and an external circuit. The drain contact 183 contacts the bottom surface 112 of the substrate 110 and is a contact structure for connecting the drain (Drain) and an external circuit. In one example, the gate contact 181 , the source contact 182 , and the drain contact 183 may be made of metal or alloy materials, such as platinum, nickel, aluminum, or a combination thereof.

In the present invention, a knee voltage, a peak current and a temperature coefficient of the semiconductor device 100 are adjusted as the thickness T of the doped channel layer 160 changes. In one example, the peak current is greater than 500 mA, and in another example, the temperature coefficient is between -0.01% and +0.01%. In this embodiment, the semiconductor device 100 is configured as a metal-oxide-semiconductor field-effect transistor (MOSFET) and can be applied to a constant current diode circuit.

When applied to the constant current diode circuit and bias is applied, current will flow through the doped channel layer 160, and when the bias rises to the channel cutoff voltage (Vk), a constant current state is reached (i.e., the current no longer increases with the increase in voltage, but is maintained at a constant value). In the present invention, by first setting the conditions of the doping concentration of the first doping region 130 and the second doping region 140, and under the conditions, finding the structure of the doping channel layer 160 and the specific parameters of the doping concentration, the following effects are achieved: the semiconductor device 100 can still maintain a nearly constant current at different operating temperatures; the inflection point voltage of the semiconductor device 100 is reduced, which can save the consumption of the circuit's own components; the range of the constant current value is increased; and the positive and negative trends of the temperature coefficient of the semiconductor device 100 are adjusted. In one example, the semiconductor device 100 can have a constant current close to that when the operating temperature is between 25°C and 150°C, and the constant current of the semiconductor device 100 can be between 0.1 mA and 500 mA. In particular, the doped channel layer 160 belongs to the back-end process and is less susceptible to the influence of other processes, so it has advantages in manufacturing, is convenient for controlling the process interval, and also reduces the challenge of mass production.

FIG2 shows IV curve characteristics of different experimental examples. The applied voltage is 5V, the operating temperature of the experimental example is 25°C, and the voltage with the increase of current is respectively curve E1, curve E2, and curve E3 in FIG2. In the experimental examples E1, E2, and E3, the depth D1 of the first doped region 130 is about 3.5 μm and the doping concentration is about 3e16 cm ^-3 , the depth D2 of the second doped region 140 is about 0.5 μm and the doping concentration is about 5e18 cm ^-3 , and the width W of the doped channel layer 160 is about 5 μm and the doping concentration is about 5e16 cm ^-3 . In addition, the thickness T of the doped channel layer 160 in Experimental Examples E1, E2, and E3 is 85 Å, 80 Å, and 75 Å, respectively.

When the thickness T of the doped channel layer 160 is 85 Å, the inflection point voltage of Experimental Example E1 is 2.8 V, and the temperature coefficient is -0.07%; when the thickness T of the doped channel layer 160 is 80 Å, the inflection point voltage of Experimental Example E2 is 2.3 V, and the temperature coefficient is -0.05%; when the thickness T of the doped channel layer 160 is 75 Å, the inflection point voltage of Experimental Example E3 is 2.0 V, and the temperature coefficient is 0.00%.

From the measurement of the peak current (constant current) of the semiconductor device 100 at a voltage value of 5 V, it can be found that when the thickness T of the doped channel layer 160 is 85 Å, the peak current of Experimental Example E1 is 119.87 mA, when the thickness T of the doped channel layer 160 is 80 Å, the peak current of Experimental Example E2 is 71.82 mA, and when the thickness T of the doped channel layer 160 is 75 Å, the peak current of Experimental Example E3 is 80.13 mA.

From the I-V curve of FIG. 2 , it can be seen that the inflection point voltage of the semiconductor device 100 can be adjusted by controlling the thickness T of the doped channel layer 160. The thickness T of the doped channel layer 160 is positively correlated with the inflection point voltage, that is, the thicker the thickness T, the higher the inflection point voltage; the thinner the thickness T, the lower the inflection point voltage; in addition, the positive and negative trends of the temperature coefficient can also be adjusted to meet the needs of the application.

FIG3 shows the I-V curve characteristics of different experimental examples. The applied voltage is 10V, the operating temperature of the experimental example is 25°C, and the voltage with the increase of current is respectively curve E4, curve E5, and curve E6 in FIG3. Experimental examples E4, E5, and E6 are devices with the same structure as experimental examples E1, E2, and E3, that is, the width, depth, and doping concentration of the first doped region 130, the second doped region 140, and the doped channel layer 160 are the same, and the thickness T of the doped channel layer 160 of the experimental examples E4, E5, and E6 is 85 Å, 80 Å, and 75 Å, respectively.

The inflection point voltages of Experimental Examples E4, E5, and E6 are all 1.8 V, and when the thickness T of the doped channel layer 160 is 85 Å, the temperature coefficient of Experimental Example E4 is -0.12%; when the thickness T of the doped channel layer 160 is 80 Å, the temperature coefficient of Experimental Example E2 is -0.09%; and when the thickness T of the doped channel layer 160 is 75 Å, the temperature coefficient of Experimental Example E3 is -0.06%.

Further measuring the current value of the peak current (constant current) of the semiconductor device 100 at a voltage value of 5 V, when the thickness T of the doped channel layer 160 is 85 Å, the peak current of Experimental Example E4 is 556 mA, when the thickness T of the doped channel layer 160 is 80 Å, the peak current of Experimental Example E5 is 551 mA, and when the thickness T of the doped channel layer 160 is 75 Å, the peak current of Experimental Example E6 is 490 mA. Therefore, according to the semiconductor device 100 of the embodiment of the present invention, a high constant current higher than 500 mA can be obtained.

From the I-V curve of FIG. 3 , it can be seen that when the inflection voltage is a constant value, the peak current of the semiconductor device 100 can be adjusted by controlling the thickness T of the doped channel layer 160. The thickness T of the doped channel layer 160 is positively correlated with the peak current, that is, the thicker the thickness T, the higher the peak current, and the thinner the thickness T, the lower the peak current. By increasing the thickness T of the doped channel layer 160, the current value of the peak current can be increased to greater than 500 mA, as shown in curves E4 and E5.

FIG4 shows the I-V curve characteristics of other experimental examples and comparative examples. Experimental examples E7, E8, and E9 were tested at operating temperatures of 25°C, 75°C, and 125°C, respectively. Comparative examples C1, C2, and C3 were tested at operating temperatures of 25°C, 75°C, and 125°C, respectively. The voltages that increase with increasing current are curves E7, E8, E9, C1, C2, and C3 in FIG4 , respectively.

It can be seen from Experimental Example E7, Experimental Example E8, and Experimental Example E9 that the I-V curves at different temperatures are close, that is, the temperature coefficient of the experimental example is lower (that is, the relative change rate of the peak current at the operating temperature is small), about -0.021%. In contrast, the temperature coefficient of Comparative Example C1, Comparative Example C2, and Comparative Example C3 is higher, about -0.325%.

5A and 5B respectively show the IV curve characteristics of other experimental examples E10 and E11 and comparative examples C4 and C5. FIG. 5A is a semiconductor device according to the present invention, and FIG. 5B is a semiconductor device according to other conditions. In experimental examples E10 and E11, the depth D1 of the first doped region 130 is approximately 4 μm and the doping concentration is approximately 8e15 cm ^-3 , the depth D2 of the second doped region 140 is approximately 0.7 μm and the doping concentration is approximately 5e18 cm ^-3 , the width W of the doped channel layer 160 is approximately 5 μm and the doping concentration is approximately 5e16 cm ^-3 , and the thickness T of the doped channel layer 160 of experimental examples E10 and E11 is 80 Å and 75 Å respectively. The difference between comparative examples C4 and C5 and experimental examples E10 and E11 is that the thickness T of the doped channel layer 160 of comparative examples C4 and C5 is 60 Å and 70 Å respectively.

The inflection point voltages of experimental examples E10 and E11 are 2.3 V and 2.0 V, respectively, and the temperature coefficients are -0.05% and 0.00%, respectively; the inflection point voltages of comparative examples C4 and C5 are 6.0 V and 5.5 V, respectively, and the temperature coefficients are -0.17% and -0.14%, respectively.

In addition to the previous experiments and comparisons, in order to verify that the present invention has found that the channel cutoff voltage (Vk) of the constant current diode circuit can be appropriately adjusted by changing the width W of the doped channel layer 160, a constant current diode circuit with the same parameters but different width W of the doped channel layer 160 is further tested. The depth D1 of the first doped region 130 is about 4 μm and the doping concentration is about 9e15 cm ^-3 , and the depth D2 of the second doped region 140 is about 0.5 μm and the doping concentration is about 5e18 cm ^-3. The width W of the doped channel layer 160 is shown in Table 1, and the doping concentration is about 5e16 cm ^-3 .

Table 1 shows the channel cutoff voltage (Vk) of different widths W of the doped channel layer 160. The width W of the doped channel layer 160 is in micrometers (μm), and the unit of the input current tested is milliamperes (mA). In the experimental examples #1 to #13, the temperature coefficient (TC) is in the range of 0.000% to -0.050%, showing good thermal stability; the channel cutoff voltage (Vk) decreases with the increase of the channel width, showing an inverse relationship.

It can be seen from the above that the semiconductor device according to the present invention has a low knee voltage and an excellent temperature coefficient.

Table 1 No. #1 #2 #3 #4 #5 #6 #7 #8 #9 #10 #11 #12 #13 Channel Width 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 2.8 2.6 Current (25℃) 40 42 45 49 53 57 62 68 74 83 94 107 120 Current (75℃) 40 43 46 49 54 58 63 68 74 83 93 105 118 Current (125℃) 40 42 45 48 53 57 62 67 73 81 91 102 114 TC 0.000% 0.000% 0.000% -0.020% 0.000% 0.000% 0.000% -0.015% -0.014% -0.024% -0.032% -0.047% -0.050% VB 240 240 220 240 250 260 260 250 260 240 210 210 200 VK 1.2 1.4 1.4 1.6 1.6 2 2 2.2 2.2 2.2 2.2 2.4 2.8

100: semiconductor device 110: substrate 111: top surface 112: bottom surface 120: drift layer 121: upper surface 130: first doped region 140: second doped region 150: third doped region 160: doped channel layer 170: gate insulating layer 181: gate contact 182: source contact 183: drain contact D1: depth D2: depth T: thickness W: width J: junction field effect transistor region CH: channel region PN1: first p-n junction PN2: second p-n junction E1, E2, E3, E4, E5, E6, E7, E8, E9, E10, E11, C1, C2, C3, C4, C5: Curve

『Fig. 1』 is a cross-sectional view of a semiconductor device of an embodiment of the present invention. 『Fig. 2』 is an I-V curve characteristic of an experimental example of the present invention. 『Fig. 3』 is an I-V curve characteristic of an experimental example of the present invention. 『Fig. 4』 is an I-V curve characteristic of an experimental example and a comparative example of the present invention. 『Fig. 5A』 is an I-V curve characteristic of an experimental example of the present invention. 『Fig. 5B』 is an I-V curve characteristic of a comparative example of the present invention.

100:Semiconductor devices

110: Substrate

111: Top

112: Bottom

120: Drift layer

121: Upper surface

130: First mixed area

140: Second mixed area

150: The third mixed area

160: Doped channel layer

170: Gate insulation layer

181: Gate contact

182: Source contact

183: Drain contact

D1: Depth

D2: Depth

T:Thickness

W: Width

J: Junction field effect transistor region

CH: Channel area

PN1: first p-n junction

PN2: Second p-n junction

Claims (9)

A semiconductor device comprises: a drift layer disposed on a substrate, the drift layer having a first conductivity type and an upper surface; a plurality of first doped regions disposed in the drift layer adjacent to the upper surface and spaced apart from each other, the first doped regions having a second conductivity type opposite to the first conductivity type, the first doped regions and the drift layer forming a plurality of first pn junctions, a junction field effect transistor region being defined between adjacent first doped regions, the first doped regions having a depth ranging from 3 μm to 5 μm, and a doping concentration ranging from 8e16 cm ^-3 to 2e15 cm ^-3 ; a plurality of second doped regions disposed in the first doped region, the second doped regions having the first conductivity type, the second doped regions forming a plurality of second pn junctions with the first doped region, and defining a plurality of channel regions between the first pn junctions and the second pn junctions along the upper surface, the second doped regions having a depth ranging from 0.4 μm to 1 μm, and a doping concentration ranging from 2e19 cm ^-3 to 2e17 cm ^-3 ; a plurality of third doped regions disposed in the second doped region, the third doped regions having the second conductivity type; a doped channel layer disposed adjacent to the upper surface and extending across the drift layer between the second doped regions, the doped channel layer having a thickness ranging between 75 Å and 90 Å, a doping concentration ranging between 1e17 cm ^-3 and 1e16 cm ^-3 , and a width ranging between 1 μm and 6 μm; a gate insulating layer disposed on the upper surface, the gate insulating layer extending over the junction field effect transistor region, the channel regions, and a portion of the second doped regions; a gate contact contacting the gate insulating layer; and a source contact contacting the second doped regions and the third doped regions. The semiconductor device of claim 1 further comprises a drain contact contacting a bottom surface of the substrate. The semiconductor device as claimed in claim 1, wherein a knee voltage of the semiconductor device is adjusted as the thickness of the doped channel layer changes. A semiconductor device as described in claim 1, wherein a peak current of the semiconductor device is adjusted as the thickness of the doped channel layer changes. A semiconductor device as described in claim 1, wherein a temperature coefficient of the semiconductor device is adjusted as the thickness of the doped channel layer changes. A semiconductor device as described in claim 1, wherein the semiconductor device has a peak current greater than 500 mA. A semiconductor device as described in claim 1, wherein the semiconductor device has a temperature coefficient between -0.01% and +0.01%. A semiconductor device as described in claim 1, wherein the semiconductor device is configured as a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). A constant current diode circuit comprises a semiconductor device as described in any one of claims 1 to 7.

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